MC68HC708MP16CFU

Manufacturer Part NumberMC68HC708MP16CFU
ManufacturerFreescale Semiconductor, Inc
MC68HC708MP16CFU datasheet
 


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Page 116/398:

CGM Registers

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Clock Generator Module (CGM)
8.5.8 CGM CPU Interrupt (CGMINT)
CGMINT is the interrupt signal generated by the PLL lock detector.
8.6 CGM Registers
The following registers control and monitor operation of the CGM:
Figure 8-4
PCTL
$FE0B
Read:
Write:
PBWC
$FE0C
Read:
Write:
PPG
$FE0D
Read:
Write:
NOTES:
1. When AUTO = 0, PLLIE is forced to logic 0 and is read-only.
2. When AUTO = 0, PLLF and LOCK read as logic 0.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic 0 and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Technical Data
116
PLL control register (PCTL) (See
PLL bandwidth control register (PBWC) (See
Bandwidth Control
Register.)
PLL programming register (PPG) ((See
Register.)
is a summary of the CGM registers.
Bit 7
6
5
4
PLLF
PLLIE
PLLON
BCS
Bit 7
6
5
4
LOCK
AUTO
ACQ
XLD
Bit 7
6
5
4
MUL7
MUL6
MUL5
MUL4
= Unimplemented
Figure 8-4. CGM I/O Register Summary
Clock Generator Module (CGM)
8.6.1 PLL Control
Register.)
8.6.2 PLL
8.6.3 PLL Programming
3
2
1
Bit 0
1
1
1
1
3
2
1
Bit 0
0
0
0
0
3
2
1
Bit 0
VRS7
VRS6
VRS5
VRS4
MC68HC708MP16
Rev. 3.1
Freescale Semiconductor