MC68HC708MP16CFU

Manufacturer Part NumberMC68HC708MP16CFU
ManufacturerFreescale Semiconductor, Inc
MC68HC708MP16CFU datasheet
 
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Page 117/398:

PLL Control Register

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8.6.1 PLL Control Register
The PLL control register contains the interrupt enable and flag bits, the
on/off switch, the base clock selector bit.
Address:
Read:
Write:
Reset:
PLLIE — PLL Interrupt Enable Bit
This read/write bit enables the PLL to generate an interrupt request
when the LOCK bit toggles, setting the PLL flag, PLLF. When the
AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE
bit.
PLLF — PLL Interrupt Flag Bit
This read-only bit is set whenever the LOCK bit toggles. PLLF
generates an interrupt request if the PLLIE bit also is set. PLLF
always reads as logic 0 when the AUTO bit in the PLL bandwidth
control register (PBWC) is clear. Clear the PLLF bit by reading the
PLL control register. Reset clears the PLLF bit.
NOTE:
Do not inadvertently clear the PLLF bit. Any read or read-modify-write
operation on the PLL control register clears the PLLF bit.
MC68HC708MP16
Rev. 3.1
Freescale Semiconductor
$FE0B
Bit 7
6
5
PLLF
PILLIE
PLLON
0
0
1
= Unimplemented
Figure 8-5. PLL Control Register (PCTL)
1 = PLL interrupts enabled
0 = PLL interrupts disabled
1 = Change in lock condition
0 = No change in lock condition
Clock Generator Module (CGM)
Clock Generator Module (CGM)
4
3
2
1
1
1
1
BCS
1
1
1
0
Technical Data
Bit 0
1
1
117