MC68HC708MP16CFU

Manufacturer Part NumberMC68HC708MP16CFU
ManufacturerFreescale Semiconductor, Inc
MC68HC708MP16CFU datasheet
 
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Page 119/398:

PLL Bandwidth Control Register

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8.6.2 PLL Bandwidth Control Register
The PLL bandwidth control register does the following:
Address:
Read:
Write:
Reset:
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control.
When initializing the PLL for manual operation (AUTO = 0), clear the
ACQ bit before turning on the PLL. Reset clears the AUTO bit.
LOCK — Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set
when the VCO clock, CGMVCLK, is locked (running at the
programmed frequency). When the AUTO bit is clear, LOCK reads as
logic 0 and has no meaning. Reset clears the LOCK bit.
MC68HC708MP16
Rev. 3.1
Freescale Semiconductor
Selects automatic or manual (software-controlled) bandwidth
control mode
Indicates when the PLL is locked
In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
In manual operation, forces the PLL into acquisition or tracking
mode.
$FE0C
Bit 7
6
5
LOCK
AUTO
ACQ
0
0
0
= Unimplemented
Figure 8-6. PLL Bandwidth Control Register (PBWC)
1 = Automatic bandwidth control
0 = Manual bandwidth control
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
Clock Generator Module (CGM)
Clock Generator Module (CGM)
4
3
2
1
0
0
0
XLD
0
0
0
0
Technical Data
Bit 0
0
0
119