MC68HC708MP16CFU

Manufacturer Part NumberMC68HC708MP16CFU
ManufacturerFreescale Semiconductor, Inc
MC68HC708MP16CFU datasheet
 


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Page 139/398:

Figure and

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To prevent a partial reload of PWM parameters from occurring while the
software is still calculating them, an interlock bit controlled from software
is provided. This bit informs the PWM module that all the PWM
parameters have been calculated, and it is “okay” to use them. A new
modulus, prescaler, and/or PWM value cannot be loaded into the PWM
module until the LDOK bit in PWM control register 1 is set. When the
LDOK bit is set, these new values are loaded into a second set of
registers and used by the PWM generator at the beginning of the next
PWM reload cycle as shown in
Figure
NOTE:
When the PWM module is enabled (via the PWMEN bit), a load will occur
if the LDOK bit is set. Even if it is not set, an interrupt will occur if the
PWMINT bit is set. To prevent this, the software should clear the
PWMINT bit before enabling the PWM module.
MC68HC708MP16
Rev. 3.1
Freescale Semiconductor
Pulse Width Modulator for Motor Control (PWMMC)
Pulse Width Modulator for Motor Control (PWMMC)
V
DD
RESET
D
LATCH
PWM RELOAD
CK
Figure 9-6. PWM Interrupt Requests
Figure
9-10. After these values are loaded, the LDOK bit is cleared.
READ PWMF AS 1,
WRITE PWMF AS 0
OR
RESET
PWMF
CPU INTERRUPT
REQUEST
PWMINT
9-7,
Figure
9-8,
Figure
9-9, and
Technical Data
139