MC68HC708MP16CFU

Manufacturer Part NumberMC68HC708MP16CFU
ManufacturerFreescale Semiconductor, Inc
MC68HC708MP16CFU datasheet
 


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Page 158/398:

Output Port Control

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Pulse Width Modulator for Motor Control (PWMMC)
9.6.5 Output Port Control
Conditions may arise in which the PWM pins need to be individually
controlled. This is made possible by the PWM output control register
(PWMOUT) shown in
$0025
Read:
Write:
Reset:
If the OUTCTL bit is set, the PWM pins can be controlled by the OUTx
bits. These bits behave according to
OUTx Bit
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
When OUTCTL is set, the polarity options TOPPOL and BOTPOL will
still affect the outputs. In addition, if complementary operation is in use,
the PWM pairs will not be allowed to be active simultaneously, and dead-
time will still not be violated. When OUTCTL is set and complimentary
operation is in use, the odd OUTx bits are inputs to the dead-time
generators as shown in
Technical Data
158
Pulse Width Modulator for Motor Control (PWMMC)
Figure
9-28.
Bit 7
6
5
4
0
OUTCTL
OUT6
OUT5
0
0
0
0
= Unimplemented
Figure 9-28. PWM Output Control Register (PWMOUT)
Table 9-7. OUTx Bits
Complementary Mode
1 — PWM1 is active
0 — PWM1 is inactive
1 — PWM2 is complement of PWM 1
0 — PWM2 is inactive
1 — PWM3 is active
0 — PWM3 is inactive
1 — PWM4 is complement of PWM 3
0 — PWM4 is inactive
1 — PWM5 is active
0 — PWM5 is inactive
1 — PWM 6 is complement of PWM 5
0 — PWM6 is inactive
Figure
9-13. Dead-time is inserted whenever
3
2
1
Bit 0
OUT4
OUT3
OUT2
OUT1
0
0
0
Table
9-7.
Independent Mode
1 — PWM1 is active
0 — PWM1 is inactive
1 — PWM2 is active
0 — PWM2 is inactive
1 — PWM3 is active
0 — PWM3 is inactive
1 — PWM4 is active
0 — PWM4 is inactive
1 — PWM5 is active
0 — PWM5 is inactive
1 — PWM6 is active
0 — PWM6 is inactive
MC68HC708MP16
Rev. 3.1
Freescale Semiconductor
0