MC68HC708MP16CFU Freescale Semiconductor, Inc, MC68HC708MP16CFU Datasheet - Page 20

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MC68HC708MP16CFU

Manufacturer Part Number
MC68HC708MP16CFU
Description
Manufacturer
Freescale Semiconductor, Inc
Datasheet
List of Figures
Figure
7-12
7-13
7-14
7-15
7-16
7-17
8-1
8-2
8-3
8-4
8-5
8-6
8-7
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
9-17
9-18
9-19
9-20
9-21
Technical Data
20
Title
Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Wait Recovery from Interrupt or Break. . . . . . . . . . . . . . . . . 98
Wait Recovery from Internal Reset . . . . . . . . . . . . . . . . . . . 98
SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . 99
SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . 101
SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . 102
CGM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
CGM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . .107
CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . 114
CGM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . .116
PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . 117
PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . . 119
PLL Programming Register (PPG) . . . . . . . . . . . . . . . . . . . 121
PWM Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 131
PWMMC Register Summary . . . . . . . . . . . . . . . . . . . . . . .132
Center-Aligned PWM (Positive Polarity). . . . . . . . . . . . . . . 135
Edge-Aligned PWM (Positive Polarity) . . . . . . . . . . . . . . . . 136
Reload Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . 138
PWM Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Center-Aligned PWM Value Loading . . . . . . . . . . . . . . . . . 140
Center-Aligned Loading of Modulus . . . . . . . . . . . . . . . . . . 140
Edge-Aligned PWM Value Loading . . . . . . . . . . . . . . . . . . 141
Edge-Aligned Modulus Loading . . . . . . . . . . . . . . . . . . . . . 141
Complementary Pairing . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Typical AC Motor Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Dead-Time Generators. . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Effects of Dead-Time Insertion. . . . . . . . . . . . . . . . . . . . . . 147
Dead-Time at Duty Cycle Boundaries . . . . . . . . . . . . . . . . 147
Dead-Time and Small Pulse Widths. . . . . . . . . . . . . . . . . . 148
Current Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
Deadtime Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
Sinusoidal Distortion of Load Voltage . . . . . . . . . . . . . . . . 150
Internal Correction Logic when ISENS[1:0] = 0X . . . . . . . . 152
Output Voltage Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 153
List of Figures
Page
MC68HC708MP16
Rev. 3.1
Freescale Semiconductor

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