MC68HC708MP16CFU Freescale Semiconductor, Inc, MC68HC708MP16CFU Datasheet - Page 231

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MC68HC708MP16CFU

Manufacturer Part Number
MC68HC708MP16CFU
Description
Manufacturer
Freescale Semiconductor, Inc
Datasheet
compare value may cause the compare to be missed. The TIMB may
pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the
output compare value on channel x:
12.4.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare
channel whose output appears on the PTE4/TCH0B pin. The TIMB
channel registers of the linked pair alternately control the output.
Setting the MS0B bit in TIMB channel 0 status and control register
(TBSC0) links channel 0 and channel 1. The output compare value in the
TIMB channel 0 registers initially controls the output on the
PTE4/TCH0B pin. Writing to the TIMB channel 1 registers enables the
TIMB channel 1 registers to synchronously control the output after the
TIMB overflows. At each subsequent overflow, the TIMB channel
registers (0 or 1) that control the output are the ones written to last.
TBSC0 controls and monitors the buffered output compare function, and
TIMB channel 1 status and control register (TBSC1) is unused. While the
MS0B bit is set, the channel 1 pin, PTE5/TCH1B, is available as a
general-purpose I/O pin.
MC68HC708MP16
Rev. 3.1
Freescale Semiconductor
When changing to a smaller value, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current output compare pulse. The interrupt routine has until
the end of the counter overflow period to write the new value.
When changing to a larger output compare value, enable channel
x TIMB overflow interrupts and write the new value in the TIMB
overflow interrupt routine. The TIMB overflow interrupt occurs at
the end of the current counter overflow period. Writing a larger
value in an output compare interrupt routine (at the end of the
current pulse) could cause two output compares to occur in the
same counter overflow period.
Timer Interface Module B (TIMB)
Timer Interface Module B (TIMB)
Technical Data
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