MC68HC708MP16CFU

Manufacturer Part NumberMC68HC708MP16CFU
ManufacturerFreescale Semiconductor, Inc
MC68HC708MP16CFU datasheet
 
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Page 263/398:

Queuing Transmission Data

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13.7 Queuing Transmission Data
The double-buffered transmit data register allows a data byte to be
queued and transmitted. For an SPI configured as a master, a queued
data byte is transmitted immediately after the previous transmission has
completed. The SPI transmitter empty flag (SPTE) indicates when the
transmit data buffer is ready to accept new data. Write to the transmit
data register only when the SPTE bit is high.
timing associated with doing back-to-back transmissions with the SPI
(SPSCK has CPHA: CPOL = 1:0).
WRITE TO SPDR
(CPHA:CPOL = 1:0)
1
2
3
4 FIRST INCOMING BYTE TRANSFERS FROM SHIFT
5
6 CPU READS SPSCR WITH SPRF BIT SET.
The transmit data buffer allows back-to-back transmissions without the
slave precisely timing its writes between transmissions as in a system
with a single data buffer. Also, if no new data is written to the data buffer,
the last value contained in the shift register is the next data word to be
transmitted.
MC68HC708MP16
Rev. 3.1
Freescale Semiconductor
1
3
SPTE
2
SPSCK
MOSI
MSB BIT
BIT
6
5
BYTE 1
SPRF
READ SPSCR
READ SPDR
CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT.
BYTE 1 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2
AND CLEARING SPTE BIT.
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
Figure 13-8. SPRF/SPTE CPU Interrupt Timing
Serial Peripheral Interface Module (SPI)
Serial Peripheral Interface Module (SPI)
Figure 13-8
8
5
BIT
BIT
BIT
BIT
LSB MSB BIT
BIT
BIT
BIT
BIT
4
3
2
1
6
5
4
3
2
BYTE 2
4
6
7
7 CPU READS SPDR, CLEARING SPRF BIT.
8
CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE
3 AND CLEARING SPTE BIT.
9
SECOND INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
10
BYTE 3 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
11 CPU READS SPSCR WITH SPRF BIT SET.
12 CPU READS SPDR, CLEARING SPRF BIT.
shows the
10
BIT
LSB MSB BIT
BIT
BIT
1
6
5
4
BYTE 3
9
11
12
Technical Data
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