MC68HC708MP16CFU

Manufacturer Part NumberMC68HC708MP16CFU
ManufacturerFreescale Semiconductor, Inc
MC68HC708MP16CFU datasheet
 


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Page 265/398

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OVRF generates a receiver/error CPU interrupt request if the error
interrupt enable bit (ERRIE) is also set. When the DMAS bit is low, the
SPRF, MODF, and OVRF interrupts share the same CPU interrupt
vector. (See
individually to generate a receiver/error CPU interrupt request. However,
leaving MODFEN low prevents MODF from being set.
If the CPU SPRF interrupt is enabled and the OVRF interrupt is not,
watch for an overflow condition.
miss an overflow. The first part of
to read the SPSCR and SPDR to clear the SPRF without problems.
However, as illustrated by the second transmission example, the OVRF
bit can be set in between the time that SPSCR and SPDR are read.
SPRF
OVRF
READ
SPSCR
READ
SPDR
MC68HC708MP16
Rev. 3.1
Freescale Semiconductor
Figure
13-11.) It is not possible to enable MODF or OVRF
Figure 13-9
BYTE 1
BYTE 2
1
4
2
3
1
BYTE 1 SETS SPRF BIT.
2
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
3
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
4
BYTE 2 SETS SPRF BIT.
Figure 13-9. Missed Read of Overflow Condition
Serial Peripheral Interface Module (SPI)
Serial Peripheral Interface Module (SPI)
shows how it is possible to
Figure 13-9
shows how it is possible
BYTE 3
BYTE 4
6
8
5
7
5
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
6
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
7
CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT,
BUT NOT OVRF BIT.
8
BYTE 4 FAILS TO SET SPRF BIT BECAUSE
OVRF BIT IS NOT CLEARED. BYTE 4 IS LOST.
Technical Data
265