MC68HC708MP16CFU

Manufacturer Part NumberMC68HC708MP16CFU
ManufacturerFreescale Semiconductor, Inc
MC68HC708MP16CFU datasheet
 
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Page 275/398:

SPI Status and Control

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MISO/MOSI
MASTER SS
SLAVE SS
(CPHA = 0)
SLAVE SS
(CPHA = 1)
When an SPI is configured as a slave, the SS pin is always configured
as an input. It cannot be used as a general purpose I/O regardless of the
state of the MODFEN control bit. However, the MODFEN bit can still
prevent the state of the SS from creating a MODF error. (See

SPI Status and Control

NOTE:
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high-
impedance state. The slave SPI ignores all incoming SPSCK clocks,
even if it was already in the middle of a transmission.
When an SPI is configured as a master, the SS input can be used in
conjunction with the MODF flag to prevent multiple masters from driving
MOSI and SPSCK. (See
SS pin to set the MODF flag, the MODFEN bit in the SPSCK register
must be set. If the MODFEN bit is low for an SPI master, the SS pin can
be used as a general purpose I/O under the control of the data direction
register of the shared I/O port. With MODFEN high, it is an input-only pin
to the SPI regardless of the state of the data direction register of the
shared I/O port.
The CPU can always read the state of the SS pin by configuring the
appropriate pin as an input and reading the port data register. (See
Table
MC68HC708MP16
Rev. 3.1
Freescale Semiconductor
BYTE 1
Figure 13-12. CPHA/SS Timing
Register.)
13.8.2 Mode Fault
13-3.)
Serial Peripheral Interface Module (SPI)
Serial Peripheral Interface Module (SPI)
BYTE 2
BYTE 3
13.14.2
Error.) For the state of the
Technical Data
275