MC68HC708MP16CFU

Manufacturer Part NumberMC68HC708MP16CFU
ManufacturerFreescale Semiconductor, Inc
MC68HC708MP16CFU datasheet
 
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Page 341/398

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The external interrupt pins are falling-edge-triggered and are software-
configurable to be both falling-edge and low-level-triggered. The
MODE1 bit in the ISCR controls the triggering sensitivity of the IRQ1/V
pin.
When the interrupt pin is edge-triggered only, the interrupt latch remains
set until a vector fetch, software clear, or reset occurs.
When the interrupt pin is both falling-edge and low-level-triggered, the
interrupt latch remains set until both of the following occur:
The vector fetch or software clear can occur before or after the interrupt
pin returns to logic 1. As long as the pin is low, the interrupt request
remains pending.
When set, the IMASK1 bit in the ISCR mask all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the IMASK bit is clear.
NOTE:
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
(See
MC68HC708MP16
Rev. 3.1
Freescale Semiconductor
Vector fetch, software clear, or reset
Return of the interrupt pin to logic 1
Figure
17-3.)
External Interrupt (IRQ)
External Interrupt (IRQ)
PP
Technical Data
341