MC68HC708MP16CFU

Manufacturer Part NumberMC68HC708MP16CFU
ManufacturerFreescale Semiconductor, Inc
MC68HC708MP16CFU datasheet
 


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N O N - D I S C L O S U R E
Bit Manipulation
Branch
DIR
DIR
REL
DIR
INH
MSB
0
1
2
3
4
LSB
5
4
3
4
1
0
BRSET0
BSET0
BRA
NEG
NEGA
3
DIR
2
DIR
2
REL
2
DIR
1
INH
5
4
3
5
4
1
BRCLR0
BCLR0
BRN
CBEQ
CBEQA
3
DIR
2
DIR
2
REL
3
DIR
3
IMM
5
4
3
5
2
BRSET1
BSET1
BHI
MUL
3
DIR
2
DIR
2
REL
1
INH
5
4
3
4
1
3
BRCLR1
BCLR1
BLS
COM
COMA
3
DIR
2
DIR
2
REL
2
DIR
1
INH
5
4
3
4
1
4
BRSET2
BSET2
BCC
LSR
LSRA
3
DIR
2
DIR
2
REL
2
DIR
1
INH
5
4
3
4
3
5
BRCLR2
BCLR2
BCS
STHX
LDHX
3
DIR
2
DIR
2
REL
2
DIR
3
IMM
5
4
3
4
1
6
BRSET3
BSET3
BNE
ROR
RORA
3
DIR
2
DIR
2
REL
2
DIR
1
INH
5
4
3
4
1
7
BRCLR3
BCLR3
BEQ
ASR
ASRA
3
DIR
2
DIR
2
REL
2
DIR
1
INH
5
4
3
4
1
8
BRSET4
BSET4
BHCC
LSL
LSLA
3
DIR
2
DIR
2
REL
2
DIR
1
INH
5
4
3
4
1
9
BRCLR4
BCLR4
BHCS
ROL
ROLA
3
DIR
2
DIR
2
REL
2
DIR
1
INH
5
4
3
4
1
A
BRSET5
BSET5
BPL
DEC
DECA
3
DIR
2
DIR
2
REL
2
DIR
1
INH
5
4
3
5
3
B
BRCLR5
BCLR5
BMI
DBNZ
DBNZA
3
DIR
2
DIR
2
REL
3
DIR
2
INH
5
4
3
4
1
C
BRSET6
BSET6
BMC
INC
INCA
3
DIR
2
DIR
2
REL
2
DIR
1
INH
5
4
3
3
1
D
BRCLR6
BCLR6
BMS
TST
TSTA
3
DIR
2
DIR
2
REL
2
DIR
1
INH
5
4
3
5
E
BRSET7
BSET7
BIL
MOV
3
DIR
2
DIR
2
REL
3
DD
5
4
3
3
1
F
BRCLR7
BCLR7
BIH
CLR
CLRA
3
DIR
2
DIR
2
REL
2
DIR
1
INH
INH Inherent
REL Relative
SP1 Stack Pointer, 8-Bit Offset
IMM Immediate
IX
Indexed, No Offset
SP2 Stack Pointer, 16-Bit Offset
DIR Direct
IX1
Indexed, 8-Bit Offset
IX+
EXT Extended
IX2
Indexed, 16-Bit Offset
DD
Direct-Direct
IMD Immediate-Direct
IX1+ Indexed, 1-Byte Offset with
IX+D Indexed-Direct
DIX+ Direct-Indexed
*
Pre-byte for stack pointer indexed instructions
A G R E E M E N T
Table 6-2. Opcode Map
Read-Modify-Write
Control
INH
IX1
SP1
IX
INH
INH
IMM
5
6
9E6
7
8
9
1
4
5
3
7
3
NEGX
NEG
NEG
NEG
RTI
BGE
SUB
1
INH
2
IX1
3
SP1
1
IX
1
INH
2
REL
2
4
5
6
4
4
3
CBEQX
CBEQ
CBEQ
CBEQ
RTS
BLT
CMP
3
IMM
3
IX1+
4
SP1
2
IX+
1
INH
2
REL
2
7
3
2
3
DIV
NSA
DAA
BGT
SBC
1
INH
1
INH
1
INH
2
REL
2
1
4
5
3
9
3
COMX
COM
COM
COM
SWI
BLE
CPX
1
INH
2
IX1
3
SP1
1
IX
1
INH
2
REL
2
1
4
5
3
2
2
LSRX
LSR
LSR
LSR
TAP
TXS
AND
1
INH
2
IX1
3
SP1
1
IX
1
INH
1
INH
2
4
3
4
1
2
LDHX
CPHX
CPHX
TPA
TSX
2
DIR
3
IMM
2
DIR
1
INH
1
INH
2
1
4
5
3
2
RORX
ROR
ROR
ROR
PULA
LDA
1
INH
2
IX1
3
SP1
1
IX
1
INH
2
1
4
5
3
2
1
ASRX
ASR
ASR
ASR
PSHA
TAX
1
INH
2
IX1
3
SP1
1
IX
1
INH
1
INH
2
1
4
5
3
2
1
LSLX
LSL
LSL
LSL
PULX
CLC
EOR
1
INH
2
IX1
3
SP1
1
IX
1
INH
1
INH
2
1
4
5
3
2
1
ROLX
ROL
ROL
ROL
PSHX
SEC
ADC
1
INH
2
IX1
3
SP1
1
IX
1
INH
1
INH
2
1
4
5
3
2
2
DECX
DEC
DEC
DEC
PULH
CLI
ORA
1
INH
2
IX1
3
SP1
1
IX
1
INH
1
INH
2
3
5
6
4
2
2
DBNZX
DBNZ
DBNZ
DBNZ
PSHH
SEI
ADD
2
INH
3
IX1
4
SP1
2
IX
1
INH
1
INH
2
1
4
5
3
1
1
INCX
INC
INC
INC
CLRH
RSP
1
INH
2
IX1
3
SP1
1
IX
1
INH
1
INH
1
3
4
2
1
TSTX
TST
TST
TST
NOP
BSR
1
INH
2
IX1
3
SP1
1
IX
1
INH
2
4
4
4
1
MOV
MOV
MOV
STOP
LDX
*
2
DIX+
3
IMD
2 IX+D
1
INH
2
1
3
4
2
1
1
CLRX
CLR
CLR
CLR
WAIT
TXA
1
INH
2
IX1
3
SP1
1
IX
1
INH
1
INH
2
Indexed, No Offset with
Post Increment
Low Byte of Opcode in Hexadecimal
Post Increment
R E Q U I R E D
Register/Memory
DIR
EXT
IX2
SP2
IX1
SP1
A
B
C
D
9ED
E
9EE
2
3
4
4
5
3
4
SUB
SUB
SUB
SUB
SUB
SUB
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
2
3
4
4
5
3
4
CMP
CMP
CMP
CMP
CMP
CMP
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
2
3
4
4
5
3
4
SBC
SBC
SBC
SBC
SBC
SBC
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
2
3
4
4
5
3
4
CPX
CPX
CPX
CPX
CPX
CPX
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
2
3
4
4
5
3
4
AND
AND
AND
AND
AND
AND
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
2
3
4
4
5
3
4
BIT
BIT
BIT
BIT
BIT
BIT
BIT
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
2
3
4
4
5
3
4
LDA
LDA
LDA
LDA
LDA
LDA
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
2
3
4
4
5
3
4
AIS
STA
STA
STA
STA
STA
STA
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
2
3
4
4
5
3
4
EOR
EOR
EOR
EOR
EOR
EOR
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
2
3
4
4
5
3
4
ADC
ADC
ADC
ADC
ADC
ADC
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
2
3
4
4
5
3
ORA
ORA
ORA
ORA
ORA
ORA
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
2
3
4
4
5
3
ADD
ADD
ADD
ADD
ADD
ADD
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
2
3
4
3
JMP
JMP
JMP
JMP
2
DIR
3
EXT
3
IX2
2
IX1
4
4
5
6
5
JSR
JSR
JSR
JSR
REL
2
DIR
3
EXT
3
IX2
2
IX1
2
3
4
4
5
3
4
LDX
LDX
LDX
LDX
LDX
LDX
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
2
3
4
4
5
3
4
AIX
STX
STX
STX
STX
STX
STX
IMM
2
DIR
3
EXT
3
IX2
4
SP2
2
IX1
3
SP1
MSB
0
High Byte of Opcode in Hexadecimal
LSB
5
Cycles
0
BRSET0
Opcode Mnemonic
3
DIR
Number of Bytes / Addressing Mode
IX
F
2
SUB
1
IX
2
CMP
1
IX
2
SBC
1
IX
2
CPX
1
IX
2
AND
1
IX
2
BIT
1
IX
2
LDA
1
IX
2
STA
1
IX
2
EOR
1
IX
2
ADC
1
IX
4
2
ORA
1
IX
4
2
ADD
1
IX
2
JMP
1
IX
4
JSR
1
IX
2
LDX
1
IX
2
STX
1
IX