MC68HC708MP16CFU

Manufacturer Part NumberMC68HC708MP16CFU
ManufacturerFreescale Semiconductor, Inc
MC68HC708MP16CFU datasheet
 


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Page 90/398

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System Integration Module (SIM)
7.4.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
SIM reset status register (SRSR). The SIM actively pulls down the RST
pin for all internal reset sources.
To prevent a COP module timeout, write any value to location $FFFF.
Writing to location $FFFF clears the COP counter and bits 12 through 4
of the SIM counter. The SIM counter output, which occurs at least every
13
2
– 2
serviced as soon as possible out of reset to guarantee the maximum
amount of time before the first timeout.
The COP module is disabled if the RST pin or the IRQ1/V
at V
DD
disabled only through combinational logic conditioned with the high
voltage signal on the RST or the IRQ1/V
from becoming disabled as a result of external noise. During a break
state, V
7.4.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
Because the MC68HC708MP16 has stop mode disabled, execution of
the STOP instruction will cause an illegal opcode reset.
7.4.2.4 Illegal Address Reset
An opcode fetch from addresses other than EPROM or RAM addresses
generates an illegal address reset. The SIM verifies that the CPU is
fetching an opcode prior to asserting the ILAD bit in the SIM reset status
register (SRSR) and resetting the MCU. A data fetch from an unmapped
address does not generate a reset.
Technical Data
90
4
CGMXCLK cycles, drives the COP counter. The COP should be
+ V
while the MCU is in monitor mode. The COP module can be
HI
+ V
on the RST pin disables the COP module.
DD
HI
System Integration Module (SIM)
pin is held
PP
pin. This prevents the COP
PP
MC68HC708MP16
Rev. 3.1
Freescale Semiconductor