OR3T20-7S208 Agere Systems, OR3T20-7S208 Datasheet

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OR3T20-7S208

Manufacturer Part Number
OR3T20-7S208
Description
ORCA feild-programmable gate array. Voltage 3.3 V.
Manufacturer
Agere Systems
Datasheet
June 1999
Table 1. ORCA Series 3 (3C and 3T) FPGAs
‡ The system gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs.
Features
The logic-only gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per
PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch,
output logic, CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing
a 32 x 4 RAM (or 512 gates) per PFU.
High-performance, cost-effective, 0.35 µm (OR3C) and
0.3 µm (OR3T) 4-level metal technology, (4- or 5-input
look-up table delay of 1.1 ns with -7 speed grade in
0.3 µm).
Same basic architecture as lower-voltage, advanced
process technology Series 3 architectures. (See ORCA
Series 3L FPGA documentation.)
Up to 186,000 usable gates.
Up to 452 user I/Os. (OR3Txxx I/Os are 5 V tolerant to
allow interconnection to both 3.3 V and 5 V devices,
selectable on a per-pin basis.)
Pin selectable I/O clamping diodes provide 5 V or 3.3 V
PCI compliance and 5 V tolerance on OR3Txxx devices.
Twin-quad programmable function unit (PFU) architec-
ture with eight 16-bit look-up tables (LUTs) per PFU,
organized in two nibbles for use in nibble- or byte-wide
functions. Allows for mixed arithmetic and logic functions
in a single PFU.
Nine user registers per PFU, one following each LUT,
plus one extra. All have programmable clock enable and
local set/reset, plus a global set/reset that can be dis-
abled per PFU.
Flexible input structure (FINS) of the PFUs provides a
routability enhancement for LUTs with shared inputs and
the logic flexibility of LUTs with independent inputs.
Fast-carry logic and routing to adjacent PFUs for nibble-,
byte-wide, or longer arithmetic functions, with the option
to register the PFU carry-out.
Softwired LUTs (SWL) allow fast cascading of up to
three levels of LUT logic in a single PFU for up to 40%
speed improvement.
Supplemental logic and interconnect cell (SLIC) provides
3-statable buffers, up to 10-bit decoder, and PAL *-like
AND-OR with optional INVERT in each programmable
OR3C/3T55
OR3C/3T80
OR3T125
OR3T20
OR3T30
Device
System
Gates
116K
186K
36K
48K
80K
LUTs
1152
1568
2592
3872
6272
Registers
1872
2436
3780
5412
8400
Max User RAM
Field-Programmable Gate Arrays
* PAL is a trademark of Advanced Micro Devices, Inc.
† IEEE is a registered trademark of The Institute of Electrical and
100K
18K
25K
42K
62K
Electronics Engineers, Inc.
logic cell (PLC), with over 50% speed improvement typi-
cal.
Abundant hierarchical routing resources based on rout-
ing two data nibbles and two control lines per set provide
for faster place and route implementations and less rout-
ing delay.
TTL or CMOS input levels programmable per pin for the
OR3Cxx (5.0 V) devices.
Individually programmable drive capability:
12 mA sink/6 mA source or 6 mA sink/3 mA source.
Built-in boundary scan ( IEEE
TS_ALL testability function to 3-state all I/O pins.
Enhanced system clock routing for low skew, high-speed
clocks originating on-chip or at any I/O.
Up to four ExpressCLK inputs allow extremely fast clock-
ing of signals on- and off-chip plus access to internal
general clock routing.
StopCLK feature to glitchlessly stop/start ExpressCLKs
independently by user command.
Programmable I/O (PIO) has:
— Fast-capture input latch and input flip-flop (FF) latch
— Capability to (de)multiplex I/O signals.
— Fast access to SLIC for decodes and PAL -like
— Output FF and two-signal function generator to
— Fast open-drain dive capability
— Capability to register 3-state enable signal.
Baseline FPGA family used in Series 3+ FPSCs (field
programmable system chips) which combine FPGA logic
and standard cell logic on one device.
for reduced input setup time and zero hold time.
functions.
reduce CLK to output propagation delay.
ORCA
User I/Os
196
228
292
356
452
®
Series 3C and 3T
Array Size
28 x 28
12 x 12
14 x 14
18 x 18
22 x 22
1149.1 JTAG) and
0.3 µm/4 LM
0.3 µm/4 LM
0.3 µm/4 LM
0.3 µm/4 LM
0.3 µm/4 LM
Technology
Process

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OR3T20-7S208 Summary of contents

Page 1

... Supplemental logic and interconnect cell (SLIC) provides 3-statable buffers 10-bit decoder, and PAL *-like AND-OR with optional INVERT in each programmable Table 1. ORCA Series 3 (3C and 3T) FPGAs System Device LUTs ‡ Gates OR3T20 36K OR3T30 48K OR3C/3T55 80K OR3C/3T80 116K OR3T125 186K ‡ ...

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ORCA Series 3C and 3T FPGAs Contents Features ......................................................................1 System-Level Features................................................6 Description...................................................................7 FPGA Overview ........................................................7 PLC Logic ..................................................................7 PIC Logic ...................................................................8 System Features .......................................................8 Routing ......................................................................8 Configuration .............................................................8 ORCA Foundry Development System ......................9 Architecture .................................................................9 Programmable Logic Cells ........................................11 Programmable ...

Page 3

Data Sheet June 1999 Contents Package Coplanarity ...............................................196 Package Parasitics ..................................................196 Package Outline Diagrams......................................197 Terms and Definitions ...........................................197 208-Pin SQFP .......................................................198 208-Pin SQFP2 .....................................................199 240-Pin SQFP .......................................................200 240-Pin SQFP2 .....................................................201 256-Pin PBGA .......................................................202 352-Pin PBGA .......................................................203 432-Pin EBGA .......................................................204 600-Pin ...

Page 4

... OR3C/T80, and OR3T125 208-Pin SQFP/SQFP2 Pinout ............................................ 155 Table 71. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 240-Pin SQFP/SQFP2 Pinout ............................................ 161 Table 72. OR3T20, OR3T30, and OR3C/T55 256-Pin PBGA Pinout ............................................ 168 Table 73. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 352-Pin PBGA Pinout . 172 Table 74. OR3C/T80 and OR3T125 432-Pin EBGA Pinout ...

Page 5

Data Sheet June 1999 Contents Explicit Mode ........................................................... 90 Figure 54. Master Parallel Configuration Schematic 92 Figure 55. Master Serial Configuration Schematic ... 93 Figure 56. Asynchronous Peripheral Configuration .. 94 Figure 57. PowerPC /MPI Configuration Schematic .. 95 Figure ...

Page 6

ORCA Series 3C and 3T FPGAs System-Level Features System-level features reduce glue logic requirements and make a system on a chip possible. These features in the ORCA Series 3 include: Full PCI local bus compliance. Dual-use microprocessor interface (MPI) can ...

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Data Sheet June 1999 Description FPGA Overview The ORCA Series 3 FPGAs are a new generation of SRAM-based FPGAs built on the successful OR2C/ TxxA FPGA Series from Lucent Technologies Micro- electronics Group, with enhancements and innovations geared toward today’s ...

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ORCA Series 3C and 3T FPGAs Description (continued) PIC Logic Series 3 PIC addresses the demand for ever-increas- ing system clock speeds. Each PIC contains four pro- grammable inputs/outputs (PIOs) and routing resources. On the input side, each PIO contains ...

Page 9

Data Sheet June 1999 Description (continued) ORCA Foundry Development System The ORCA Foundry Development System is used to process a design from a netlist to a configured FPGA. This system is used to map a design onto the ORCA architecture ...

Page 10

ORCA Series 3C and 3T FPGAs Architecture (continued) PT1 PT2 PT3 PT4 PT5 R1C1 R1C2 R1C3 R1C4 R1C5 R2C1 R2C2 R2C3 R2C4 R2C5 R3C1 R3C2 R3C3 R3C4 R3C5 R4C1 R4C2 R4C3 R4C4 R4C5 R5C1 R5C2 R5C3 R5C4 R5C5 R6C1 R6C2 ...

Page 11

Data Sheet June 1999 Programmable Logic Cells The programmable logic cell (PLC) consists of a pro- grammable function unit (PFU), a supplemental logic and interconnect cell (SLIC), and routing resources. All PLCs in the array are functionally identical with only ...

Page 12

ORCA Series 3C and 3T FPGAs Programmable Logic Cells F5D K7_0 K7_1 K7_2 K7_3 K6_0 K6_1 K6_2 K6_3 K5_0 K5_1 K5_2 K5_3 K4_0 K4_1 K4_2 K4_3 F5C CLK 0 SEL 0 CIN ASWE ...

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Data Sheet June 1999 Programmable Logic Cells Look-Up Table Operating Modes The operating mode affects the functionality of the PFU input and output ports and internal PFU routing. For exam- ple, in some operating modes, the DIN[7:0] inputs are direct ...

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ORCA Series 3C and 3T FPGAs Programmable Logic Cells Table 4. Control Input Functionality Mode CLK Logic CLK to all latches/ LSR to all latches/ FFs FFs, enabled per nib- ble and for ninth FF Half Logic/ CLK to all ...

Page 15

Data Sheet June 1999 Programmable Logic Cells Softwired LUT submode uses F4 and F5 LUTs and internal PFU feedback routing to generate complex logic func- tions up to three LUT-levels deep. Figure 3 shows multiplexers between the K LUTs. These ...

Page 16

ORCA Series 3C and 3T FPGAs Programmable Logic Cells Half-Logic Mode Series 3 FPGAs are based upon a twin-quad architec- ture in the PFUs. The byte-wide nature (eight LUTs, eight latches/FFs) may just as easily be viewed as two nibbles ...

Page 17

Data Sheet June 1999 Programmable Logic Cells The ripple mode can be used in one of four submodes. The first of these is adder-subtractor submode. In this submode, each LUT generates three separate out- puts. One of the three outputs ...

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ORCA Series 3C and 3T FPGAs Programmable Logic Cells In the third submode, multiplier submode, a single PFU can affect bit ( for half-ripple mode) multiply and sum with a partial product (see Figure ...

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Data Sheet June 1999 Programmable Logic Cells Memory Mode The Series 3 PFU can be used to implement (128-bit) synchronous, dual-port random access memory (RAM). A block diagram of a PFU in memory mode is shown ...

Page 20

ORCA Series 3C and 3T FPGAs Programmable Logic Cells Data is written to the write data, write address, and write enable registers on the active edge of the clock, but data is not written into the RAM until the next ...

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Data Sheet June 1999 Programmable Logic Cells Supplemental Logic and Interconnect Cell (SLIC) Each PLC contains a supplemental logic and intercon- nect cell (SLIC) embedded within the PLC routing, out- side of the PFU. As its name indicates, the SLIC ...

Page 22

ORCA Series 3C and 3T FPGAs Programmable Logic Cells BRI9 BL09 I9 BR09 BLI9 BRI8 BL08 I8 BR08 BLI8 BRI7 BL07 I7 BR07 BLI7 BRI6 BL06 I6 BR06 BLI6 BRI5 BL05 I5 BR05 BLI5 BRI4 BL04 I4 BR04 BLI4 TRI ...

Page 23

Data Sheet June 1999 Programmable Logic Cells BRI9 BLI9 BRI8 BLI8 BRI7 BL07 I7 BR07 BLI7 BRI6 BL06 I6 BR06 BLI6 BRI5 BL05 I5 BR05 BLI5 BRI4 BL04 I4 BR04 BLI4 1 HIGH Z TRI WHEN LOW 1 1 HIGH ...

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ORCA Series 3C and 3T FPGAs Programmable Logic Cells BRI9 BLI9 BRI8 BLI8 BRI7 BLI7 BRI6 BLI6 BRI5 BLI5 BRI4 BLI4 TRI 1 HIGH Z WHEN LOW 1 BRI3 BL03 I3 BR03 BLI3 BRI2 BL02 I2 BR02 BLI2 BRI1 BL01 ...

Page 25

Data Sheet June 1999 Programmable Logic Cells PLC Latches/Flip-Flops The eight general-purpose latches/FFs in the PFU can be used in a variety of configurations. In some cases, the configuration options apply to all eight latches/FFs in the PFU and some ...

Page 26

ORCA Series 3C and 3T FPGAs Programmable Logic Cells The GSRN signal is only asynchronous, and it sets/ resets all latches/FFs in the FPGA based upon the set/ reset configuration bit for each latch/FF. The set/reset value determines whether GSRN ...

Page 27

Data Sheet June 1999 Programmable Logic Cells PLC Routing Resources Generally, the ORCA Foundry Development System is used to automatically route interconnections. Interac- tive routing with the ORCA Foundry design editor (EPIC) is also available for design optimization. To use ...

Page 28

ORCA Series 3C and 3T FPGAs Programmable Logic Cells General Routing Structure Routing resources in Series 3 FPGAs generally consist of routing segments in groups of ten, with varying lengths and connectivity to logic and other routing resources. The varying ...

Page 29

Data Sheet June 1999 Programmable Logic Cells Intra-PLC Routing The function of the intra-PLC routing resources is to connect the PFU’s input and output ports to the routing resources used for entry to and exit from the PLC. This routing ...

Page 30

ORCA Series 3C and 3T FPGAs Programmable Logic Cells BIDI Routing and SLIC Connectivity The SLIC is connected to the rest of the PLC by the bidirectional (BIDI) routing segments and the PFU out- put switching segments coming from the ...

Page 31

Data Sheet June 1999 Programmable Logic Cells Inter-PLC Routing Resources The inter-PLC routing is used to route signals between PLCs. The routing segments occur in groups of ten, and differ in the numbers of PLCs spanned. The x1 routing segments ...

Page 32

ORCA Series 3C and 3T FPGAs Programmable Logic Cells 10 PFU 2 SLIC PFU 2 SLIC PFU 2 SLIC 2 10 KEY: CONFIGURABLE SIGNAL-LINE BREAKS: LINE-BY-LINE PLC BOUNDARY Figure ...

Page 33

Data Sheet June 1999 Programmable Logic Cells xL Routing Lines. The xL routing lines run vertically and horizontally the height and width of the array, respectively. There are a total routing lines per PLC: ten horizontal (hxL[9:0]) ...

Page 34

ORCA Series 3C and 3T FPGAs Programmable Logic Cells PLC Architectural Description Figure architectural drawing of the PLC (as seen in ORCA Foundry) that reflects the PFU, the rout- ing segments, and the CIPs. A discussion of ...

Page 35

Data Sheet June 1999 Programmable Logic Cells SLIC Lucent Technologies Inc. (continued ...

Page 36

ORCA Series 3C and 3T FPGAs Programmable Input/Output Cells The programmable input/output cells (PICs) are located along the perimeter of the device. The PIC’s name is represented by a two-letter designation to indi- cate on which side of the device ...

Page 37

Data Sheet June 1999 Programmable Input/Output Cells (continued) Table 9. PIO Options Input Input Level TTL, OR3Cxx only CMOS, OR3Cxx or OR3Txxx 3.3 V PCI Compliant, OR3Txxx 5 V PCI Compliant, OR3Txxx Input Speed Fast, Delayed Float Value Pull-up, Pull-down, ...

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ORCA Series 3C and 3T FPGAs Programmable Input/Output Cells (continued) Inputs As outlined earlier in Table 9, there are six major options on the PIO inputs that can be selected in the ORCA Foundry tools. For OR3Cxx devices, the inputs ...

Page 39

Data Sheet June 1999 Programmable Input/Output Cells Zero-Hold Input There are two options for zero-hold input capture in the PIO. If input delay mode is selected to delay the signal from the input pin, data can be either registered or ...

Page 40

ORCA Series 3C and 3T FPGAs Programmable Input/Output Cells Input Demultiplexing The combination of input register capability and the two inputs, IN1 and IN2, from each PIO to the internal routing provides for input signal demultiplexing without any additional resources. ...

Page 41

Data Sheet June 1999 Programmable Input/Output Cells (continued) Outputs The PIC’s output drivers have programmable drive capability and slew rates. Three propagation delays (fast, slewlim, sinklim) are available on output drivers. The sinklim mode has the longest propagation delay and ...

Page 42

ORCA Series 3C and 3T FPGAs Programmable Input/Output Cells ADDRESS FROM ROUTING ROUTING CLK OUT1 OUT2 PIC OUTPUT Figure 25. Output Multiplexing (OUT1OUT2 Mode) PLC ADDRESS FROM ROUTING CLK DATA FROM ROUTING CLK ADDR ADDR1 DATA REG ADDRESS PAD Figure ...

Page 43

Data Sheet June 1999 Programmable Input/Output Cells (continued) PIO Logic Function Generator The PIO logic block can also generate logic functions based on the signals on the OUT2 and CLK ports of the PIO. The functions are AND, NAND, OR, ...

Page 44

ORCA Series 3C and 3T FPGAs Programmable Input/Output Cells (continued) PIC Routing Resources The PIC routing borrows many of the concepts and constructs from the PLC routing designed to be able to gather an 8-bit bidirectional bus from ...

Page 45

Data Sheet June 1999 Programmable Input/Output Cells (continued) PIC Architectural Description The PIC architecture as seen in ORCA Foundry is shown in Figure 27. The figure is the left PIC of a PIC pair on the top edge of a ...

Page 46

ORCA Series 3C and 3T FPGAs Programmable Input/Output Cells 46 (continued) Figure 27. PIC Architecture Data Sheet June 1999 5-5823(F) Lucent Technologies Inc. ...

Page 47

Data Sheet June 1999 High-Level Routing Resources The high-level routing resources in the ORCA Series 3 devices are interquad routing, corner cell routing, and PIC interquad routing. These resources and their related structures are discussed in the following subsections. Interquad ...

Page 48

ORCA Series 3C and 3T FPGAs High-Level Routing Resources Figure 29 shows the connections from the interquad routing to the inter-PLC routing for a block of the hori- zontal interquad. The vertical interquad has similar connections. The connections shown in ...

Page 49

Data Sheet June 1999 High-Level Routing Resources PIC Interquad (MID) Routing There is also connectivity between the PICs in each quadrant, as well as a clock control (CLKCNTRL) mod- ule (discussed in the Special Function Blocks section) between the PIC ...

Page 50

ORCA Series 3C and 3T FPGAs Clock Distribution Network The Series 3 FPGAs provide three types of high- speed, low-skew clock distributions: system clock, fast middle clock (fast clock), and ExpressCLK . Because of the great variety of sources and ...

Page 51

Data Sheet June 1999 Clock Distribution Network Clock Distribution in the PLC Array System Clock (SCLK) The clock distribution network, or clock spine network, within the PLC array is designed to minimize clock skew while maximizing clock flexibility. Clock flexibility ...

Page 52

ORCA Series 3C and 3T FPGAs Clock Distribution Network Clock Sources to the PLC Array The source of a clock that is globally available to the PLC array can be from any user I/O pad, any of the ExpressCLK pads, ...

Page 53

Data Sheet June 1999 Clock Distribution Network ExpressCLK Inputs There are four dedicated ExpressCLK pads on each Series 3 device: one in the middle of each side. Two other user I/O pads can also be used as corner ExpressCLK inputs, ...

Page 54

ORCA Series 3C and 3T FPGAs Special Function Blocks Special function blocks in the Series 3 provide extra capabilities beyond general FPGA operation. These blocks reside in the corners and MIDs (middle inter- quad areas) of the FPGA array. Single ...

Page 55

Data Sheet June 1999 Special Function Blocks The readback frame contains the configuration data and the state of the internal logic. During readback, the value of all registered PFU and PIC outputs can be captured. The following options are allowed ...

Page 56

ORCA Series 3C and 3T FPGAs Special Function Blocks Start-Up Logic The start-up logic block is located in the lower right cor- ner of the FPGA. This block can be configured to coor- dinate the relative timing of the release ...

Page 57

Data Sheet June 1999 Special Function Blocks Boundary Scan The increasing complexity of integrated circuits (ICs) and IC packages has increased the difficulty of testing printed-circuit boards (PCBs). To address this testing problem, the IEEE standard 1149.1/D1 ( IEEE Standard ...

Page 58

ORCA Series 3C and 3T FPGAs Special Function Blocks D[7:0] D[7:0] CE MICRO- PROCESSOR RA R/W DAV INTR INT SP The boundary-scan support circuit shown in Figure 37 is the 497AA Boundary-Scan Master (BSM). The BSM off-loads tasks from the ...

Page 59

... The SAMPLE/PRELOAD instruction is useful for sys- tem debugging and fault diagnosis by allowing the data at the FPGA’s I/ observed during normal Table 14. Boundary-Scan ID Code Version Part* Device (4 bits) (10 bits) OR3T20 0000 0011000000 110000 OR3T30 0000 0111000000 110000 OR3C/T55 0000 0100100000 110000 ...

Page 60

ORCA Series 3C and 3T FPGAs Special Function Blocks ORCA Boundary-Scan Circuitry The ORCA Series boundary-scan circuitry includes a test access port controller (TAPC), instruction register (IR), boundary-scan register (BSR), and bypass regis- ter. It also includes circuitry to support ...

Page 61

Data Sheet June 1999 Special Function Blocks ORCA Series TAP Controller (TAPC) The ORCA Series TAP controller (TAPC 1149.1/ D1 compatible test access port controller. The 16 JTAG state assignments from the IEEE 1149.1/D1 specifica- tion are used. ...

Page 62

ORCA Series 3C and 3T FPGAs Special Function Blocks Boundary-Scan Cells Figure diagram of the boundary-scan cell (BSC) in the ORCA series PICs. There are four BSCs in each PIC: one for each pad, except as noted ...

Page 63

Data Sheet June 1999 Special Function Blocks Boundary-Scan Timing To ensure race-free operation, data changes on specific clock edges. The TMS and TDI inputs are clocked in on the rising edge of TCK, while changes on TDO occur on the ...

Page 64

ORCA Series 3C and 3T FPGAs Microprocessor Interface (MPI) The Series 3 FPGAs have a dedicated synchronous microprocessor interface function block (see Figure 42). The MPI is programmable to operate with PowerPC MPC800 series microprocessors and Intel * i960 * ...

Page 65

Data Sheet June 1999 Microprocessor Interface (MPI) PowerPC System In Figure 43, the ORCA FPGA is a memory-mapped peripheral to the PowerPC processor. The PowerPC interface uses separate address and data buses and has several control lines. The ORCA chip ...

Page 66

ORCA Series 3C and 3T FPGAs Microprocessor Interface (MPI) i960 System Figure 44 shows a schematic for connecting the ORCA MPI to supported i960 processors. In the figure, the FPGA is shown as the only peripheral, with the FPGA chip ...

Page 67

Data Sheet June 1999 Microprocessor Interface (MPI) MPI Interface to FPGA The MPI interfaces to the user-programmable FPGA logic using a 4-bit address, read/write control signal, interrupt request signal, and user start and user end handshake signals. Timing numbers are ...

Page 68

ORCA Series 3C and 3T FPGAs Microprocessor Interface (MPI) MPI Setup and Control The MPI has a series of addressable registers that provide MPI control and status, configuration and readback data transfer, FPGA device identification, and a dedicated user scratchpad ...

Page 69

Data Sheet June 1999 Microprocessor Interface (MPI) Scratchpad Register The MPI scratchpad register is an 8-bit read/write register with no defined operation. It may be used for any user- defined function. Control Register 2 The MPI control register 2 is ...

Page 70

ORCA Series 3C and 3T FPGAs Microprocessor Interface (MPI) Status Register The microprocessor interface status register is a read-only register, providing information to the host processor. Table 22 . Status Register Bit # Reserved. Bit 0 Bit 1 Data Ready. ...

Page 71

... Example: (First version of Lucent’s OR3C55) * PLC array size of FPGA. Table 24 shows the family and device values for all parts covered by this data sheet. Table 24. Series 3 Family and Device ID Values Family ID Part Name (Hex) OR3T20 03 OR3T30 03 OR3C/T55 03 OR3C/T80 03 OR3T125 ...

Page 72

ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) The ORCA programmable clock manager ( PCM ) is a special function block that is used to modify or condi- tion clock signals for optimum system performance. Some of the ...

Page 73

Data Sheet June 1999 Programmable Clock Manager (PCM) PCM Registers The PCM contains eight user-programmable registers used for configuring the PCM ’s functionality. Table 26 shows the mapping of the registers and their functions. See Figure 46 for more information ...

Page 74

ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) INPUT CLOCK 0 EXPRESSCLK PAD PROGRAMMABLE 1 S0 DIVIDER FROM 2 DIV0 ROUTING 3 REGISTER 7 REGISTER 6 REGISTER 5 REGISTER 4 REGISTER 3 REGISTER 2 REGISTER 1 REGISTER 0 ...

Page 75

Data Sheet June 1999 Programmable Clock Manager (PCM) (continued) Delay-Locked Loop (DLL) Mode DLL mode is used for implementing a delayed clock (phase adjustment), clock doubling, and duty cycle adjustment. All DLL functions stem from a delay line with 32 ...

Page 76

ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) (continued) 2x Clock Duty-Cycle Adjustment A doubled-frequency, duty-cycle adjusted version of the input clock can be constructed in DLL mode. The first clock cycle of the 2x clock output occurs ...

Page 77

Data Sheet June 1999 Programmable Clock Manager (PCM) (continued) Clock Multiplication An output clock that is a multiple (not necessarily an integer multiple) of the input clock can be generated in PLL mode. The multiplication ratio is programmed in the ...

Page 78

ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) (continued) Table 29. PCM Oscillator Frequency Range 3Txxx System Clock Output Frequency Register 4 Min (MHz) 76543210 (MHz) NOM 00XXX010 17.00 58.50 00XXX011 16.10 52.50 00XXX100 15.17 49.00 00XXX101 14.25 ...

Page 79

Data Sheet June 1999 Programmable Clock Manager (PCM) (continued) PCM/FPGA Internal Interface Writing and reading the PCM registers is done through a simple asynchronous interface that connects with the FPGA routing resources. Reads from the PCM by the FPGA logic ...

Page 80

ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) PCM Detailed Programming Descriptions of bit fields and individual control bits in the PCM control registers are provided in Table 31. Refer to Figure 46 for more information on the ...

Page 81

Data Sheet June 1999 Programmable Clock Manager (PCM) Table 31. PCM Control Registers (continued) Bit # Register 4—DLL 1x Duty-Cycle Programming Bits [2:0] Duty-Cycle/Delay Selection for Duty Cycle/Delays Less Than or Equal to 50%. The duty- cycle/delay is (value of ...

Page 82

ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) Table 31. PCM Control Registers (continued) Bit # Bits [5:4] ExpressCLK Output Source Selector. Default is 00. 00: PCM input clock, bypass path through PCM 01: DLL output 10: tapped ...

Page 83

Data Sheet June 1999 Programmable Clock Manager (PCM) (continued) PCM Applications The applications discussed below are only a small sampling of the possible uses for the PCM . Check the Lucent Technologies ORCA FPGA Internet website (listed at the end ...

Page 84

ORCA Series 3C and 3T FPGAs Programmable Clock Manager (PCM) (continued) High-Speed Internal Processing with Slow I/Os The PCM PLL mode provides two outputs, one sent to the global system clock routing of the FPGA and the other to the ...

Page 85

Data Sheet June 1999 FPGA States of Operation Prior to becoming operational, the FPGA goes through a sequence of states, including initialization, configura- tion, and start-up. Figure 49 outlines these three FPGA states. POWERUP – POWER-ON TIME DELAY INITIALIZATION – ...

Page 86

ORCA Series 3C and 3T FPGAs FPGA States of Operation If configuration has begun, an assertion of initiates an abort, returning the FPGA to the ini- PRGM tialization state. The and PRGM RESET pulled back high before the FPGA will ...

Page 87

Data Sheet June 1999 FPGA States of Operation Start-Up After configuration, the FPGA enters the start-up phase. This phase is the transition between the config- uration and operational states and begins when the number of CCLKs received after INIT to ...

Page 88

ORCA Series 3C and 3T FPGAs FPGA States of Operation CCLK_NOSYNC DONE I GSRN ACTIVE CCLK_SYNC DONE IN DONE C1, C2 ...

Page 89

Data Sheet June 1999 Configuration Data Format The ORCA Foundry Development System interfaces with front-end design entry tools and provides tools to produce a fully configured FPGA. This section dis- cusses using the ORCA Foundry Development System to generate configuration ...

Page 90

ORCA Series 3C and 3T FPGAs Configuration Data Format PREAMBLE LENGTH ID FRAME COUNT CONFIGURATION HEADER Figure 52. Serial Configuration Data Format—Autoincrement Mode PREAMBLE LENGTH ID FRAME COUNT CONFIGURATION HEADER Figure 53. ...

Page 91

... If using either of the MPI modes to configure the FPGA, the specific type of bit stream error is written to one of the MPI registers by the FPGA configuration logic. The out of the error condition and restart configuration. Lucent Technologies Inc. (continued) OR3T20 OR3T30 856 984 202 232 ...

Page 92

ORCA Series 3C and 3T FPGAs FPGA Configuration Modes There are eight methods for configuring the FPGA. Seven of the configuration modes are selected on the M0, M1, and M2 inputs. The eighth configuration mode is accessed through the boundary-scan ...

Page 93

Data Sheet June 1999 FPGA Configuration Modes Master Serial Mode In the master serial mode, the FPGA loads the configu- ration data from an external serial ROM. The configura- tion data is either loaded automatically at start- ...

Page 94

ORCA Series 3C and 3T FPGAs FPGA Configuration Modes Asynchronous Peripheral Mode Figure 56 shows the connections needed for the asyn- chronous peripheral mode. In this mode, the FPGA system interface is similar to that of a microprocessor- peripheral interface. ...

Page 95

Data Sheet June 1999 FPGA Configuration Modes There are two options for using the host interrupt request in configuration mode. The configuration con- trol register offers control bits to enable the interrupt on either a bit stream error or to ...

Page 96

ORCA Series 3C and 3T FPGAs FPGA Configuration Modes WRITE RD_CFG STOP CONTROL REGISTER 1 96 (continued) ENABLE MICROPROCESSOR INTERFACE IN USER MODE SET READBACK ADDRESS WRITE RD_CFG CONTROL REGISTER 1 READ STATUS REGISTER NO DATA_RDY = ...

Page 97

Data Sheet June 1999 FPGA Configuration Modes Slave Serial Mode The slave serial mode is primarily used when multiple FPGAs are configured in a daisy-chain (see the Daisy- Chaining section also used on the FPGA evalua- tion board ...

Page 98

ORCA Series 3C and 3T FPGAs FPGA Configuration Modes Daisy-Chaining Multiple FPGAs can be configured by using a daisy- chain of the FPGAs. Daisy-chaining uses a lead FPGA and one or more FPGAs configured in slave serial mode. The lead ...

Page 99

Data Sheet June 1999 FPGA Configuration Modes Daisy-Chaining with Boundary Scan Multiple FPGAs can be configured through the JTAG ports by using a daisy-chain of the FPGAs. This daisy-chain- ing operation is available upon initial configuration after powerup, after a ...

Page 100

ORCA Series 3C and 3T FPGAs Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at ...

Page 101

... OR3C/T55 OR3C/T80 internal oscillator running, no out- OR3T125 Standby Current: I DDSB OR3T20 OR3T30 OR3C/T55 OR3C/T80 OR3T125 Powerup Current: Ipp Power supply current @ approxi- OR3T20 mately 1 V, within a recommended OR3T30 OR3C/T55 OR3C/T80 OR3T125 Data Retention Voltage V DR Input Capacitance C IN Output Capacitance C OUT Lucent Technologies Inc. < ...

Page 102

ORCA Series 3C and 3T FPGAs Electrical Characteristics Table 37. Electrical Characteristics (continued) OR3Cxx Commercial 5.0 V ± 5%, 0 °C < OR3Txxx Commercial 3 3 °C < ...

Page 103

Data Sheet June 1999 Timing Characteristics Description To define speed grades, the ORCA Series part number designation (see Ordering Information) uses a single- digit number to designate a speed grade. This number is not related to any single ac parameter. ...

Page 104

ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) In addition to supply voltage, process variation, and operating temperature, circuit and process improve- ments of the ORCA Series FPGAs over time will result in significant improvement of the actual performance ...

Page 105

Data Sheet June 1999 Timing Characteristics (continued) K [3: [3:0], F5[A: [3: [3:0] Z F5[A:D] F5[A:D] Note: See Table 46 for an explanation of FDBK_DEL and OMUX_DEL. Lucent Technologies Inc. FDBK–DEL PFU F[7:0] F4_DEL ...

Page 106

ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 42. Sequential PFU Timing Characteristics OR3Cxx Commercial 5.0 V ± 5%, 0 °C < OR3Txxx Commercial 3 3 °C < ...

Page 107

Data Sheet June 1999 Timing Characteristics (continued) Table 43. Ripple Mode PFU Timing Characteristics OR3Cxx Commercial 5.0 V ± 5%, 0 °C < OR3Txxx Commercial 3 3 °C < T ...

Page 108

ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 43. Ripple Mode PFU Timing Characteristics (continued) OR3Cxx Commercial 5.0 V ± 5%, 0 °C < OR3Txxx Commercial 3 3 ...

Page 109

Data Sheet June 1999 Timing Characteristics (continued) Table 44. Synchronous Memory Write Characteristics OR3Cxx Commercial 5.0 V ± 5%, 0 °C DD OR3Txxx Commercial 3 3 °C DD Parameter Write Operation for ...

Page 110

ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 45. Synchronous Memory Read Characteristics OR3Cxx Commercial 5.0 V ± 5%, 0 °C DD OR3Txxx Commercial 3 3 °C DD Parameter (T ...

Page 111

Data Sheet June 1999 Timing Characteristics (continued) PLC Timing Table 46. PFU Output MUX and Direct Routing Timing Characteristics OR3Cxx Commercial 5.0 V ± 5%, 0 °C DD OR3Txxx Commercial 3 3 ...

Page 112

ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) PIO Timing Table 48. Programmable I/O (PIO) Timing Characteristics OR3Cxx Commercial 5.0 V ± 5%, 0 °C DD OR3Txxx Commercial 3 3 °C ...

Page 113

Data Sheet June 1999 Timing Characteristics (continued) Table 48. Programmable I/O (PIO) Timing Characteristics (continued) OR3Cxx Commercial 5.0 V ± 5%, 0 °C DD OR3Txxx Commercial 3 3 °C DD Parameter Output ...

Page 114

ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 48. Programmable I/O (PIO) Timing Characteristics (continued) OR3Cxx Commercial 5.0 V ± 5%, 0 °C DD OR3Txxx Commercial 3 3 °C DD ...

Page 115

Data Sheet June 1999 Timing Characteristics (continued) Special Function Blocks Timing Table 49. Microprocessor Interface (MP I) Timing Characteristics OR3Cxx Commercial 5.0 V ± 5%, 0 °C DD OR3Txxx Commercial 3 3 ...

Page 116

ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 49. Microprocessor Interface (MP I) Timing Characteristics (continued) OR3Cxx Commercial 5.0 V ± 5%, 0 °C DD OR3Txxx Commercial 3 3 °C ...

Page 117

Data Sheet June 1999 Timing Characteristics (continued) MPI_CLK A[4:0] MPI_RW (RD/WR) CS0, CS1 D[7:0] MPI_STRB (TS) UA[3:0] URDWRN USTART UEND MPI_ACK (TA) MPI_BI (BI) Figure 67. MPI PowerPC User Space Read Timing MPI_CLK A[4:0] MPI_RW (RD/WR) CS0, CS1 D[7:0] MPI_STRB ...

Page 118

ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) MPI_CLK A[4:0] MPI_RW (RD/WR) CS0, CS1 D[7:0] MPI_STRB (TS) UA[3:0] URDWRN MPI_ACK (TA) MPI_BI (BI) Figure 69. MPI PowerPC Internal Read Timing MPI_CLK A[4:0] MPI_RW (RD/WR) CS0, CS1 D[7:0] MPI_STRB (TS) ...

Page 119

Data Sheet June 1999 Timing Characteristics (continued) A_SET ADSN_SET RW_SET MPI_CLK D[7:0] MPI_RW (W/R) CS0, CS1 BE0, BE1 MPI_ALE (ALE) MPI_STRB (ADS) UA[3:0] URDWRN USTART UEND MPI_ACK (RDYRCV) Figure 71. MPI i960 User Space Read Timing CS_SET A_SET ADSN_SET RW_SET ...

Page 120

ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) A_SET ADSN_SET RW_SET MPI_CLK D[7:0] MPI_RW (W/R) CS0, CS1 BE0, BE1 MPI_ALE (ALE) MPI_STRB (ADS) UA[3:0] URDWRN MPI_ACK (RDYRCV) CS_SET A_SET ADSN_SET RW_SET MPI_CLK D[7:0] MPI_RW (W/R) CS0, CS1 MPI_ALE (ALE) ...

Page 121

Data Sheet June 1999 Timing Characteristics (continued) Table 50. Programmable Clock Manager ( PCM ) Timing Characteristics (Preliminary Information) OR3Cxx Commercial 5.0 V ± 5%, 0 ° OR3Txxx Commercial 3 3.6 V, ...

Page 122

ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 51. Boundary-Scan Timing Characteristics OR3Cxx Commercial 5.0 V ± 5%, 0 °C DD OR3Txxx Commercial 3 3 °C DD Parameter TDI/TMS to ...

Page 123

... FCLK Delay (middle pad): OR3T20 OR3T30 OR3C/T55 OR3C/T80 OR3T125 FCLK Delay (corner pad): OR3T20 OR3T30 OR3C/T55 OR3C/T80 OR3T125 Notes: The ECLK delays are to all of the PICs on one side of the device for middle pin input, or two sides of the device for corner pin input. The delay includes both the input buffer delay and the clock routing to the PIC clock input ...

Page 124

... DD OR3Txxx Commercial 3 3 °C DD Device Symbol ( ° min OR3T20 CLK_DEL OR3T30 CLK_DEL OR3C/T55 CLK_DEL OR3C/T80 CLK_DEL OR3T125 CLK_DEL Notes: This table represents the delay for an internally generated clock from the clock tree input in one of the four middle PICs (using pSW routing) on any side of the device which is then distributed to the PFU/PIO clock inputs ...

Page 125

... OR3C/T80 — 12.54 OR3T125 — — OR3T20 — — OR3T30 — — OR3C/T55 — 13.73 OR3C/T80 — 13.90 OR3T125 — — OR3T20 — — OR3T30 — — OR3C/T55 — 1.97 OR3C/T80 — 1.97 OR3T125 — — PIO OUTPUT (50 pF LOAD) CLKCNTRL ECLK Figure 76. ExpressCLK to Output Delay ORCA Series 3C and 3T FPGAs < ...

Page 126

... OR3T20 — — — OR3T30 — — — OR3C/T55 — 18.47 — OR3C/T80 — 19.10 — OR3T125 — — — OR3T20 — — — OR3T30 — — — OR3C/T55 — 2.10 — OR3C/T80 — 2.14 — OR3T125 — — — PIO ...

Page 127

... OR3T125 — — OR3T20 — — OR3T30 — — OR3C/T55 — 0.41 OR3C/T80 — 0.63 OR3T125 — — OR3T20 — — OR3T30 — — OR3C/T55 — 0.41 OR3C/T80 — 0.63 OR3T125 — — PIO OUTPUT (50 pF LOAD) Figure 78. System Clock to Output Delay ORCA Series 3C and 3T FPGAs < ...

Page 128

... OR3C/T55 0.00 — 0.00 OR3C/T80 0.00 — 0.00 OR3T125 — — 0.00 OR3T20 — — 4.39 OR3T30 — — 4.35 OR3C/T55 4.94 — 4.28 OR3C/T80 4.82 — 4.21 OR3T125 — — 4.10 OR3T20 — — 0.00 OR3T30 — — 0.00 OR3C/T55 0.00 — 0.00 OR3C/T80 0.00 — 0.00 OR3T125 — — 0.00 OR3T20 — — 0.00 OR3T30 — — 0.00 OR3C/T55 0.00 — 0.00 OR3C/T80 0 ...

Page 129

... Device -4 -5 Min Max Min OR3T20 — — 0.00 OR3T30 — — 0.00 OR3C/T55 0.00 — 0.00 OR3C/T80 0.00 — 0.00 OR3T125 — — 0.00 OR3T20 — — 0.00 OR3T30 — — 0.00 OR3C/T55 0.00 — 0.00 OR3C/T80 0.00 — 0.00 OR3T125 — — 0.00 PIO ECLK LATCH INPUT D CLKCNTRL CLK ECLK ORCA Series 3C and 3T FPGAs < ...

Page 130

... OR3C/T80 0.00 — 0.00 OR3T125 — — 0.00 OR3T20 — — 0.00 OR3T30 — — 0.00 OR3C/T55 0.00 — 0.00 OR3C/T80 0.00 — 0.00 OR3T125 — — 0.00 OR3T20 — — 4.29 OR3T30 — — 4.50 OR3C/T55 6.33 — 4.97 OR3C/T80 6.95 — 5.49 OR3T125 — — 6.36 Data Sheet June 1999 < < = 5.0 V ± 10%, –40 °C T +85 °C. A < ...

Page 131

... OR3C/T80 0.00 — 0.00 OR3T125 — — 0.00 OR3T20 — — 6.26 OR3T30 — — 6.49 OR3C/T55 8.43 — 6.98 OR3C/T80 9.09 — 7.53 OR3T125 — — 8.45 OR3T20 — — 0.00 OR3T30 — — 0.00 OR3C/T55 0.00 — 0.00 OR3C/T80 0.00 — 0.00 OR3T125 — — 0.00 INPUT D CLKCNTRL ECLK FCLK ORCA Series 3C and 3T FPGAs < < = 5.0 V ± 10%, –40 °C T +85 ° ...

Page 132

... OR3T30 — — 5.01 6.82 — 5.56 7.62 — 6.19 — — 7.07 OR3T20 — — 0.00 OR3T30 — — 0.00 0.00 — 0.00 0.00 — 0.00 — — 0.00 OR3T20 — — 0.16 OR3T30 — — 0.20 0.41 — 0.36 0.63 — 0.55 — — 1.11 PIO FF INPUT D SCLK Data Sheet June 1999 < < = 5.0 V ± 10%, –40 °C T +85 °C. A < ...

Page 133

... Partial Reconfiguration (explicit mode): OR3T20 OR3T30 OR3C/T55 OR3C/T80 OR3T125 Slave Serial Mode Power-on Reset Delay CCLK Period OR3Cxx OR3Txxx Configuration Latency (autoincrement mode): OR3T20 OR3T30 OR3C55 OR3T55 OR3C80 OR3T80 OR3T125 * Not applicable to asynchronous peripheral mode. Lucent Technologies Inc. ORCA Series 3C and 3T FPGAs < < ...

Page 134

... Slave Parallel Slave Serial Master Serial Master Parallel Initialization Latency ( high to PRGM OR3T20 OR3T30 OR3C/T55 OR3C/T80 OR3T125 High to , Asynchronous Peripheral INIT WR Note triggered when V reaches between 3 4.0 V for the OR3Cxx and between 2.7 V and 3.0 V for the OR3Txxx. ...

Page 135

Data Sheet June 1999 Timing Characteristics (continued PRGM INIT CCLK M[3:0] DONE Figure 82. General Configuration Mode Timing Diagram Lucent Technologies Inc INIT_CLK T HMODE T SMODE T CL ORCA ...

Page 136

ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 61 . Master Serial Configuration Mode Timing Characteristics OR3Cxx Commercial 5.0 V ± 5%, 0 °C DD OR3Txxx Commercial 3 3 °C ...

Page 137

Data Sheet June 1999 Timing Characteristics (continued) Table 62 . Master Parallel Configuration Mode Timing Characteristics OR3Cxx Commercial 5.0 V ± 5%, 0 °C DD OR3Txxx Commercial 3 3 °C DD Parameter ...

Page 138

ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 63 . Asynchronous Peripheral Configuration Mode Timing Characteristics OR3Cxx Commercial 5.0 V ± 5%, 0 °C DD OR3Txxx Commercial 3 3 °C ...

Page 139

Data Sheet June 1999 Timing Characteristics (continued) Table 64. Slave Serial Configuration Mode Timing Characteristics OR3Cxx Commercial 5.0 V ± 5%, 0 °C DD OR3Txxx Commercial 3 3 °C DD Parameter Symbol ...

Page 140

ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Table 65. Slave Parallel Configuration Mode Timing Characteristics OR3Cxx Commercial 5.0 V ± 5%, 0 °C DD OR3Txxx Commercial 3 3 °C DD ...

Page 141

Data Sheet June 1999 Timing Characteristics (continued) Microprocessor Interface (MPI) Configuration Timing Characteristics For configuration timing using the MPI, consult Table 49. See Figures 67 through 74 for MPI timing diagrams. Lucent Technologies Inc. ORCA Series 3C and 3T FPGAs ...

Page 142

ORCA Series 3C and 3T FPGAs Timing Characteristics (continued) Readback Timing Table 66 . Readback Timing Characteristics OR3Cxx Commercial 5.0 V ± 5%, 0 °C DD OR3Txxx Commercial 3 3 °C DD ...

Page 143

Data Sheet June 1999 Input/Output Buffer Measurement Conditions TO THE OUTPUT UNDER TEST A. Load Used to Measure Propagation Delay Note: Switch to V for switch to GND for T DD PLZ PZL out[i] out[i] PAD OUT ...

Page 144

ORCA Series 3C and 3T FPGAs Output Buffer Characteristics OR3Cxx OUTPUT VOLTAGE, V Figure 92. Sinklim ( ° 250 225 200 175 150 125 ...

Page 145

Data Sheet June 1999 Output Buffer Characteristics OR3Txxx 110 100 0.0 0.5 1.0 1.5 2.0 OUTPUT VOLTAGE, V Figure 98. Sinklim ( ° 140 120 100 ...

Page 146

ORCA Series 3C and 3T FPGAs Estimating Power Dissipation OR3Cxx The total operating power dissipated is estimated by summing the standby (I ), internal, and external DDSB power dissipated. The internal and external power is the power consumed in the ...

Page 147

... OR3T20 Clock Power P = [0.38 mW/MHz + (0.045 mW/MHz/Branch) (# Branches) + (0.015 mW/MHz/PFU) (# PFUs) + (0.004 mW/MHz/PIO (# PIOs)] For a quick estimate, the worst-case (typical circuit) OR3T20 clock power 2.92 mW/MHz. OR3T30 Clock Power P = [0.53 mW/MHz + (0.061 mW/MHz/Branch) (# Branches) + (0.015 mW/MHz/PFU) (# PFUs) + (0.004 mW/MHz/PIO (# PIOs)] For a quick estimate, the worst-case (typical circuit) OR3T30 clock power 3 ...

Page 148

ORCA Series 3C and 3T FPGAs Estimating Power Dissipation As an example of estimating power dissipation, suppose that a fully utilized OR3T80 has an average of six outputs for each of the 484 PFUs, that 12 clock branches are used ...

Page 149

Data Sheet June 1999 Pin Information Pin Descriptions This section describes the pins found on the Series 3 FPGAs. Any pin not described in this table is a user-program- mable I/O. During configuration, the user-programmable I/Os are 3-stated with an ...

Page 150

ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 67. Pin Descriptions (continued) Symbol I/O Special-Purpose Pins (continued During powerup and initialization used to select the speed of the internal oscillator dur- ing configuration with ...

Page 151

Data Sheet June 1999 Pin Information (continued) Table 67. Pin Descriptions (continued) Symbol I/O Special-Purpose Pins (continued) , CS1 I and CS1 are used in the asynchronous peripheral, slave parallel, and microprocessor CS0 CS0 configuration modes. The FPGA is selected ...

Page 152

ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 67. Pin Descriptions (continued) Symbol I/O Special-Purpose Pins (continued) A11/ O MPI active-low interrupt request output. MPI_IRQ After configuration, if the MPI is not used, this pin is a user-programmable ...

Page 153

... When a package pin left connect for a specific die indicated as a note in the device pad column for the FPGA. The tables provide no information on unused pads. Table 68. ORCA I/Os Summary 208-Pin Device SQFP/SQPF2 OR3T20 User I/Os* 171 ...

Page 154

ORCA Series 3C and 3T FPGAs Pin Information (continued) Compatibility with OR2C/TxxA Series The pinouts shown for the OR3Cxx and OR3Txxx devices are consistent with the OR2C/TxxA Series for all devices offered in the same packages. This includes the following ...

Page 155

... Data Sheet June 1999 Pin Information Pin Information (continued) (continued) Table 70. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 208-Pin SQFP/SQFP2 Pinout Table 70. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 208-Pin SQFP/SQFP2 Pinout OR3T20 OR3T20 OR3T30 OR3T30 Pin Pin Pad Pad ...

Page 156

... ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 70. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125, 208-Pin SQFP/SQFP2 Pinout (continued) OR3T20 OR3T30 Pin Pad PL10D 42 PL10C 43 PL10B PL21D 44 PL10A 45 PL11D 46 PL11A 47 PL12D 48 PL12C PL27D 49 PL12B 50 PL12A PCCLK PCCLK ...

Page 157

... Data Sheet June 1999 Pin Information (continued) Table 70. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 208-Pin SQFP/SQFP2 Pinout (continued) OR3T20 OR3T30 Pin Pad PECKB PECKB 81 PB7B 82 PB7C 83 PB7D PB8A 86 PB8B 87 PB8C 88 PB8D 89 PB9A 90 PB9B 91 PB9C 92 PB9D ...

Page 158

... ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 70. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 208-Pin SQFP/SQFP2 Pinout (continued) OR3T20 OR3T30 Pin Pad 118 PR9B PR19D 119 PR9C 120 PR9D PR18D 121 PR8A 122 PR8B PR17D 123 PR8C 124 PR8D PR16D 125 ...

Page 159

... Data Sheet June 1999 Pin Information (continued) Table 70. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 208-Pin SQFP/SQFP2 Pinout (continued) OR3T20 OR3T30 Pin Pad 157 V SS 158 V SS 159 PT12D 160 PT12A 161 PT11D 162 PT11C 163 PT11A 164 PT10D 165 PT10C 166 ...

Page 160

... ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 70. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 208-Pin SQFP/SQFP2 Pinout (continued) OR3T20 OR3T30 Pin Pad 197 PT3D 198 PT3C 199 PT3B 200 PT3A 201 PT2D 202 PT2A 203 PT1D 204 PT1C 205 PT1B 206 ...

Page 161

... Data Sheet June 1999 Pin Information (continued) Table 71. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 240-Pin SQFP/SQFP2 Pinout OR3T20 OR3T30 Pin Pad PL1D 4 PL1C 5 PL1B 6 PL1A PL2D 9 PL2C 10 PL2B 11 PL2A 12 PL3D 13 PL3C 14 PL3B 15 PL3A PL4D ...

Page 162

... ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 71. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 240-Pin SQFP/SQFP2 Pinout (continued) OR3T20 OR3T30 Pin Pad 40 PL9D 41 PL9C 42 PL9B 43 PL9A PL10D 46 PL10C 47 PL10B 48 PL10A 49 PL11D 50 PL11C 51 PL11B 52 PL11A PL12D 55 PL12C 56 PL12B ...

Page 163

... Data Sheet June 1999 Pin Information (continued) Table 71. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 240-Pin SQFP/SQFP2 Pinout (continued) OR3T20 OR3T30 Pin Pad 79 PB4C 80 PB4D 81 PB5A 82 PB5B 83 PB5C 84 PB5D PB6A 87 PB6B 88 PB6C 89 PB6D PECKB PECKB 92 PB7B 93 PB7C 94 PB7D ...

Page 164

... ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 71. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 240-Pin SQFP/SQFP2 Pinout (continued) OR3T20 OR3T30 Pin Pad 118 V SS 119 PDONE PDONE 120 V DD 121 V SS 122 PRESETN PRESETN 123 PPRGMN PPRGMN 124 PR12A 125 PR12B ...

Page 165

... Data Sheet June 1999 Pin Information (continued) Table 71. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 240-Pin SQFP/SQFP2 Pinout (continued) OR3T20 OR3T30 Pin Pad 157 PR5A 158 PR5B 159 PR5C 160 PR5D 161 PR4A 162 PR4B 163 PR4C 164 PR4D 165 V DD 166 ...

Page 166

... ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 71. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 240-Pin SQFP/SQFP2 Pinout (continued) OR3T20 OR3T30 Pin Pad 196 PT10A 197 V DD 198 PT9D 199 PT9C 200 PT9B 201 PT9A 202 PT8D 203 PT8C 204 PT8B 205 ...

Page 167

... Data Sheet June 1999 Pin Information (continued) Table 71. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 240-Pin SQFP/SQFP2 Pinout (continued) OR3T20 OR3T30 Pin Pad 235 PT1D 236 PT1C 237 PT1B 238 PT1A 239 V SS 240 PRD_DATA PRD_DATA Lucent Technologies Inc. OR3C/T55 OR3C/T80 Pad ...

Page 168

... ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 72. OR3T20, OR3T30, and OR3C/T55 256-Pin PBGA Pinout OR3T20 OR3T30 OR3C/T55 Pin Pad Pad PL1D PL1D D2 PL1C PL1B D3 PL1B PL1A E4 PL1A PL2D C1 — PL2C D1 — PL2B E3 — PL2A E2 PL2D PL3D E1 PL2C ...

Page 169

... Data Sheet June 1999 Pin Information (continued) Table 72. OR3T20, OR3T30, and OR3C/T55 256-Pin PBGA Pinout (continued) OR3T20 OR3T30 OR3C/T55 Pin Pad Pad W11 PECKB PECKB PECKB V11 PB7B PB8B PB10B U11 PB7C PB8C PB10C Y12 PB7D PB8D PB10D W12 PB8A PB9A ...

Page 170

... ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 72. OR3T20, OR3T30, and OR3C/T55 256-Pin PBGA Pinout (continued) OR3T20 OR3T30 OR3C/T55 Pin Pad Pad B20 — PR1B C18 — PR1C B19 — PR1D A20 PRD_CFGN PRD_CFGN PRD_CFGN A19 PT12D PT14D B18 — PT14C ...

Page 171

... Data Sheet June 1999 Pin Information (continued) Table 72. OR3T20, OR3T30, and OR3C/T55 256-Pin PBGA Pinout (continued) OR3T20 OR3T30 OR3C/T55 Pin Pad Pad M10 M11 M12 D11 D15 ...

Page 172

... ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 73. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 352-Pin PBGA Pinout OR3T20 OR3T30 Pin Pad PL1D B1 C2 — C1 PL1C D2 PL1B D3 PL1A D1 — E2 — E4 — E3 — E1 PL2D F2 — G4 PL2C F3 — F1 PL2B G2 — G1 — G3 PL2A H2 — J4 — ...

Page 173

... Data Sheet June 1999 Pin Information (continued) Table 73. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 352-Pin PBGA Pinout (continued) OR3T20 OR3T30 Pin Pad P3 PL8C R1 PL8B T2 PL8A R3 PL9D T1 PL9C R4 PL9B U2 PL9A T3 PL10D U1 — U4 PL10C V2 — U3 PL10B V1 — W2 PL10A W1 — V3 PL11D Y2 PL11C W4 PL11B Y1 — ...

Page 174

... ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 73. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 352-Pin PBGA Pinout (continued) OR3T20 OR3T30 Pin Pad AF5 — AE6 — AC7 — AD6 PB2A AF6 — AE7 — AF7 — AD7 — AE8 — AC9 ...

Page 175

... Data Sheet June 1999 Pin Information (continued) Table 73. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 352-Pin PBGA Pinout (continued) OR3T20 OR3T30 Pin Pad AC17 PB10B AE18 PB10C AD17 PB10D AF18 — AE19 — AF19 — AD18 PB11A AE20 — AC19 — AF20 — ...

Page 176

... ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 73. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 352-Pin PBGA Pinout (continued) OR3T20 OR3T30 Pin Pad W25 PR10A PR11A V23 PR10B PR11B W26 — W24 — V25 PR10C PR11C V26 PR10D PR11D U25 — V24 — ...

Page 177

... Data Sheet June 1999 Pin Information (continued) Table 73. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 352-Pin PBGA Pinout (continued) OR3T20 OR3T30 Pin Pad H23 PR2B G26 — H24 PR2C F25 PR2D G23 — F26 — G24 — E25 PR1A E26 PR1B F24 — ...

Page 178

... ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 73. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 352-Pin PBGA Pinout (continued) OR3T20 OR3T30 Pin Pad C18 PT9D A17 PT9C PT10D D17 — PT10C B16 PT9B C17 PT9A A16 PT8D B15 PT8C A15 PT8B C16 ...

Page 179

... Data Sheet June 1999 Pin Information (continued) Table 73. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 352-Pin PBGA Pinout (continued) OR3T20 OR3T30 Pin Pad B5 PT1D A5 PT1C C6 — B4 — D5 PT1B A4 — C5 — B3 — C4 PT1A A3 PRD_DATA PRD_DATA A26 V SS AC13 V SS AC18 ...

Page 180

... ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 73. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 352-Pin PBGA Pinout (continued) OR3T20 OR3T30 Pin Pad L11 V SS L12 V SS L13 V SS L14 V SS L15 V SS L16 V SS M11 V SS M12 V SS M13 V SS M14 ...

Page 181

... Data Sheet June 1999 Pin Information (continued) Table 73. OR3T20, OR3T30, OR3C/T55, OR3C/T80, and OR3T125 352-Pin PBGA Pinout (continued) OR3T20 OR3T30 Pin Pad D11 V DD D16 V DD D21 F23 L23 T23 *Thermally enhanced connection. ...

Page 182

ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 74. OR3C/T80 and OR3T125 432-Pin EBGA Pinout OR3C/T80 OR3T125 Pin Pad Pad E4 PRD_CFGN PRD_CFGN D3 PR1D PR1D D2 PR1C PR1C D1 PR1B PR1B F4 PR1A PR1A E3 PR2D PR2D ...

Page 183

Data Sheet June 1999 Pin Information (continued) Table 74. OR3C/T80 and OR3T125 432-Pin EBGA Pinout (continued) OR3C/T80 OR3T125 Pin Pad Pad AJ5 PB21D PB27D AK5 PB21C PB27C AL5 PB21B PB27B AJ6 PB21A PB27A AK6 PB20D PB26D AL6 PB20C PB26C AH8 ...

Page 184

ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 74. OR3C/T80 and OR3T125 432-Pin EBGA Pinout (continued) OR3C/T80 OR3T125 Pin Pad Pad AF31 PL20B PL26B AD28 PL20C PL26C AE29 PL20D PL26D AE30 PL19A PL25A AE31 PL19B PL25B AC28 PL19C ...

Page 185

Data Sheet June 1999 Pin Information (continued) Table 74. OR3C/T80 and OR3T125 432-Pin EBGA Pinout (continued) OR3C/T80 OR3T125 Pin Pad Pad D23 PT4C PT4C C24 PT4D PT4D B24 PT5A PT5A C23 PT5B PT5B D22 PT5C PT5C B23 PT5D PT5D A23 ...

Page 186

ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 74. OR3C/T80 and OR3T125 432-Pin EBGA Pinout (continued) OR3C/T80 OR3T125 Pin Pad Pad AL16 AL2 AL20 AL24 V ...

Page 187

Data Sheet June 1999 Pin Information (continued) Table 75. OR3T125 600-Pin EBGA Pinout OR3T125 Pin Pad E4 PRD_CFGN E3 PR1D E2 PR1C F5 PR1B F4 PR1A F3 PR2D F2 PR2C G5 PR2B G4 PR2A G3 PR3D G2 PR3C H5 PR3B ...

Page 188

ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 75. OR3T125 600-Pin EBGA Pinout (continued) OR3T125 Pin Pad AF3 PR23A AF4 PR24D AF5 PR24C AG1 PR24B AG2 PR24A AG3 PR25D AG4 PR25C AG5 PR25B AH2 PR25A AH3 PR26D AH4 ...

Page 189

Data Sheet June 1999 Pin Information (continued) Table 75. OR3T125 600-Pin EBGA Pinout (continued) OR3T125 Pin Pad AN21 PB12A AM21 PB11D AL21 PB11C AR22 PB11B AP22 PB11A AN22 PB10D AM22 PB10C AL22 PB10B AP23 PB10A AN23 PB9D AM23 PB9C AL23 ...

Page 190

ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 75. OR3T125 600-Pin EBGA Pinout (continued) OR3T125 Pin Pad AA34 PL17A AA35 PL17B Y32 PL17C Y33 PL17D Y34 PL16A W34 PL16B W32 PL16C W31 PL16D I/O-A9/ W33 PL15A I/O-A8/MPI_RW W35 ...

Page 191

Data Sheet June 1999 Pin Information (continued) Table 75. OR3T125 600-Pin EBGA Pinout (continued) OR3T125 Pin Pad B26 PT6B A26 PT6C D25 PT6D C25 PT7A B25 PT7B A25 PT7C E24 PT7D D24 PT8A C24 PT8B B24 PT8C A24 PT8D E23 ...

Page 192

ORCA Series 3C and 3T FPGAs Pin Information (continued) Table 75. OR3T125 600-Pin EBGA Pinout (continued) OR3T125 Pin Pad A13 V SS A16 V SS A20 V SS A23 V SS A28 V SS A29 ...

Page 193

Data Sheet June 1999 Pin Information (continued) Table 75. OR3T125 600-Pin EBGA Pinout (continued) OR3T125 Pin Pad AL35 V DD AL5 V DD AM32 V DD AM4 V DD AN3 V DD AN33 V DD AP1 V DD AP2 V ...

Page 194

ORCA Series 3C and 3T FPGAs Package Thermal Characteristics There are four thermal parameters that are in common use should be noted that all JA JC, JC, and JB , the parameters are affected, to varying degrees, by ...

Page 195

Data Sheet June 1999 Package Thermal Characteristics FPGA Maximum Junction Temperature Once the power dissipated by the FPGA has been determined (see the Estimating Power Dissipation section), the maximum junction temperature of the FPGA can be found. This is needed ...

Page 196

ORCA Series 3C and 3T FPGAs Package Coplanarity The coplanarity limits of the ORCA Series 3 packages are as follows. Table 77. Package Coplanarity Coplanarity Limit Package Type EBGA PBGA SQFP/SQFP2 Package Parasitics The electrical performance package, ...

Page 197

Data Sheet June 1999 Package Outline Diagrams Terms and Definitions Basic Size (BSC): The basic size of a dimension is the size from which the limits for that dimension are derived by the application of the allowance and the tolerance. ...

Page 198

ORCA Series 3C and 3T FPGAs Package Outline Diagrams 208-Pin SQFP Dimensions are in millimeters. 30.60 ± 0.20 28.00 ± 0.20 PIN #1 IDENTIFIER ZONE 208 DETAIL A 0.50 TYP Note: The dimensions in this outline diagram ...

Page 199

Data Sheet June 1999 Package Outline Diagrams 208-Pin SQFP2 Dimensions are in millimeters. 30.60 0.20 28.00 0.20 21.0 REF PIN #1 IDENTIFIER ZONE 208 53 EXPOSED HEAT SINK APPEARS ON BOTTOM SURFACE: CHIP BONDED FACE UP. (SEE DETAIL C.) DETAIL ...

Page 200

ORCA Series 3C and 3T FPGAs Package Outline Diagrams 240-Pin SQFP Dimensions are in millimeters. 34.60 ± 0.20 32.00 ± 0.20 PIN #1 IDENTIFIER ZONE 240 DETAIL A 0.50 TYP Note: The dimensions in this outline diagram ...

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