CS8412-CP Cirrus Logic, Inc., CS8412-CP Datasheet

no-image

CS8412-CP

Manufacturer Part Number
CS8412-CP
Description
Digital audio interface receiver
Manufacturer
Cirrus Logic, Inc.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS8412-CP
Manufacturer:
FSC
Quantity:
6 218
Part Number:
CS8412-CP
Manufacturer:
CRYSTAL
Quantity:
367
Part Number:
CS8412-CP
Manufacturer:
CS
Quantity:
20 000
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
Features
l
l
l
l
l
l
Monolithic CMOS Receiver
Low-Jitter, On-Chip Clock Recovery
256x Fs Output Clock Provided
Supports: AES/EBU, IEC958, S/PDIF, &
EIAJ CP-340 Professional and Consumer
Formats
Extensive Error Reporting
- Repeat Last Sample on Error Option
On-Chip RS422 Line Receiver
Configurable Buffer Memory (CS8411)
I
CS8411
CS8412
RXN
RXN
RXP
RXP
10
10
9
9
VD+
VD+
7
7
Digital Audio Interface Receiver
Receiver
Receiver
RS422
RS422
CS12/
MUX
FCK
13
DGND
DGND
8
8
SEL
16
22
22
VA+
VA+
Clock and Data Recovery
Clock and Data Recovery
C0/
20
20
E0
FILT
FILT
6
Ca/
E1
5
21
21
AGND
AGND
MUX
Cb/
E2
4
Copyright
IEnable and Status
ERF
Cc/
F0
Description
The CS8411/12 are monolithic CMOS devices which re-
ceive and decode audio data according to the AES/EBU,
IEC958, S/PDIF, & EIAJ CP-340 interface standards.
The CS8411/12 receive data from a transmission line,
recover the clock and synchronization signals, and de-
multiplex the audio and digital data. Differential or single
ended inputs can be decoded.
The CS8411 has a configurable internal buffer memory,
read via a parallel port, which may be used to buffer
channel status, auxiliary data, and/or user data.
The CS8412 de-multiplexes the channel, user, and va-
lidity data directly to serial output pins with dedicated
output pins for the most important channel status bits.
ORDERING INFORMATION
25
3
(All Rights Reserved)
19
19
See page 32.
Cd/
MCK
MCK
F1
De-MUX
De-MUX
2
Cirrus Logic, Inc. 1998
INT
Ce/
F2
14
27
17
M3
ERF
Configurable
Registers
Memory
25
Buffer
18
Serial Port
Serial Port
M2
Audio
Audio
CBL
24
M1
15
23
M0
CS8411
CS8412
4
8
14
28
26
12
11
26
12
11
1
13
24
23
CS
RD/WR
SDATA
SCK
FSYNC
A4/FCK
A3-A0
D7-D0
SDATA
SCK
FSYNC
C
U
VERF
OCT ‘98
DS61F1
1

Related parts for CS8412-CP

CS8412-CP Summary of contents

Page 1

... The CS8411 has a configurable internal buffer memory, read via a parallel port, which may be used to buffer channel status, auxiliary data, and/or user data. The CS8412 de-multiplexes the channel, user, and va- lidity data directly to serial output pins with dedicated output pins for the most important channel status bits. ...

Page 2

... Special Modes ( ..................................................................... VERF, ERF, and CBL Serial Outputs .............................................. 26 Multifunction Pins ...................................................................................... 26 Channel Status Reporting .................................................................. 27 Professional Channel Status ( ................................................ 28 Consumer Channel Status ( ................................................... 28 SCMS ................................................................................................. 28 PIN DESCRIPTIONS: CS8412 .......................................................................... 29 ORDERING GUIDE ............................................................................................ 32 PACKAGE DIMENSIONS .................................................................................. 33 APPE2NDIX A: RS422 RECEIVER INFORMATION ........................................ 35 Professional Interface ............................................................................... 35 Consumer Interface .................................................................................. 36 TTL/CMOS Levels .................................................................................... 36 Transformers ...

Page 3

... Symbol except RXP, RXN V IH except RXP, RXN V IL (IO = 200 µ (IO = -3.2 mA CS8411/12- CS8411/12- Note 3 Note 3 MCK t j CS8411 CS8412 Min Max 6.0 ± 10 -0.3 VD+ + 0.3 -12 12 -55 125 -65 150 Min Typ Max 4.5 5.0 5 -40 ...

Page 4

... RD/WR high (reading) t csddr RD/WR high (reading) t csdhr adcss t t csl t t rwcss csrwi t dcssw t csddr CS8411 Parallel Port Timing CS8411 CS8412 (RXP, RXN pins only; VD ± Min Typ Max Unit 10 200 °C for suf- A Min Typ Max Unit 13 ...

Page 5

... CS8411 the edge is selectable. The table is defined for the CS8411 with control reg. 2 bit 0, SCED, set to one, and for the CS8412 in formats and 7. For the other formats, the table and figure edges must be reversed (i.e.. "rising" to "falling" and vice versa). ...

Page 6

... MCK 21 AGND VERF SCK 9 RXP SDATA 10 FSYNC RXN CS8412 13 CS12/FCK 16 C SEL 25 U ERF CBL E-F bits 20 FILT DGND 8 Figure 2. CS8412 Typical Connection Diagram CS8411 CS8412 Audio 12 Data 26 Processor 25 14 Audio Data 24 Processor 23 or Micro- controller 19 28 Audio 12 Data 26 ...

Page 7

... FS. In the CS8411, FSYNC can be programmed divided version of MCK or it can be generated directly from the in- coming data stream. In the CS8412, FSYNC is al- ways generated from the incoming data stream. When FSYNC is generated from the data, its edges are extracted at times when intersymbol interfer- ence minimum ...

Page 8

... CS8411 DESCRIPTION The CS8411 is more flexible than the CS8412 but requires a microcontroller or DSP to load internal registers. The CS8412 does not have internal regis- ters so it may be used in a stand-alone mode where no microprocessor or DSP is available. The CS8411 accepts data from a transmission line coded according to the digital audio interface stan- dards ...

Page 9

... ERF is the error flag bit and is set when the ERF pin goes high OR’ing of the errors listed in status register 2, bits 0 through 4, AND’ed with their associated interrupt enable bits in IEnable register 2. CS8411 CS8412 11 FSYNC Audio 12 Serial ...

Page 10

... SR1 and the error pin (ERF), and can specify the received clock fre- quency. As previously mentioned, the first five bits of SR2 are AND’ed with their interrupt enable bits (in IER2) and then OR’ed to create ERF. The V, CS8411 CS8412 DS61F1 ...

Page 11

... CS8411 comes fully out of reset when the block boundary is found recommended to reset the CS8411 after power-up and any time the user per- forms a system-wide reset. The serial port, in mas- ter mode, will begin to operate as soon as RST goes CS8411 CS8412 Sample Frequency 0 0 Out of Range ...

Page 12

... SR2 and enabled in IER2. Figure 10 illustrates the modes selectable by SDF2-SDF0 and FSF1-FSF0. MSTR, which in most applications will be set to one, determines whether FSYNC and SCK are out- puts (MSTR = 1) or inputs (MSTR = 0). When FSYNC and SCK are inputs (slave mode) the audio CS8411 CS8412 B0 Mode Buffer Memory Contents 0 0 ...

Page 13

... Bits, Incl. Aux MSB LSB 24 Bits, Incl. Aux LSB MSB 16 Bits MSB LSB 32 Bits AUX VUCP LSB MSB Bi-Phase Mark Data CS8411 CS8412 32 Bits 32 Clocks 32 Clocks Right Sample 24 Bits, Incl. Aux MSB LSB 24 Bits, Incl. Aux LSB MSB 16 Bits MSB LSB 18 Bits ...

Page 14

... LSB aligned to the end of the sample frame. These formats are used by many interpolation filters. 14 CS8411 CS8412 Special Modes Five special modes are included for unique applica- tions. In these modes, the master bit, MSTR, must be defined as shown in Figure 10 ...

Page 15

... The lower portion of Figure 11 expands the first byte of channel status showing eight pairs of DS61F1 CS8411 CS8412 data, with a pair defined as a frame. This is further expanded showing the first sub-frame (A0) to con- tain 32 bits defined as per the digital audio stan- dards ...

Page 16

... The second four locations, addresses 0CH to 0FH, provide a cyclic buffer for the last 20 bytes of channel status data. The channel status buffer is divided in this fashion because the first four bytes are the most im- CS8411 CS8412 ...

Page 17

... Hex Block (384 Audio Samples (Expanded 1B, 13,14 CS8411 CS8412 (Addresses are in Hex 1B, ...

Page 18

... These bits are illustrated in 6. Block (384 Audio Samples (Expanded CS8411 CS8412 (Addresses are in Hex) 1 DS61F1 ...

Page 19

... ERF pin in that it only causes an interrupt the first time an error occurs until SR1 compatible read. More information on the ERF pin and bit is contained at the end of the Status and IEnable Reg- isters section. Right 191 CS8411 CS8412 Left 0 19 ...

Page 20

... SCK A4/FCK INT A3 CS8411 CS8412 DATA BUS BIT 1 DATA BUS BIT 0 SERIAL OUTPUT DATA ERROR FLAG CHIP SELECT READ/WRITE SELECT ANALOG POWER ANALOG GROUND FILTER MASTER CLOCK ADDRESS BUS BIT 0 ADDRESS BUS BIT 1 ADDRESS BUS BIT 2 ADDRESS BUS BIT 3 ...

Page 21

... INT - Interrupt, PIN 14. Open drain output that can signal the state of the internal buffer memory as well as error information resistor to VD+ is typically used to support logic gates. All bits affecting INT are maskable to allow total control over the interrupt mechanism. DS61F1 CS8411 CS8412 21 ...

Page 22

... RS422 compatible line receivers. Described in detail in Appendix A. Phase Locked Loop MCK - Master Clock, PIN 19. Low jitter clock output of 256 times the received sample frequency. FILT - Filter, PIN 20. An external 1k resistor and 0.047 µF capacitor are required from the FILT pin to analog ground. 22 CS8411 CS8412 DS61F1 ...

Page 23

... CS8412 DESCRIPTION The CS8412 does not need a microprocessor to handle the non-audio data (although a micro may be used with the C and U serial ports). Instead, ded- icated pins are available for the most important channel status bits. The CS8412 is a monolithic CMOS circuit that receives and decodes digital au- dio data which was encoded according to the digital audio interface standards ...

Page 24

... Figure 18 illus- trates formats 12 and 13. Format 14 is reserved and not presently used, and format 15 causes the CS8412 to go into a reset state. While in reset all outputs will be inactive except MCK. The CS8412 comes out of reset at the first block boundary after leaving the reset state ...

Page 25

... Left MSB LSB Left MSB LSB Left LSB MSB 16 Bits Left MSB LSB 18 Bits Left MSB LSB Figure 17. CS8412 Audio Serial Port Formats CS8411 CS8412 Right MSB LSB Right MSB LSB Right MSB LSB Right MSB LSB Right LSB MSB Right ...

Page 26

... Figure 19. Multifunction Pins There are seven multifunction pins which contain either error and received frequency information, or channel status information, selectable by SEL. Right 0 Left 1 Right 31 Figure 19. CBL Timing CS8411 CS8412 Right MSB AUX LSB Right AUX MSB LSB ...

Page 27

... This error is indicated when the CS8412 calculated CRC value does not match the CRC byte of the channel status block or when a block boundary changes (as in re- moving samples while editing) ...

Page 28

... C9, is the inverse of channel status bit 9, which gives some indication of channel mode. (Bit 9 is also defined as bit 1 of byte 1.) When Ce, defined as CRCE, is low, the CS8412 calculated CRC value does not match the received CRC value. This signal may be used to qualify Ca through Cd through Ce are being displayed, Ce going low can indicate not to update the display ...

Page 29

... PIN DESCRIPTIONS: CS8412 CHANNEL STATUS OUTPUT FREQ REPORT FREQ REPORT ERROR CONDITION ERROR CONDITION ERROR CONDITION 0 DIGITAL POWER DIGITAL GROUND RECEIVE POSITIVE RECEIVE NEGATIVE FRAME SYNC SERIAL DATA CLOCK CHANNEL SELECT / FCLOCK USER DATA OUTPUT Power Supply Connections VD+ - Positive Digital Power, PIN 7 ...

Page 30

... Ca-Ce pins. These pins are updated with the rising edge of CBL. CS12 - Channel Select, PIN 13. This pin is also dual function and is selected by bringing SEL high. CS12 selects sub-frame1 (when low) or sub-frame2 (when high displayed by channel status pins C0 and Ca through Ce. 30 CS8411 CS8412 DS61F1 ...

Page 31

... RS422 compatible line receivers. Phase Locked Loop MCK - Master Clock, PIN 19. Low jitter clock output of 256 times the received sample frequency. FILT - Filter, PIN 20. An external 1 k resistor and 0.047 µF capacitor is required from FILT pin to analog ground. DS61F1 CS8411 CS8412 31 ...

Page 32

... CS8412 - IP CS8412 - CS CS8412 - IS * Although the ‘-CP’ and ‘-CS’ suffixed parts are guaranteed to operate over °C, they are tested at 25 °C only. If testing over temperature is desired, the ‘-IP’ and ‘-IS’ suffixed parts are tested over their speci- fied temperature range ...

Page 33

... MAX 0.000 0.250 0.015 0.025 0.125 0.195 0.014 0.022 0.030 0.070 0.008 0.014 1.380 1.565 0.600 0.625 0.485 0.580 0.090 0.110 0.580 0.620 0.600 0.700 0.000 0.060 0.115 0.200 0° 15° CS8411 CS8412 SIDE VIEW MILLIMETERS MIN MAX 0.00 6.35 0.38 0.64 3.18 4.95 0.36 0.56 0.76 1.78 0.20 0.36 35.05 39.75 15.24 15.88 12.32 14.73 2.29 2.79 14 ...

Page 34

... PLANE e DIM INCHES MIN MAX 0.093 0.104 0.004 0.012 0.013 0.020 0.009 0.013 0.697 0.713 17.70 0.291 0.299 0.040 0.060 0.394 0.419 10.00 0.016 0.050 0° 8° CS8411 CS8412 MILLIMETERS MIN MAX 2.35 2.65 0.10 0.30 0.33 0.51 0.23 0.32 18.10 7.40 7.60 1.02 1.52 10.65 0.40 1.27 0° 8° DS61F1 ...

Page 35

... APPENDIX A: RS422 RECEIVER INFORMATION The RS422 receivers on the CS8411 and CS8412 are designed to receive both the professional and consumer interfaces, and meet all specifications listed in the digital audio standards. Figure 20 illus- trates the internal schematic of the receiver portion of both chips. The receiver has a differential input. ...

Page 36

... The circuit shown in Figure 24 may be used when external RS422 receivers or TTL/CMOS logic drive the CS8411/12 receiver section. TTL/CMOS CS8411/12 RXP RXN Transformers 0.01 F Please refer to Application Note AN134: AES and S/PDIF Recommended Transformers for further information. CS8411 CS8412 CS8411/12 Gate 0.01 F 0.01 F Figure 24. TTL/CMOS Interface RXP RXN DS61F1 ...

Page 37

... APPENDIX B: SUGGESTED RESET CIRCUIT FOR CS8412 CS8412 The CS8412 should be reset immediately after power-up and any time the user issues a system- wide reset. This is accomplished by pulling all four DS61F1 Figure 25. CS8412 Reset Circuit Mode Select pins high. Figure 25 shows a simple circuit to implement this ...

Page 38

...

Related keywords