EPF81188ARC240-6 Altera Corporation, EPF81188ARC240-6 Datasheet

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EPF81188ARC240-6

Manufacturer Part Number
EPF81188ARC240-6
Description
Manufacturer
Altera Corporation
Datasheet
DS-F8000-11.1
1
Features...
Altera Corporation
Usable gates
Flipflops
Logic array blocks (LABs)
Logic elements (LEs)
Maximum user I/O pins
January 2003, ver. 11.1
Table 1. FLEX 8000 Device Features
Feature
EPF8282A
EPF8282AV
2,500
282
208
26
78
Low-cost, high-density, register-rich CMOS programmable logic
device (PLD) family (see
System-level features
Flexible interconnect
Powerful I/O pins
Programmable output slew-rate control reduces switching noise
devices or intelligent controller
Special Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 5.0-V operation
circuitry compliant with IEEE Std. 1149.1-1990 on selected devices
while I/O pins are compatible with 5.0-V and 3.3-V logic levels
standby mode)
predictable interconnect delays
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
logic functions (automatically used by software tools and
megafunctions)
In-circuit reconfigurability (ICR) via external configuration
Fully compliant with the peripheral component interconnect
Built-in Joint Test Action Group (JTAG) boundary-scan test (BST)
MultiVolt
Low power consumption (typical specification is 0.5 mA or less in
FastTrack
Dedicated carry chain that implements arithmetic functions such
Dedicated cascade chain that implements high-speed, high-fan-in
Tri-state emulation that implements internal tri-state nets
2,500 to 16,000 usable gates
282 to 1,500 registers
EPF8452A
®
4,000
452
336
120
42
TM
®
Interconnect continuous routing structure for fast,
I/O interface enabling device core to run at 5.0 V,
EPF8636A
6,000
636
504
136
63
Table
1)
EPF8820A
8,000
820
672
152
84
Programmable Logic
EPF81188A EPF81500A
12,000
1,188
1,008
126
184
FLEX 8000
Device Family
Data Sheet
16,000
1,500
1,296
162
208
1
3

Related parts for EPF81188ARC240-6

EPF81188ARC240-6 Summary of contents

Page 1

... Table 1. FLEX 8000 Device Features Feature EPF8282A EPF8282AV Usable gates Flipflops Logic array blocks (LABs) Logic elements (LEs) Maximum user I/O pins Altera Corporation DS-F8000-11.1 ® Low-cost, high-density, register-rich CMOS programmable logic device (PLD) family (see – 2,500 to 16,000 usable gates – 282 to 1,500 registers System-level features – ...

Page 2

... Yes No II development system for Windows-based 208- 225- 232- 240- Pin Pin Pin Pin PQFP BGA PGA PQFP 136 152 152 148 184 184 181 ® ) family combines the Altera Corporation Yes Table 2) 280- 304- Pin Pin PGA RQFP 208 208 ...

Page 3

... Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet FLEX 8000 devices provide a large number of storage elements for applications such as digital signal processing (DSP), wide-data-path manipulation, and data transformation. These devices are an excellent choice for bus interfaces, TTL integration, coprocessor functions, and high-speed controllers ...

Page 4

... LE provides highly efficient logic implementation. Eight LEs are grouped together to form a logic array block (LAB). Each FLEX 8000 LAB is an independent structure with common inputs, interconnections, and control signals. The LAB architecture provides a coarse-grained structure for high device performance and easy routing. 4 Altera Corporation ...

Page 5

... Block (LAB) IOE IOE Logic Element (LE) Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 1 shows a block diagram of the FLEX 8000 architecture. Each group of eight LEs is combined into an LAB; LABs are arranged into rows and columns. The I/O pins are supported by I/O elements (IOEs) located at the ends of rows and columns ...

Page 6

... Dedicated Row Interconnect Inputs 4 4 Carry-In and Cascade-In from LAB on Left 4 2 LE1 4 LE2 4 LE3 4 LE4 4 LE5 4 LE6 4 LE7 4 LE8 Figure 2 shows a block 8 See Figure 8 for details Column-to-Row Interconnect Column Interconnect Carry-Out and Cascade-Out to LAB on Right Altera Corporation ...

Page 7

... LABCTRL1 LABCTRL2 LABCTRL3 LABCTRL4 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Each LAB provides four control signals that can be used in all eight LEs. Two of these signals can be used as clocks, and the other two for clear/preset control. The LAB control signals can be driven directly from a dedicated input pin, an I/O pin, or any internal signal via the LAB local interconnect ...

Page 8

... The final carry-out signal is routed to another LE, where it can be used as a general-purpose signal. In addition to mathematical functions, carry chain logic supports very fast counters and comparators. 8 shows how an n-bit full adder can be implemented LEs Altera Corporation ...

Page 9

... Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 4. FLEX 8000 Carry Chain Operation Carry- Carry a2 LUT b2 Carry Chain a n LUT b n Carry Chain LUT Carry Chain Cascade Chain With the cascade chain, the FLEX 8000 architecture can implement functions that have a very wide fan-in. Adjacent LUTs can be used to compute portions of the function in parallel ...

Page 10

... Design performance can also be enhanced by designing for the operating mode that supports the desired application. 10 shows how the cascade function can connect adjacent LEs to OR Cascade Chain LE1 d[3..0] LE2 d[7.. d[(4 n- 1)..4( n- 1)] LE1 LUT LE2 LUT LE n LUT Altera Corporation ...

Page 11

... Clearable Counter Mode Carry-In (ena) data1 (nclr) data2 data3 (data) (nload) data4 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Cascade-In 4-Input LUT Cascade-Out Cascade-In 3-Input LUT Cascade-Out 3-Input LUT Carry-Out Cascade-In 3-Input 1 ...

Page 12

... Two 3-input LUTs are used: one generates the counter data, and the other generates the fast carry bit. Synchronous loading is provided by a 2-to-1 multiplexer, and the output of this multiplexer is ANDed with a synchronous clear. 12 Altera Corporation ...

Page 13

... Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Internal Tri-State Emulation Internal tri-state emulation provides internal tri-stating without the limitations of a physical tri-state bus physical tri-state bus, the tri-state buffers’ output enable signals select the signal that drives the bus. ...

Page 14

... NOT Asynchronous Load without Clear or Preset NOT LABCTRL1 (Asynchronous Load) DATA3 (Data) NOT 14 Asynchronous Preset LABCTRL1 or LABCTRL2 PRN D Q CLRN PRN Q D CLRN PRN Q D CLRN PRN Q D CLRN Asynchronous Clear & Preset LABCTRL1 PRN D Q CLRN LABCTRL2 Altera Corporation ...

Page 15

... Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Asynchronous Clear A register is cleared by one of the two LABCTRL signals. When the CLRn port receives a low signal, the register is set to zero. Asynchronous Preset An asynchronous preset is implemented as either an asynchronous load or an asynchronous clear. If DATA3 is tied to VCC, asserting LABCTRLl asynchronously loads a 1 into the register ...

Page 16

... Figure 8. FLEX 8000 LAB Connections to Row & Column Interconnect 16 shows how an LE drives the row and column interconnect. Row Channels (1) Each LE drives one row channel. LE1 LE2 Note: (1) See Table 4 for the number of row channels. to Local to Local Each LE drives up to Feedback Feedback two column channels. Altera Corporation 16 Column Channels ...

Page 17

... Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Each LAB can drive up to two separate column interconnect channels. Therefore, all 16 available column channels can be driven by the LAB. The column channels run vertically across the entire device, and share access to LABs in the same column but in different rows. The MAX+PLUS II Compiler chooses which LEs must be connected to a column channel ...

Page 18

... IOE IOE IOE Row Interconnect LAB A2 LAB B2 Cascade & Carry Chain IOE IOE IOE Figure 10 shows the IOE block diagram. See Figure 12 for details. See Figure 11 for details. IOE 1 IOE 8 IOE 1 IOE 8 Altera Corporation ...

Page 19

... Figure 10. FLEX 8000 IOE Numbers in parentheses are for EPF81500A devices only. To Row or Column Interconnect From Row or Column Interconnect Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet I/O Controls 6 Programmable (6) Inversion VCC VCC Row-to-IOE Connections Figure 11 illustrates the connection between row interconnect channels and IOEs ...

Page 20

... The output signal to an IOE can choose from 8 of the 16 column channels through an 8-to-1 multiplexer. 20 Note (1 168 (216 12). When an IOE is used as an input, it can drive up to two IOE 1 IOE 2 IOE 3 IOE 4 IOE 5 IOE 6 IOE 7 IOE Altera Corporation ...

Page 21

... Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Figure 12. FLEX 8000 Column-to-IOE Connections Each IOE is driven by an IOE 8-to-1 multiplexer. 8 Column Interconnect In addition to general-purpose I/O pins, FLEX 8000 devices have four dedicated input pins. These dedicated inputs provide low-skew, device- wide signal distribution, and are typically used for global clock, clear, and preset control signals ...

Page 22

... The number of row channels in a row that can drive the Numbers in parentheses are for EPF81500A devices. 4 Dedicated Inputs 1 2 Row Channels ( for EPF8282A and EPF8282AV devices for EPF8452A, EPF8636A, EPF8820A, and EPF81188A devices for EPF81500A devices. Peripheral Control Signals Programmable Inversion Altera Corporation ...

Page 23

... OE6 – OE7 – OE8 – OE9 Output Configuration f Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 5 lists the source of the peripheral control signal for each FLEX 8000 device by row. EPF8452A EPF8636A Row A Row A Row B Row C Row A ...

Page 24

... CC level, input voltages are at TTL levels and are therefore CCINT 26. Description levels lower than 4.75 V CCIO instead See Table 8 OD2 OD1 Table 6. Altera Corporation ...

Page 25

... FLEX 8000 devices that support JTAG include weak pull-ups on the JTAG pins. Figure 14. EPF8282A, EPF8282AV, EPF8636A, EPF8820A & EPF81500A JTAG Waveforms Table 8 EPF8282AV, EPF8636A, EPF8820A, and EPF81500A devices. Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 7. FLEX 8000 Boundary-Scan Register Length Device EPF8282A, EPF8282AV EPF8636A ...

Page 26

... FLEX 8000 devices are made under conditions equivalent to those shown in Figure 15. Designers can use multiple test patterns to configure devices during all stages of the production flow. EPF8282A Unit EPF8282AV EPF8636A EPF8820A EPF81500A Min Max 100 Altera Corporation ...

Page 27

... Storage temperature STG T Ambient temperature AMB T Junction temperature J Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Power supply transients can affect AC measurements. Simultaneous transitions of multiple outputs should be avoided for accurate measurement. Threshold tests must not be performed under AC conditions. Large-amplitude, fast-ground- ...

Page 28

... ground ground, no load I Min Max 4.75 (4.50) 5.25 (5.50) 4.75 (4.50) 5.25 (5.50) 3.00 (3.00) 3.60 (3.60) –0 0.5 CCINT 0 V CCIO 0 70 – (5), (6) Min Typ Max 2 0.5 CCINT –0.5 0.8 2.4 2.4 V – 0.2 CCIO 0.45 0.45 0.2 –10 10 –40 40 0.5 10 Altera Corporation Unit ° C ° Unit µA µA mA ...

Page 29

... V Input voltage I V Output voltage O T Operating temperature A t Input rise time R t Input fall time F Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Note (8) Conditions 1.0 MHz 1.0 MHz OUT Sheet through 16 provide information on absolute maximum ratings, ...

Page 30

... FLEX 8000 devices. The output driver is compliant with PCI Local Bus Specification, Revision 2.2. Note (4) Min Typ 2.0 –0.3 (5) V – 0.2 CC –10 –40 (6) 0.3 Min parameter refers to low-level TTL output current. OL Max Unit µA 40 µ Max Unit Altera Corporation ...

Page 31

... Output Voltage (V) Figure 17 EPF8282A devices. The output driver is compliant with PCI Local Bus Specification, Revision 2.2. Figure 17. Output Drive Characteristics of EPF8282A Devices with 5.0-V V Figure 18 devices. Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet I OL Typical I Output Current (mA 5.0 V CCINT ...

Page 32

... The Timing Analyzer provides point-to-point timing delay information, setup and hold time prediction, and device-wide performance analysis. Tables 17 through 20 describe the FLEX 8000 timing parameters and their symbols 3 Room Temperature Output Voltage (V) Altera Corporation 4 ...

Page 33

... LE register setup time before clock; LE register recovery time after asynchronous preset, clear load t LE register hold time after clock register preset delay PRE t LE register clear delay CLR Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Note (1) Parameter = 5 CCIO = 3 CCIO ( CCIO = 3 ...

Page 34

... Table 21 summarizes the interconnect paths shown in Figure 19. For more information on timing parameters (Understanding FLEX 8000 Timing). Note (1) Parameter Note (5) Parameter 29. Timing). Figure 19. This model contains three distinct Figure 19 through 49. Hand-calculations that use the Application Note 76 (6) is expressed as a Altera Corporation ...

Page 35

ROW Carry-In from Cascade-In from Previous LE Previous LE Cascade Gate Delay LUT Delay t LUT t t RLUT GATE t CLUT Carry Chain Delay t t LOCAL CGEN t CGENR t CICO Register Control CASC ...

Page 36

... Max Min 0.7 1.7 1.7 1.0 0.3 1.6 0.0 1.2 1.5 1.1 – 4.6 1.4 1.4 – 4.9 Total Delay t LOCAL ROW LOCAL COL ROW t COL t ROW ROW LOCAL COL ROW A-4 Max Min Max 0.8 0.9 1.8 1.9 1.8 1.9 1.0 1.0 0.2 0.1 1.8 0.0 1.2 1.2 1.6 1.7 1.4 1.7 – – 4.9 5.2 1.6 1.8 1.6 1.8 – – 5.1 5.3 Altera Corporation + t LOCAL + t LOCAL Unit ...

Page 37

... Table 23. EPF8282A Interconnect Timing Parameters Symbol Min t LABCASC t LABCARRY t LOCAL t ROW t COL t DIN_C t DIN_D t DIN_IO Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Speed Grade A-2 A-3 Max Min 0.3 0.3 0.5 4.2 2.5 5.0 7.2 5.0 A-4 Max Min Max 0.3 0.4 0.3 0.4 0.6 0.8 4.2 4.2 2.5 2.5 5.0 5.5 7.2 7.2 5.0 5.5 Unit ...

Page 38

... COMB PRE t CLR Table 25. EPF8282A External Timing Parameters Symbol Min t DRR t 1.0 ODH 38 Speed Grade A-2 A-3 Max Min 2.0 0.0 0.9 0.0 0.6 0.4 0.4 0.9 1.6 4.0 4.0 0.4 0.4 1.1 1.1 0.6 0.6 Speed Grade A-2 A-3 Max Min 15.8 1.0 A-4 Max Min Max 2.5 3.2 0.0 0.0 1.1 1.5 0.0 0.0 0.7 0.9 0.5 0.6 0.5 0.7 1.1 1.5 2.0 2.5 4.0 4.0 0.5 0.6 0.5 0.6 1.2 1.5 0.7 0.8 0.7 0.8 A-4 Max Min Max 19.8 24.8 1.0 Altera Corporation Unit Unit ns ns ...

Page 39

... Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 26. EPF8282AV I/O Element Timing Parameters Symbol A-3 Min t IOD t IOC t IOE t IOCO t IOCOMB t 1.8 IOSU t 0.0 IOH t IOCLR OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 Table 27. EPF8282AV Interconnect Timing Parameters Symbol A-3 Min t LABCASC ...

Page 40

... COMB PRE t CLR Table 29. EPF8282AV External Timing Parameters Symbol A-3 Min t DRR t 1.0 ODH Speed Grade A-4 Max Min Max 3.2 7.3 0.0 1.4 1.5 5.1 0.0 0.0 0.9 2.8 0.6 1.5 0.7 2.2 1.5 3.7 2.5 4.7 6.0 6.0 0.6 0.9 0.6 0.9 2.4 4.6 0.8 1.3 0.8 1.3 Speed Grade A-4 Max Min Max 24.8 50.1 1.0 Unit Unit ns ns Altera Corporation ...

Page 41

... OD2 t OD3 ZX1 t ZX2 t ZX3 Table 31. EPF8452A Interconnect Timing Parameters Symbol Min t LABCASC t LABCARRY t LOCAL t ROW t COL t DIN_C t DIN_D t DIN_IO Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Speed Grade A-2 A-3 Max Min 0.7 1.7 1.7 1.0 0.3 1.6 0.0 1.2 1.5 1.1 – 4.6 1.4 1.4 – 4.9 Speed Grade A-2 A-3 Max Min 0.3 0.3 ...

Page 42

... COMB PRE t CLR Table 33. EPF8452A External Timing Parameters Symbol Min t DRR t 1.0 ODH 42 Speed Grade A-2 A-3 Max Min 2.0 0.0 0.9 0.0 0.6 0.4 0.4 0.9 1.6 4.0 4.0 0.4 0.4 1.0 1.1 0.6 0.6 Speed Grade A-2 A-3 Max Min 16.0 1.0 A-4 Max Min Max 2.3 3.0 0.2 0.1 1.6 1.6 0.0 0.0 0.7 0.9 0.5 0.6 0.9 0.8 1.4 1.5 1.8 2.4 4.0 4.0 0.5 0.6 0.5 0.6 1.1 1.4 0.7 0.8 0.7 0.8 A-4 Max Min Max 20.0 25.0 1.0 Altera Corporation Unit Unit ns ns ...

Page 43

... IN t OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 Table 35. EPF8636A Interconnect Timing Parameters Symbol Min t LABCASC t LABCARRY t LOCAL t ROW t COL t DIN_C t DIN_D t DIN_IO Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Speed Grade A-2 A-3 Max Min 0.7 1.7 1.7 1.0 0.3 1.6 0.0 1.2 1.5 1.1 1.6 4.6 1.4 1.4 1.9 4.9 Speed Grade A-2 A-3 Max Min 0.3 0.3 0.5 5.0 3.0 5.0 7 ...

Page 44

... PRE t CLR Table 37. EPF8636A External Timing Parameters Symbol t DRR t ODH 44 Speed Grade A-2 Min Max Min 2.0 0.0 0.9 0.0 0.6 0.4 0.4 0.9 1.6 4.0 4.0 4.0 4.0 0.4 0.4 0.8 1.0 0.9 1.1 0.6 0.6 Speed Grade A-2 Min Max Min 16.0 1.0 1.0 A-3 A-4 Max Min 2.3 0.2 1.6 0.0 0.7 0.5 0.9 1.4 1.8 4.0 4.0 0.5 0.5 1.1 1.4 0.7 0.7 A-3 A-4 Max Min 20.0 1.0 Altera Corporation Unit Max 3.0 ns 0.1 ns 1.6 ns 0.0 ns 0.9 ns 0.6 ns 0.8 ns 1 0 0.8 ns 0.8 ns Unit Max 25 ...

Page 45

... IN t OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 Table 39. EPF8820A Interconnect Timing Parameters Symbol Min t LABCASC t LABCARRY t LOCAL t ROW t COL t DIN_C t DIN_D t DIN_IO Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Speed Grade A-2 A-3 Max Min 0.7 1.7 1.7 1.0 0.3 1.6 0.0 1.2 1.5 1.1 1.6 4.6 1.4 1.4 1.9 4.9 Speed Grade A-2 A-3 Max Min 0.3 0.3 0.5 5.0 3.0 5.0 7 ...

Page 46

... COMB PRE t CLR Table 41. EPF8820A External Timing Parameters Symbol Min t DRR t 1.0 ODH 46 Speed Grade A-2 A-3 Max Min 2.0 0.0 0.9 0.0 0.6 0.4 0.4 0.9 1.6 4.0 4.0 0.4 0.4 1.1 1.1 0.6 0.6 Speed Grade A-2 A-3 Max Min 16.0 1.0 A-4 Max Min Max 2.5 3.2 0.0 0.0 1.1 1.5 0.0 0.0 0.7 0.9 0.5 0.6 0.5 0.7 1.1 1.5 2.0 2.5 4.0 4.0 0.5 0.6 0.5 0.6 1.2 1.5 0.7 0.8 0.7 0.8 A-4 Max Min Max 20.0 25.0 1.0 Altera Corporation Unit Unit ns ns ...

Page 47

... OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 Table 43. EPF81188A Interconnect Timing Parameters Symbol t LABCASC t LABCARRY t LOCAL t ROW t COL t DIN_C t DIN_D t DIN_IO Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Speed Grade A-2 Min Max Min 0.7 1.7 1.7 1.0 0.3 1.4 1.6 0.0 0.0 1.2 1.5 1.1 1.6 4.6 1.4 1.4 1.9 4.9 Speed Grade A-2 Min Max Min 0.3 ...

Page 48

... COMB PRE t CLR Table 45. EPF81188A External Timing Parameters Symbol Min t DRR t 1.0 ODH 48 Speed Grade A-2 A-3 Max Min 2.0 0.0 0.9 0.0 0.6 0.4 0.4 0.9 1.6 4.0 4.0 0.4 0.4 1.1 1.1 0.6 0.6 Speed Grade A-2 A-3 Max Min 16.0 1.0 A-4 Max Min Max 2.5 3.2 0.0 0.0 1.1 1.5 0.0 0.0 0.7 0.9 0.5 0.6 0.5 0.7 1.1 1.5 2.0 2.5 4.0 4.0 0.5 0.6 0.5 0.6 1.2 1.5 0.7 0.8 0.7 0.8 A-4 Max Min Max 20.0 25.0 1.0 Altera Corporation Unit Unit ns ns ...

Page 49

... IN t OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 Table 47. EPF81500A Interconnect Timing Parameters Symbol Min t LABCASC t LABCARRY t LOCAL t ROW t COL t DIN_C t DIN_D t DIN_IO Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Speed Grade A-2 A-3 Max Min 0.7 1.7 1.7 1.0 0.3 1.6 0.0 1.2 1.5 1.1 1.6 4.6 1.4 1.4 1.9 4.9 Speed Grade A-2 A-3 Max Min 0.3 0.3 0.5 6.2 3.0 5.0 8 ...

Page 50

... COMB PRE t CLR Table 49. EPF81500A External Timing Parameters Symbol Min t DRR t 1.0 ODH 50 Speed Grade A-2 A-3 Max Min 2.0 0.0 0.9 0.0 0.6 0.4 0.4 0.9 1.6 4.0 4.0 0.4 0.4 1.1 1.1 0.6 0.6 Speed Grade A-2 A-3 Max Min 16.1 1.0 A-4 Max Min Max 2.5 3.2 0.0 0.0 1.1 1.5 0.0 0.0 0.7 0.9 0.5 0.6 0.5 0.7 1.1 1.5 2.0 2.5 4.0 4.0 0.5 0.6 0.5 0.6 1.2 1.5 0.7 0.8 0.7 0.8 A-4 Max Min Max 20.1 25.1 1.0 Altera Corporation Unit Unit ns ns ...

Page 51

... This calculation provides an I with no output load. The actual I operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions. Figure 20 for several LE utilization values. Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet + P = [(I INT IO ...

Page 52

... For more information Devices) and Application Note 38 (Configuring Multiple FLEX 8000 vs. Operating Frequency 30 Frequency (MHz) 30 Frequency (MHz) Application Note 33 (Configuring FLEX 8000 Altera Corporation 1,500 LEs 1,000 LEs 500 LEs 60 200 LEs 150 LEs 100 LEs 50 LEs 60 Devices). ...

Page 53

... MHz and 6 MHz. In the passive configuration schemes, an external controller guides the FLEX 8000 device. shows the data source for each of the six configuration schemes. Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet Table 51. Data Source for Configuration ...

Page 54

... 102 K2 71 103 K1 72 104 K3 73 105 M1 160-Pin PQFP EPF8820A ( 125 124 87 89 110 118 121 100 107 Altera Corporation ...

Page 55

... TDO TCK (4), (6) 72 (4) 20 TMS (7) 52 TRST Dedicated 12, 31, 54, Inputs (10) 73 17, 38, 59, VCCINT 80 – VCCIO Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet 84-Pin 100-Pin 100-Pin PLCC TQFP EPF8452A EPF8282A EPF8452A EPF8636A EPF8282AV ...

Page 56

... TQFP PGA EPF8820A EPF8452A 7, 17, 27, C12, D4, 39, 54, D7, D9, 80, 81, D13, G4, 100,101, G13, H3, 128, 142 H12, J4, J13, L1, M3, M8, M12, M15, N4 – – 108 116 Altera Corporation 160-Pin PQFP EPF8820A (1) 12, 13, 34, 35, 51, 63, 75, 80, 83, 93, 103, 115, 126, 131, 143, 155 – 116 ...

Page 57

... ADD5 105 ADD4 106 ADD3 109 ADD2 110 ADD1 123 ADD0 144 DATA7 150 DATA6 152 DATA5 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet 160-Pin 192-Pin PGA PQFP EPF8636A EPF8636A EPF8820A 1 R15 3 T15 120 ...

Page 58

... Altera Corporation 208-Pin PQFP EPF81188A (1) 170 168 166 163 161 119 – ...

Page 59

... G11 ADD6 F14 ADD5 E13 ADD4 D15 ADD3 D14 ADD2 E12 ADD1 C15 ADD0 A7 DATA7 D7 DATA6 A6 DATA5 Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet 232-Pin 240-Pin PGA PQFP EPF81188A EPF81188A C14 237 G15 21 L15 40 L3 141 R4 117 C4 184 ...

Page 60

... E14, R7, R9, 236 R11, R13, R14, T14 17, 39, 61, 78, D14, E7, E9, 94, 108, 130, E11, E13, R6, 152, 174, 191, R8, R10, R12, 205, 221, 235 T13, T15 Altera Corporation 304-Pin RQFP EPF81500A 248 246 243 241 239 169 80 (14) 149 ...

Page 61

... H9, H10, H11, J6, J7, J8, J9, J10, K6, K7, K8, K9, K11, L15, N3 Connect – (N.C.) Total User I/O 148 Pins (9) Altera Corporation FLEX 8000 Programmable Logic Device Family Data Sheet 232-Pin 240-Pin PGA PQFP EPF81188A EPF81188A A1, D6, E11 30, 31, E7, E9, G4, 52, 53, 72, 90, G5, G13, ...

Page 62

... The information contained in the FLEX 8000 Programmable Logic Device Family Data Sheet version 11.1 supersedes information published in History previous versions. The FLEX 8000 Programmable Logic Device Family Data Sheet version 11.1 contains the following change: minor textual updates. 62 for more information. Application Note 74 Altera Corporation ...

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