SC16C550 NXP Semiconductors, SC16C550 Datasheet
SC16C550
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SC16C550 Summary of contents
Page 1
... System interrupts may be tailored to meet user requirements. An internal loop-back capability allows on-board diagnostics. The SC16C550 operates 3.3 V and 2.5 V, and the Industrial temperature range, and is available in plastic DIP40, PLCC44 and LQFP48 packages. 2. Features ...
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... Even-, Odd-, or No-Parity formats 1 1 2-stop bit 2 Baud generation ( Mbit/s) Loop-back controls for communications link fault isolation 10 +85 C. amb Rev. 05 — 19 June 2003 SC16C550 Version SOT187-2 7 1.4 mm SOT313-2 SOT129-1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... REGISTER FLOW CONTROL LOGIC RECEIVE RECEIVE FIFO REGISTERS REGISTER FLOW CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR XTAL1 XTAL2 RCLK BAUDOUT Rev. 05 — 19 June 2003 SC16C550 TX SHIFT IR ENCODER RX SHIFT IR DECODER DTR RTS OUT1, OUT2 MODEM CONTROL LOGIC CTS RI DCD DSR 002aaa052 © ...
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... UART with 16-byte FIFO and IrDA encoder/decoder RCLK SC16C550IA44 CS0 14 CS1 15 16 CS2 BAUDOUT 17 Rev. 05 — 19 June 2003 SC16C550 OUT1 37 DTR 36 RTS 35 OUT2 INT 32 RXRDY 002aaa092 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... UART with 16-byte FIFO and IrDA encoder/decoder RCLK SC16C550IB48 CS0 9 CS1 10 CS2 11 BAUDOUT 12 Rev. 05 — 19 June 2003 SC16C550 OUT1 33 DTR 32 RTS 31 OUT2 30 INT 29 RXRDY 002aaa093 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... Baud out. BAUDOUT clock signal for the transmitter section of the UART. The clock rate is established by the reference oscillator frequency divided by a divisor specified in the baud generator divisor latches. BAUDOUT may also be used for the receiver section by tying this output to RCLK. Rev. 05 — 19 June 2003 SC16C550 ...
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... OUT2). OUT1 and OUT2 are set to inactive the (HIGH) level as a result of Master Reset, during loop mode operations clearing bit 2 (OUT1) or bit 3 (OUT2) of the MCR. Rev. 05 — 19 June 2003 SC16C550 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multi-transfer DMA in which multiple transfers are made continuously until the transmit FIFO has been filled. Rev. 05 — 19 June 2003 SC16C550 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... The combination of the above greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. The SC16C550 is capable of operation Mbits/s with a 48 MHz external clock input (at 5 V). The rich feature set of the SC16C550 is available through internal registers. ...
Page 10
... Philips Semiconductors 6.1 Internal registers The SC16C550 provides 15 internal registers for monitoring and control. These registers are shown in in the standard 16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status and control registers (LCR/LSR), modem status and control registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a user accessible scratchpad register (SPR) ...
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... When RTS is connected to CTS, data transmission does not occur unless the receiver FIFO has space for the data; thus, overrun errors are eliminated using UART 1 and UART 2 from a SC16C550 with the autoflow control enabled. If not, overrun errors occur when the transmit data rate exceeds the receiver FIFO read latency ...
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... The auto-CTS function reduces interrupts to the host system. STOP START BITS 0-7 STOP and Figure 8. STOP START BYTE STOP 1 2 Rev. 05 — 19 June 2003 SC16C550 START BITS 0-7 STOP 002aaa049 START BYTE STOP N N+1 002aaa050 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 13
... Following a suspension due to a match of the Xoff characters’ values, the SC16C550 will monitor the receive data stream for a match to the Xon1,2 character value(s match is found, the SC16C550 will resume operation and clear the flags (ISR[4]). Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. ...
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... Three special interrupts have been added to monitor the hardware and software flow control. The interrupts are enabled by IER[5-7]. Care must be taken when handling these interrupts. Following a reset, the transmitter interrupt is enabled, the SC16C550 will issue an interrupt to indicate that the Transmit Holding Register is empty. This interrupt must be serviced prior to continuing operations ...
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... Fig 9. Crystal oscillator connection. The generator divides the input 16 clock by any divisor from SC16C550 divides the basic crystal or external clock by 16. The frequency of the BAUDOUT output pin is exactly 16 (16 times) of the selected baud rate (BAUDOUT = 16 Baud Rate). Customized baud rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate generator ...
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... DMA operation The SC16C550 FIFO trigger level provides additional flexibility to the user for block mode operation. The user can optionally operate the transmit and receive FIFOs in the DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY output pins ...
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... RX, RI, CTS, DSR, DCD transmit data is provided by the user. If the sleep mode is enabled and the SC16C550 is awakened by one of the conditions described above, it will return to the sleep mode automatically after the last character is transmitted or read by the user ...
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... REGISTER REGISTERS FLOW CONTROL LOGIC MODEM CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR XTAL1 XTAL2 RCLK BAUDOUT Rev. 05 — 19 June 2003 SC16C550 TX IR ENCODER RX IR DECODER RTS DCD DTR RI OUT1 DSR OUT2 CTS 002aaa276 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... Enhanced Feature Register, Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BF 9397 750 11619 Product data UART with 16-byte FIFO and IrDA encoder/decoder details the assigned bit functions for the fifteen SC16C550 internal registers. Bit 7 Bit 6 Bit 5 Bit 4 bit 7 ...
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... FIFO full; logic least one FIFO location available). The serial receive section also contains an 8-bit Receive Holding Register (RHR). Receive data is removed from the SC16C550 and receive FIFO by reading the RHR register. The receive section provides a mechanism to prevent false starts. On the falling edge of a start or false start bit, an internal receiver counter starts counting clocks at the 16 clock rate ...
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... FIFO reset when the FIFO is empty. 7.2.2 IER versus Receive/Transmit FIFO polled mode operation When FCR[0] = logic 1, resetting IER[0-3] enables the SC16C550 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR, either or both can be used in the polled mode by selecting respective transmit or receive control bit(s) ...
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... Logic 0 = Set DMA mode ‘0’ (normal default condition). Logic 1 = Set DMA mode ‘1’ Transmit operation in mode ‘0’: When the SC16C550 is in the 16C450 mode (FIFOs disabled; FCR[0] = logic the FIFO mode (FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no characters in the transmit FIFO or transmit holding register, the TXRDY pin will be a logic 0 ...
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... FIFO Control Register bits description Symbol Description Transmit operation in mode ‘1’: When the SC16C550 is in FIFO mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a logic 1 when the transmit FIFO is completely full. It will be a logic 0 if one or more FIFO locations are empty. ...
Page 24
... Philips Semiconductors 7.4 Interrupt Status Register (ISR) The SC16C550 provides six levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced ...
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... Logic 0 or cleared = default condition. LCR[1-0] Word length bits 1, 0. These two bits specify the word length to be transmitted or received (see Logic 0 or cleared = default condition. Rev. 05 — 19 June 2003 SC16C550 Table 15). Table 16). Table 17). © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... LCR[2] stop bit length Word length Stop bit length (bit times LCR[1-0] word length LCR[0] Word length Rev. 05 — 19 June 2003 SC16C550 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 27
... Loop-back. Enable the local loop-back mode (diagnostics). In this mode the transmitter output (TX) and the receiver input (RX), CTS, DSR, DCD, and RI are disconnected from the SC16C550 I/O pins. Internally the modem data and control pins are connected into a loop-back data configuration (see receiver and transmitter interrupts remain fully operational. The Modem Control Interrupts are also operational, but the interrupts’ ...
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... Philips Semiconductors 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C550 and the CPU. Table 19: Bit 9397 750 11619 Product data UART with 16-byte FIFO and IrDA encoder/decoder Line Status Register bits description ...
Page 29
... A modem Status Interrupt will be generated. [1] MSR[2] RI Logic change (normal default condition). Logic 1 = The RI input to the SC16C550 has changed from a logic logic 1. A modem Status Interrupt will be generated. Rev. 05 — 19 June 2003 SC16C550 …continued © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated. 7.9 Scratchpad Register (SPR) The SC16C550 provides a temporary data register to store 8 bits of user information. 7.10 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. Bits 0 through 4 provide single or dual character software flow control selection. ...
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... EFR[5] Special Character Detect. Logic 0 = Special character detect disabled (normal default condition). Logic 1 = Special character detect enabled. The SC16C550 compares each incoming receive character with Xoff2 data match exists, the received data will be transferred to FIFO and ISR[4] will be set to indicate detection of special character. Bit-0 in the X-registers corresponds with the LSB bit for the receive character. When this feature is enabled, the normal software fl ...
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... Philips Semiconductors 7.11 SC16C550 external reset conditions Table 23: Register IER ISR LCR MCR LSR MSR FCR EFR Table 24: Output TX RTS DTR RXRDY TXRDY 8. Limiting values Table 25: In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol amb T stg P tot(pack) ...
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... OH (databus (other outputs 800 A 1. (databus 400 A 1. (other outputs MHz - 3 500 - for a listing of pins having internal pull-up resistors. Rev. 05 — 19 June 2003 SC16C550 3.3 V 5.0 V Unit Min Max Min Max 0.3 0.6 0.5 0.6 V 2 0.3 0.8 0.5 0.8 V 2 ...
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... Rev. 05 — 19 June 2003 SC16C550 3.3 V 5.0 V Unit Max Min Max - MHz - ...
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... Min - 100 VALID ADDRESS t 6h VALID ACTIVE t 11d t 11d ACTIVE t t 12d 12h DATA Rev. 05 — 19 June 2003 SC16C550 3.3 V 5.0 V Max Min Max Min Max clock cycle. 1 002aaa331 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... ACTIVE t t 16s 16h DATA VALID t 7h ACTIVE ACTIVE t 12h t 12d DATA Rev. 05 — 19 June 2003 SC16C550 002aaa332 VALID ADDRESS ACTIVE t t 12d 12h 002aaa333 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... VALID t 7h ACTIVE t t 13w 15d ACTIVE t 16h t 16s DATA t 17d CHANGE OF STATE CHANGE OF STATE t 18d ACTIVE ACTIVE Rev. 05 — 19 June 2003 SC16C550 VALID ADDRESS ACTIVE t 13w t t 16s 16h 002aaa334 CHANGE OF STATE t 18d ACTIVE ACTIVE t 19d ACTIVE ACTIVE ...
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... UART with 16-byte FIFO and IrDA encoder/decoder DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS 16 BAUD RATE CLOCK Rev. 05 — 19 June 2003 SC16C550 002aaa112 NEXT DATA START PARITY STOP BIT BIT BIT 20d ACTIVE t 21d ...
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... Product data UART with 16-byte FIFO and IrDA encoder/decoder DATA BITS (5– DATA BITS (5– Rev. 05 — 19 June 2003 SC16C550 NEXT DATA PARITY STOP START BIT BIT BIT 25d ACTIVE DATA READY t 26d ...
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... DATA BITS (5– DATA BITS 6 DATA BITS 7 DATA BITS ACTIVE TX READY t 22d 16 BAUD RATE CLOCK Rev. 05 — 19 June 2003 SC16C550 NEXT DATA PARITY STOP START BIT BIT BIT 24d ACTIVE 002aaa116 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... Product data UART with 16-byte FIFO and IrDA encoder/decoder DATA BITS (5– TRANSMITTER READY t 27d ACTIVE Rev. 05 — 19 June 2003 SC16C550 NEXT DATA PARITY STOP START BIT BIT BIT 28d TRANSMITTER NOT READY 002aaa129 © ...
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... UART with 16-byte FIFO and IrDA encoder/decoder DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS t 28d FIFO FULL Rev. 05 — 19 June 2003 SC16C550 PARITY STOP BIT BIT D6 D7 002aaa118 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... UART with 16-byte FIFO and IrDA encoder/decoder UART FRAME DATA TX BIT TIME RX BIT TIME DATA Rev. 05 — 19 June 2003 SC16C550 DATA BITS 1/2 BIT TIME 3/16 BIT TIME 002aaa212 0-1 16X CLOCK DELAY DATA BITS UART FRAME © ...
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... 16.66 16.66 16.00 16.00 17.65 17.65 1.22 1.27 16.51 16.51 14.99 14.99 17.40 17.40 1.07 0.656 0.656 0.63 0.63 0.695 0.695 0.048 0.05 0.650 0.650 0.59 0.59 0.685 0.685 0.042 REFERENCES JEDEC JEITA MS-018 EDR-7319 Rev. 05 — 19 June 2003 SC16C550 SOT187 detail X (1) ( max. max. 1.44 0.18 0.18 0.1 2.16 2.16 1. ...
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... 2 scale (1) ( 0.18 7.1 7.1 9.15 9.15 1 0.5 0.12 6.9 6.9 8.85 8.85 REFERENCES JEDEC JEITA MS-026 Rev. 05 — 19 June 2003 SC16C550 SOT313 detail X (1) ( 0.75 0.95 0.95 7 0.2 0.12 0.1 o 0.45 0.55 0.55 0 EUROPEAN ISSUE DATE PROJECTION 00-01-19 03-02-25 © ...
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... 0.53 0.36 52.5 14.1 2.54 0.38 0.23 51.5 13.7 0.021 0.014 2.067 0.56 0.1 0.015 0.009 2.028 0.54 REFERENCES JEDEC JEITA MO-015 SC-511-40 Rev. 05 — 19 June 2003 SC16C550 3.60 15.80 17.42 15.24 0.254 3.05 15.24 15.90 0.14 0.62 0.69 0.6 0.01 0.12 0.60 0.63 EUROPEAN ISSUE DATE PROJECTION ...
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... C (SnPb process) or below 245 C (Pb-free process) – for all the BGA and SSOP-T packages 9397 750 11619 Product data UART with 16-byte FIFO and IrDA encoder/decoder Rev. 05 — 19 June 2003 SC16C550 ). stg(max) © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... UART with 16-byte FIFO and IrDA encoder/decoder 2.5 mm thick/large packages. parallel to the transport direction of the printed-circuit board; transport direction of the printed-circuit board. Rev. 05 — 19 June 2003 SC16C550 3 350 mm so called 3 so called small/thin packages. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
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... HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS [6] PLCC , SO, SOJ suitable LQFP, QFP, TQFP not recommended SSOP, TSSOP, VSO, not recommended VSSOP Rev. 05 — 19 June 2003 SC16C550 [2] Reflow Dipping [3] suitable suitable [5] suitable suitable [6][7] suitable [8] suitable 10 C measured in the atmosphere of the reflow © ...
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... Product data (9397 750 09836); ECN 853-2366 28865 of 04 September 2002. 9397 750 11619 Product data UART with 16-byte FIFO and IrDA encoder/decoder 15: changed capacitors’ values and Rev. 05 — 19 June 2003 SC16C550 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Rev. 05 — 19 June 2003 SC16C550 Fax: + 24825 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
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... Scratchpad Register (SPR 7.10 Enhanced Feature Register (EFR 7.11 SC16C550 external reset conditions . . . . . . . 32 © Koninklijke Philips Electronics N.V. 2003. Printed in the U.S.A All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice ...