CXA2006Q Sony, CXA2006Q Datasheet
CXA2006Q
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CXA2006Q Summary of contents
Page 1
... Digital CCD Camera Head Amplifier Description The CXA2006Q is a bipolar IC developed as a head amplifier for digital CCD cameras. This IC provides the following functions: correlated double sampling, AGC for the CCD signal, GCA for the low- band chroma signal, AMP for high-band chroma and line signals, A/D sample and hold, blanking, A/D reference voltage, and an output driver ...
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... RFCONT CENTER BIAS 32 PBRFC MODE SWITCHING AGCCLP LPF CAMSH AGC REF BOTTOM LIN/ AMP VISH GCA – 2 – CXA2006Q 18 17 AGCCLP 16 CLPOB 15 BLK XRS 14 REF 13 PBLK TOP OFFSET 12 OFFSET SW VRT 11 CH/CL VRB 10 DC DRV ...
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... CXA2006Q ( 4.75V) CC Description Camera and video signal selector. 68k Chroma signal and composite video signal selector. 1.35V High-band chroma signal and low-band chroma signal selector ...
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... SW1 SW2 OFFSET 13.75k 2V 2k 10k 100µA 1.1k 3.75k 4V 3k 20k 100µA 100µA 100µA – 4 – CXA2006Q Description Driver output for A/D 8 converter capable of DRVOUT DC coupling. Dynamic range = 2Vp-p 30k SW1 SW2 Mode CAM 1 0 LIN ...
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... CXA2006Q Description Controls the output offset during camera mode. When 0V: 12 less than (VRB – 200mV) When 3.0V: 10k greater than (VRB + 300mV) Camera signal pre- blanking pulse input. ...
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... CXA2006Q Description AGC clamp capacitor. 16 (Recommended value: 0.1µF) AGC gain control. When 0V: 8dB 38k (Minimum gain) When 3.0V: 38dB (Maximum gain) 20µA 20µA Enables monitoring of the SHD output camera signal ...
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... CXA2006Q Description 66k Clamp pulse used to clamp the dummy 1.45V pixel portion of the input CCD signal. 29k 2k CCD signal input. 2k 10k LIN mode Common input for 2µA the composite video ...
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... CXA2006Q Description 50µA 41k Gain control for the low-band chroma signal (CL). When 0V: 3.5dB (Minimum gain) When 3.0V: 15.5dB 0.86V (Maximum gain) 9k 100µA Low-band chroma signal (CL) input. ...
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... BLKOF (PBLK = 3V) – BLKOF (PBLK = 0V) LIN/CH = 3MHz, 500mVp-p, sine wave + offset voltage LIN/CH = 3MHz, 500mVp-p, sine wave RFCONT = 3V 15kHz 80mVp-p sine wave RFCONT = 0V 15kHz 400mVp-p sine wave – 9 – CXA2006Q 1, 2 and 3 = 4.5V OPEN Min. Typ. Max. Unit and V RB ...
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... L H 0.1µ PL7 V10 GND GND GND GND GND GND SW1 SW2 – 10 – CXA2006Q V12 AGCCLP 0.1µ 16 PL4 CLPOB 15 BLK PL5 XRS 14 PL6 PBLK REF 13 TOP V15 OFFSET 12 C9 4.7 µ SW ...
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... PL1 (CLPDM) PL6 (PBLK) V5 (DIN) Equivalent to CCD signal black level V3 (CH) V4 (PBRFC (LIN) PL2 (SHD) PL3 (SHP) PL5 (XRS) PL7 (VSHP) 1H 2µs 1H 2µs 1H Different for each test – 11 – CXA2006Q 1.5V GND 1.5V GND 1.5V GND Different for each test 2.5V GND ...
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... LIN/CH SW C/V SW OFFSET AMP VISH DRV GCA LOUTCLP 0.1µ VSHP GND GND GND GND GND GND – 12 – CXA2006Q 17 C7 AGCCLP 0.1µ 16 CLPOB 15 XRS 14 PBLK 13 OFFSET 4.7µF VRT 11 VRB CH/ 4.7µ ...
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... BLK output CAMVISW output DRVOUT output = 4.75V) CC Idle transfer OPB interval interval Signal level Basic black level 2.16V [ 3] 2µs 2.16V – 13 – CXA2006Q Sig interval 2. 2.7V 2µs Black level 10µs 2.16V [ Approx. 2.65V when OFFSET = 3V Approx. 1.73V when OFFSET = 0V ...
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... CH/CL DC [CH/CLDC], which gives center potential to the high-band chroma and low-band chroma signals of the video signal. DRV: DRV drives the external A/D. Camera and video (LIN, CH, CL modes) signals are input by switching C/VSW, and offset adjusted signals are output from DRVOUT pin. AGCCONT – 14 – CXA2006Q from 0 to 3V. ...
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... The video signal processing system operates in CL signal mode when PS is high, CAM/VIDEO is low, PB/REC is high and CH/CL is low, or when PS is high, CAM/VIDEO is low, PB/REC is high and CH/CL is high. Video signal processing system timing chart LIN mode LIN/CH input AMP output 9.5dB VISP DRVOUT output – 15 – CXA2006Q and RT 2.4V 2.1V 2.1V ...
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... VISW switches between the LIN, CH and CL low-band chroma signals for the video signal processing system. The signals are switched according to the mode selection. LOUTCLP: LOUTCLP is a clamp circuit which operates when the LIN signal is output to the DRV. The clamp potential is the sync portion, and is 2.1V. – 16 – CXA2006Q ...
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... DC bias so that the center potential of the SIN signal is 2.7V to allow full input. The input level and frequency are respectively 470mVp-p (Max.) and from 1 to 7MHz. CH/CL DC: CH/ bias circuit which operates when the CH signal is output to the DRV. The DC bias potential is 3V. CH mode LIN/CH input AMPOUT output 9.1dB VISH DRVOUT output – 17 – CXA2006Q 2. ...
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... The GCA amplifier controls the gain of the CL signal input to PBRFC. The gain can be varied from 0.4 to 20.5dB by adjusting the RFCONT voltage from 0 to 3V. CH/CL DC: CH/ bias circuit which operates when the CL signal is output to the DRV. The DC bias potential is 3V. CL mode PBREC input GCAOUT output 0.4 to 20.5dB VISH DRVOUT output – 18 – CXA2006Q 2.94V 3V 3V ...
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... CL mode RFGCA gain control supply voltage characteristics V vs. Gain AGCCONT 4. 5. 0.0 1.0 2.0 V [V] AGCCONT V vs. OFFSET OFFSET 0 0.0 1.0 2.0 V [V] OFFSET V vs. Gain RFCONT 4. 5. 0.0 1.0 2.0 V [V] RFCONT – 19 – CXA2006Q 3 4. 4.75V 5.0V CC 3.0 3.0 ...
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... V OFFSET CL mode RFGCA gain control temperature characteristics V vs. Gain RFCONT –1 0.0 1.0 V RFCONT – 20 – = 4.75V) CC –20°C 27°C 75° 4.75V CC 2.0 3.0 75°C 27°C –20° 4.75V CC 2.0 3.0 [V] –20°C 27°C 75° 4.75V CC 2.0 3.0 [V] CXA2006Q ...
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... CC 2.60 2.50 – [°C] CH mode AMP gain temperature characteristics Ta vs. Gain (CH mode – [°C] LIN mode AMP gain temperature characteristics Ta vs. Gain (CL mode – [°C] – 21 – CXA2006Q V = 4.75V 4.75V CC 60 ...
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... OUT = 1.8Vp-p –40 –45 –50 –55 3rd: OUT = 1.4Vp-p –60 –65 –70 = 4.5V –75 –80 60 – – 22 – CXA2006Q 2nd: OUT = 1.4Vp-p 3rd: OUT = 1.8Vp 5MHz [°C] 2nd: OUT = 1.8Vp-p 2nd: OUT = 1.4Vp 5MHz [°C] ...
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... SONY CODE QFP-32P-L01 QFP032-P-0707 EIAJ CODE JEDEC CODE 32PIN QFP (PLASTIC 0.15 0.3 – 0.1 0.24 M PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS – 23 – CXA2006Q 0.1 + 0.35 1.5 – 0.15 + 0.2 0.1 – 0.1 + 0.1 0.127 – 0.05 0° to 10° EPOXY RESIN SOLDER PLATING 42 ALLOY 0.2g ...