UPD78F0134M2GB-8EU Renesas Electronics Corporation., UPD78F0134M2GB-8EU Datasheet
UPD78F0134M2GB-8EU
Related parts for UPD78F0134M2GB-8EU
UPD78F0134M2GB-8EU Summary of contents
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User’s Manual 78K0/KE1 8-Bit Single-Chip Microcontrollers µ µ PD780131 PD780131(A) µ µ PD780132 PD780132(A) µ µ PD780133 PD780133(A) µ µ PD780134 PD780134(A) µ µ PD780136 PD780136(A) µ µ PD780138 PD780138(A) µ µ PD78F0134 PD78F0134(A) µ µ PD78F0138 PD78F0138(A) Document No. ...
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User’s Manual U16228EJ3V1UD ...
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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...
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EEPROM is a trademark of NEC Electronics Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/ trademark of International Business Machines Corporation. HP9000 series 700 ...
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Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and ...
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Readers This manual is intended for user engineers who wish to understand the functions of the 78K0/KE1 and design and develop application systems and programs for these devices. The target products are as follows. 78K0/KE1: Purpose This manual is intended ...
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How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. • When using this manual as the manual for (A) grade products, (A1) grade products, and ...
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Differences Between 78K0/KE1 and 78K0/KE1+ Series Name Item Mask ROM version Flash Power supply memory Self-programming function version Option byte Version with on-chip debug function Regulator Power-on clear function Minimum instruction execution time Related Documents The related documents indicated in ...
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Documents Related to Development Tools (Hardware) (User’s Manuals) IE-78K0-NS In-Circuit Emulator IE-78K0-NS-A In-Circuit Emulator IE-78K0K1-ET In-Circuit Emulator QB-78K0KX1H In-Circuit Emulator IE-780148-NS-EM1 Emulation Board Documents Related to Flash Memory Programming PG-FP3 Flash Memory Programmer User’s Manual PG-FP4 Flash Memory Programmer User’s ...
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CHAPTER 1 OUTLINE ............................................................................................................................ 18 1.1 Expanded-Specification Products and Conventional Products (Standard Products, (A) Grade Products Only) ...................................................................... 18 1.2 Features ...................................................................................................................................... 19 1.3 Applications................................................................................................................................ 20 1.4 Ordering Information ................................................................................................................. 21 1.5 Pin Configuration (Top View).................................................................................................... 28 1.6 Kx1 Series ...
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Special function register (SFR) area...............................................................................................64 3.1.4 Data memory addressing ...............................................................................................................65 3.2 Processor Registers .................................................................................................................. 73 3.2.1 Control registers .............................................................................................................................73 3.2.2 General-purpose registers ..............................................................................................................77 3.2.3 Special function registers (SFRs) ...................................................................................................78 3.3 Instruction Address Addressing .............................................................................................. 83 3.3.1 Relative addressing ........................................................................................................................83 ...
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Registers Controlling Clock Generator ................................................................................. 124 5.4 System Clock Oscillator .......................................................................................................... 131 5.4.1 X1 oscillator ..................................................................................................................................131 5.4.2 Subsystem clock oscillator............................................................................................................131 5.4.3 When subsystem clock is not used...............................................................................................134 5.4.4 Internal oscillator...........................................................................................................................134 5.4.5 Prescaler.......................................................................................................................................134 5.5 Clock Generator Operation ..................................................................................................... 135 5.6 ...
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Operation of 8-Bit Timers H0 and H1 ..................................................................................... 221 8.4.1 Operation as interval timer/square-wave output ...........................................................................221 8.4.2 Operation as PWM output mode ..................................................................................................224 8.4.3 Carrier generator mode operation (8-bit timer H1 only) ................................................................230 CHAPTER 9 WATCH TIMER ............................................................................................................... 237 ...
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Cautions for A/D Converter..................................................................................................... 275 CHAPTER 13 SERIAL INTERFACE UART0 ...................................................................................... 280 13.1 Functions of Serial Interface UART0...................................................................................... 280 13.2 Configuration of Serial Interface UART0 ............................................................................... 281 13.3 Registers Controlling Serial Interface UART0....................................................................... 284 13.4 Operation of Serial Interface ...
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CHAPTER 18 KEY INTERRUPT FUNCTION ..................................................................................... 386 18.1 Functions of Key Interrupt ...................................................................................................... 386 18.2 Configuration of Key Interrupt................................................................................................ 386 18.3 Register Controlling Key Interrupt......................................................................................... 387 CHAPTER 19 STANDBY FUNCTION.................................................................................................. 388 19.1 Standby Function and Configuration .................................................................................... 388 19.1.1 Standby ...
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Program Execution Flow ......................................................................................................... 441 26.7 Cautions for ROM Correction ................................................................................................. 443 µ CHAPTER 27 PD78F0134, 78F0138.................................................................................................. 444 27.1 Internal Memory Size Switching Register.............................................................................. 445 27.2 Internal Expansion RAM Size Switching Register ................................................................ 446 27.3 Writing with Flash Programmer.............................................................................................. ...
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Cautions for Wait ..................................................................................................................... 560 35.2 Peripheral Hardware That Generates Wait ............................................................................ 561 35.3 Example of Wait Occurrence .................................................................................................. 562 APPENDIX A DEVELOPMENT TOOLS .............................................................................................. 563 A.1 Software Package .................................................................................................................... 567 A.2 Language Processing Software ............................................................................................. 567 A.3 Control ...
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Expanded-Specification Products and Conventional Products (Standard Products, (A) Grade Products Only) The expanded-specification products and conventional products refer to the following products. Expanded-specification product: Products with a rank µ • PD780131, 780132, 780133, and 780134 for which orders were ...
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Features Minimum instruction execution time can be changed from high speed (0.166 input clock) to ultra low-speed (122 General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks) ROM, RAM capacities Item Part Number ...
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A/D converter: 8 channels Supply voltage 2 2 3 Operating ambient temperature: T Notes 1. Use these products in the ...
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Ordering Information (1) Mask ROM version (1/3) Part Number µ PD780131GB-×××-8EU µ PD780131GC-×××-8BS µ PD780131GK-×××-9ET µ PD780132GB-×××-8EU µ PD780132GC-×××-8BS µ PD780132GK-×××-9ET µ PD780133GB-×××-8EU µ PD780133GC-×××-8BS µ PD780133GK-×××-9ET µ PD780134GB-×××-8EU µ PD780134GC-×××-8BS µ PD780134GK-×××-9ET µ PD780136GB-×××-8EU µ PD780136GC-×××-8BS µ PD780136GK-×××-9ET ...
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Mask ROM version (2/3) Part Number µ PD780131GB(A)-×××-8EU µ PD780131GC(A)-×××-8BS µ PD780131GK(A)-×××-9ET µ PD780132GB(A)-×××-8EU µ PD780132GC(A)-×××-8BS µ PD780132GK(A)-×××-9ET µ PD780133GB(A)-×××-8EU µ PD780133GC(A)-×××-8BS µ PD780133GK(A)-×××-9ET µ PD780134GB(A)-×××-8EU µ PD780134GC(A)-×××-8BS µ PD780134GK(A)-×××-9ET µ PD780136GB(A)-×××-8EU µ PD780136GC(A)-×××-8BS µ PD780136GK(A)-×××-9ET µ PD780138GB(A)-×××-8EU µ ...
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Mask ROM version (3/3) Part Number µ PD780131GB(A2)-×××-8EU µ PD780131GC(A2)-×××-8BS µ PD780131GK(A2)-×××-9ET µ PD780132GB(A2)-×××-8EU µ PD780132GC(A2)-×××-8BS µ PD780132GK(A2)-×××-9ET µ PD780133GB(A2)-×××-8EU µ PD780133GC(A2)-×××-8BS µ PD780133GK(A2)-×××-9ET µ PD780134GB(A2)-×××-8EU µ PD780134GC(A2)-×××-8BS µ PD780134GK(A2)-×××-9ET µ PD780136GB(A2)-×××-8EU µ PD780136GC(A2)-×××-8BS µ PD780136GK(A2)-×××-9ET µ PD780138GB(A2)-×××-8EU µ ...
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Flash memory version (1/3) Part Number µ PD78F0134M1GB-8EU µ PD78F0134M1GC-8BS µ PD78F0134M1GK-9ET µ PD78F0134M2GB-8EU µ PD78F0134M2GC-8BS µ PD78F0134M2GK-9ET µ PD78F0134M3GB-8EU µ PD78F0134M3GC-8BS µ PD78F0134M3GK-9ET µ PD78F0134M4GB-8EU µ PD78F0134M4GC-8BS µ PD78F0134M4GK-9ET µ PD78F0134M5GB-8EU µ PD78F0134M5GC-8BS µ PD78F0134M5GK-9ET µ PD78F0134M6GB-8EU µ ...
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Flash memory version (2/3) Part Number µ PD78F0134M3GK-9ET-A µ PD78F0134M4GB-8EU-A µ PD78F0134M4GC-8BS-A µ PD78F0134M4GK-9ET-A µ PD78F0134M5GB-8EU-A µ PD78F0134M5GC-8BS-A µ PD78F0134M5GK-9ET-A µ PD78F0134M6GB-8EU-A µ PD78F0134M6GC-8BS-A µ PD78F0134M6GK-9ET-A µ PD78F0138M1GB-8EU-A µ PD78F0138M1GC-8BS-A µ PD78F0138M1GK-9ET-A µ PD78F0138M2GB-8EU-A µ PD78F0138M2GC-8BS-A µ PD78F0138M2GK-9ET-A µ ...
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Flash memory version (3/3) Part Number µ PD78F0134M6GB(A)-8EU µ PD78F0134M6GC(A)-8BS µ PD78F0134M6GK(A)-9ET µ PD78F0138M1GB(A)-8EU µ PD78F0138M1GC(A)-8BS µ PD78F0138M1GK(A)-9ET µ PD78F0138M2GB(A)-8EU µ PD78F0138M2GC(A)-8BS µ PD78F0138M2GK(A)-9ET µ PD78F0138M3GB(A)-8EU µ PD78F0138M3GC(A)-8BS µ PD78F0138M3GK(A)-9ET µ PD78F0138M4GB(A)-8EU µ PD78F0138M4GC(A)-8BS µ PD78F0138M4GK(A)-9ET µ PD78F0138M5GB(A)-8EU µ ...
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Mask ROM versions ( PD780131, 780132, 780133, 780134, 780136, and 780138) include mask options. When ordering possible to select “Power-on-clear (POC) circuit can be used/cannot be used”, “Internal oscillator can be stopped/cannot be stopped by software” and ...
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Pin Configuration (Top View) • 64-pin plastic LQFP (10 × 10) • 64-pin plastic LQFP (14 × 14) • 64-pin plastic TQFP (12 × 12 ...
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Pin Identification ANI0 to ANI7: Analog input AV : Analog reference voltage REF AV : Analog ground SS BUZ: Buzzer output EV : Power supply for port Ground for port SS IC: Internally connected INTP0 to INTP7: ...
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FBGA (6 × PD780134 standard product only) Top View Pin No. Pin Name Pin No. A1 P31/INTP2 C1 A2 P32/INTP3 C2 A3 XT2 ...
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Kx1 Series Lineup 1.6.1 78K0/Kx1, 78K0/Kx1+ product lineup • 30-pin SSOP (7.62 mm 0.65 mm pitch) 78K0/KB1 µ PD78F0103 Two-power-supply flash memory: 24 KB, RAM: 768 B • × 44-pin LQFP (10 78K0/KC1 µ PD78F0114 Two-power-supply flash memory: 32 ...
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The list of functions in the 78K0/Kx1 is shown below. Part Number 78K0/KB1 Item Number of pins Internal Mask ROM 8 memory (KB) Flash memory RAM 0.5 Power supply voltage Minimum instruction execution time 0.166 4.0 to 5.5 V) 0.2 ...
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The list of functions in the 78K0/Kx1+ is shown below. Part Number 78K0/KB1+ Item Number of pins Internal Flash memory 8 memory RAM 0.5 (KB) Power supply voltage Minimum instruction execution time Clock Crystal/ceramic RC Subclock Internal oscillation Ports CMOS ...
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V850ES/Kx1, V850ES/Kx1+ product lineup 64-pin plastic LQFP (10 × 10 mm, 0.5 mm pitch) • 64-pin plastic TQFP (12 × 12 mm, 0.65 mm pitch) • 64-pin plastic LQFP (14 × 14 mm, 0.8 mm pitch) • V850ES/KE1 µ ...
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The list of functions in the V850ES/Kx1 is shown below. Part Number Item Number of pins Internal Mask ROM 96/128 memory (bytes) Flash memory RAM Power supply voltage Minimum instruction execution time Clock X1 input Subclock Internal oscillation Ports CMOS ...
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The list of functions in the V850ES/Kx1+ is shown below. Part Number Item Number of pins Internal Mask ROM 96/128 memory Flash memory (bytes) RAM Power supply voltage Minimum instruction execution time Clock X1 input Subclock Internal oscillation Ports CMOS ...
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Block Diagram TO00/TI010/P01 16-bit timer/ event counter 00 TI000/P00 Note 1 Note 1 TO01 /TI011 /P06 16-bit timer/ Note 1 event counter 01 TI001 /P05 TOH0/P15 8-bit timer H0 TOH1/P16 8-bit timer H1 8-bit timer/ TI50/TO50/P17 event counter 50 ...
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Outline of Functions µ Item PD780131 Internal Mask ROM 8 K memory Flash memory (bytes) High-speed RAM 512 Expansion RAM Memory space input clock (oscillation Ceramic/crystal/external clock oscillation frequency) • REGC pin is connected directly to ...
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Item PD780131 • 16-bit timer/event counter: 2 channels (1 channel only in the Timers • 8-bit timer/event counter: • 8-bit timer: • Watch timer • Watchdog timer: Timer outputs 5 (PWM output: 4) Clock output • 78.125 kHz, 156.25 ...
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An outline of the timer is shown below. Operation Interval timer 1 channel 1 channel 1 channel 1 channel 1 channel 1 channel mode External event counter 1 channel 1 channel 1 channel 1 channel Watchdog timer Function Timer output ...
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Pin Function List There are three types of pin I/O buffer power supplies: AV power supplies and the pins is shown below. Power Supply AV REF (1) Port pins (1/2) Pin Name I/O P00 I/O ...
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Port pins (2/2) Pin Name I/O P40 to P43 I/O Port 4. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P50 to P53 I/O ...
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Non-port pins (1/2) Pin Name I/O INTP0 Input External interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be INTP1 to INTP3 specified INTP4 INTP5 INTP6 INTP7 SI10 Input ...
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Non-port pins (2/2) Pin Name I/O AV Input A/D converter reference voltage input and positive power REF supply for port 2 − AV A/D converter ground potential. Make the same potential KR0 to ...
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Description of Pin Functions 2.2.1 P00 to P06 (port 0) P00 to P06 function as a 7-bit I/O port. These pins also function as timer I/O, serial interface data I/O, clock I/O, and chip select input. The following operation ...
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P10 to P17 (port 1) P10 to P17 function as an 8-bit I/O port. These pins also function as pins for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. The following operation modes can ...
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P30 to P33 (port 3) P30 to P33 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input and timer I/O. The following operation modes can be specified in 1-bit units. (1) ...
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P120 (port 12) P120 functions as a 1-bit I/O port. This pin also functions as a pin for external interrupt request input. The following operation modes can be specified. (1) Port mode P120 functions as a 1-bit I/O port. ...
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RESET This is the active-low system reset input pin. 2.2.15 REGC This is the pin for connecting the capacitor for the regulator. When using the regulator, connect this pin to V µ capacitor (1 F: recommended). When the regulator ...
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Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins. Refer to Figure 2-1 for the configuration of the I/O circuit of each type. ...
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Pin Name I/O Circuit Type RESET 2 XT1 16 XT2 AV REF Notes 1. Except for rank K and rank I products. When using rank K or rank I products, connect as follows. <When regulator ...
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Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 3-C P-ch Data N-ch Type 5-A Pullup enable V Data Output disable Input enable 52 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/2) Type 8-A Pullup enable Data ...
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Figure 2-1. Pin I/O Circuit List (2/2) Type 13-S Mask option Data N-ch Output disable Type 13-V Mask option Data N-ch Output disable Input enable Middle-voltage input buffer CHAPTER 2 PIN FUNCTIONS Type 13-W ...
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Memory Space Products in the 78K0/KE1 can each access memory space. Figures 3-1 to 3-8 show the memory maps. Caution Regardless of the internal memory capacity, the initial values of the internal memory size switching register ...
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Figure 3-1. Memory Map ( PD780131 Special function registers (SFR) 256 General-purpose registers 32 8 bits ...
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Special function registers General-purpose Internal high-speed RAM ...
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Figure 3-3. Memory Map ( PD780133 Special function registers (SFR) 256 General-purpose registers 32 8 bits ...
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Special function registers General-purpose Internal high-speed RAM ...
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Figure 3-5. Memory Map ( PD78F0134 Special function registers (SFR) 256 General-purpose registers 32 8 bits ...
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FFFFH Special function registers FF00H FEFFH General-purpose FEE0H FEDFH Internal high-speed RAM FB00H FAFFH Data memory space F800H F7FFH Internal expansion RAM F400H F3FFH C000H BFFFH Program memory space 0000H 60 CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Memory Map ( ...
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Figure 3-7. Memory Map ( PD780138) FFFFH Special function registers 256 FF00H FEFFH General-purpose registers 32 FEE0H FEDFH Internal high-speed RAM 1024 FB00H FAFFH Reserved Data memory space F800H F7FFH Internal expansion RAM 1024 F400H F3FFH Reserved F000H EFFFH Program ...
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FFFFH Special function registers FF00H FEFFH General-purpose FEE0H FEDFH Internal high-speed RAM FB00H FAFFH Data memory space F800H F7FFH Internal expansion RAM F400H F3FFH F000H EFFFH Program memory space 0000H 62 CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Memory Map ( ...
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Internal program memory space The internal program memory space stores the program and table data. Normally addressed with the program counter (PC). 78K0/KE1 products incorporate internal ROM (mask ROM or flash memory), as shown below. Part Number ...
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CALLF instruction entry area The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF). 3.1.2 Internal data memory space 78K0/KE1 products incorporate the following RAMs. (1) Internal high-speed RAM Table 3-4. Internal ...
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Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for ...
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Figure 3-10. Correspondence Between Data Memory and Addressing ( PD780132 Special function registers (SFR) 256 8 bits ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-11. Correspondence Between Data Memory and Addressing ( PD780133 Special function registers (SFR) 256 8 bits ...
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Figure 3-12. Correspondence Between Data Memory and Addressing ( PD780134 Special function registers (SFR) 256 8 bits ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-13. Correspondence Between Data Memory and Addressing ( PD78F0134 Special function registers (SFR) 256 8 bits ...
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Figure 3-14. Correspondence Between Data Memory and Addressing ( PD780136) FFFFH Special function registers (SFR) 256 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 1024 8 bits FE20H FE1FH FB00H FAFFH Reserved ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-15. Correspondence Between Data Memory and Addressing ( PD780138) FFFFH Special function registers (SFR) 256 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 1024 8 bits FE20H ...
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Figure 3-16. Correspondence Between Data Memory and Addressing ( PD78F0138) FFFFH Special function registers (SFR) 256 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 1024 8 bits FE20H FE1FH FB00H FAFFH Reserved ...
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Processor Registers The 78K0/KE1 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and ...
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Zero flag (Z) When the operation result is zero, this flag is set (1 reset (0) in all other cases. (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-20. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H) FEE0H FEE0H SP FEDFH FEDEH SP FEDEH (b) CALL, CALLF, CALLT instructions (when SP = FEE0H) SP FEE0H FEE0H ...
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Figure 3-21. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH (c) RETI, RETB instructions (when SP = FEDDH CHAPTER 3 CPU ARCHITECTURE FEE0H FEE0H FEDFH Register ...
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General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers ( and H). ...
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Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer and bit ...
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Table 3-6. Special Function Register List (1/4) Address Special Function Register (SFR) Name FF00H Port register 0 FF01H Port register 1 FF02H Port register 2 FF03H Port register 3 FF04H Port register 4 FF05H Port register 5 FF06H Port register ...
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Table 3-6. Special Function Register List (2/4) Address Special Function Register (SFR) Name FF2CH Port mode register 12 FF2EH Port mode register 14 FF30H Pull-up resistor option register 0 FF31H Pull-up resistor option register 1 FF33H Pull-up resistor option register ...
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Table 3-6. Special Function Register List (3/4) Address Special Function Register (SFR) Name FF68H Multiplier/divider control register 0 FF69H 8-bit timer H mode register 0 FF6AH Timer clock selection register 50 FF6BH 8-bit timer mode control register 50 FF6CH 8-bit ...
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Table 3-6. Special Function Register List (4/4) Address Special Function Register (SFR) Name Note 1 FFB7H Prescaler mode register 01 FFB8H Capture/compare control register 01 FFB9H 16-bit timer output control register 01 FFBAH 16-bit timer mode control register 00 FFBBH ...
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Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is ...
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Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and ...
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Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits the immediate data of an operation code are transferred to the program counter (PC) and branched. This ...
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Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register that functions as an accumulator (A and AX) among the general-purpose registers ...
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Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes (Rn and RPn operation code. Register addressing is carried ...
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Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. [Operand format] [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code [Illustration ...
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Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function ...
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Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the ...
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Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing ...
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Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and ...
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Based indexed addressing [Function] The register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank ...
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Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation ...
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Port Functions There are two types of pin I/O buffer power supplies: AV supplies and the pins is shown below. Power Supply AV REF EV DD 78K0/KE1 products are provided with the ports shown in Figure 4-1, which enable ...
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Pin Name I/O P00 I/O Port 0. 7-bit I/O port. P01 Input/output can be specified in 1-bit units. P02 Use of an on-chip pull-up resistor can be specified by a P03 software setting. P04 P05 P06 P10 I/O Port 1. ...
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Pin Name I/O P120 I/O Port 12. 1-bit I/O port. Use of an on-chip pull-up resistor can be specified by a software setting. P130 Output Port 13. 1-bit output-only port. P140 I/O Port 14. 2-bit I/O port. P141 Input/output can ...
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Port 0 Port 7-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P06 ...
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Figure 4-3. Block Diagram of P01 and P06 WR PU PU0 PU01, PU06 Alternate function RD WR PORT Output latch (P01, P06 PM0 PM01, PM06 Alternate function µ Note Available only in the PD780133, 780134, 78F0134, 780136, 780138, ...
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WR PU PU0 PU02 RD WR PORT Output latch (P02 PM0 PM02 Alternate function µ Note Available only in the PD780133, 780134, 78F0134, 780136, 780138, and 78F0138. PU0: Pull-up resistor option register 0 PM0: Port mode register 0 ...
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WR PU PU0 PU04 Alternate function RD WR PORT Output latch (P04 PM0 PM04 Alternate function µ Note Available only in the PD780133, 780134, 78F0134, 780136, 780138, and 78F0138. PU0: Pull-up resistor option register 0 PM0: Port mode ...
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Port 1 Port 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P11 and P14 WR PU PU1 PU11, PU14 Alternate function RD WR PORT Output latch (P11, P14 PM1 PM11, PM14 PU1: Pull-up resistor option register 1 PM1: Port mode ...
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Figure 4-8. Block Diagram of P12 and P15 WR PU PU1 PU12, PU15 RD WR PORT Output latch (P12, P15 PM1 PM12, PM15 Alternate function PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P13 WR PU PU1 PU13 RD WR PORT Output latch (P13 PM1 PM13 Alternate function PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal ...
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Figure 4-10. Block Diagram of P16 and P17 WR PU PU1 PU16, PU17 Alternate function RD WR PORT Output latch (P16, P17 PM1 PM16, PM17 Alternate function PU1: Pull-up resistor option register 1 PM1: Port mode register 1 ...
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Port 2 Port 8-bit input-only port. This port can also be used for A/D converter analog input. Figure 4-11 shows a block diagram of port 2. Figure 4-11. Block Diagram of P20 to P27 RD A/D ...
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Port 3 Port 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When used as an input ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of P33 WR PU PU3 PU33 Alternate function RD WR PORT Output latch (P33 PM3 PM33 Alternate function PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: ...
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Port 4 Port 4-bit I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). Use of an on-chip pull-up ...
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Port 5 Port 4-bit I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (PM5). Use of an on-chip pull-up ...
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Port 6 Port 4-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). This port has the following ...
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Port 7 Port 8-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When the P70 to P77 ...
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Port 12 Port 1-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input ...
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Port 13 Port 1-bit output-only port. Figure 4-19 shows a block diagram of port 13 PORT Output latch (P130) RD: Read signal WR××: Write signal Remark When reset is effected, P130 outputs a low ...
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Port 14 Port 2-bit I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (PM14). When the P140 and P141 ...
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Registers Controlling Port Function Port functions are controlled by the following three types of registers. • Port mode registers (PM0, PM1, PM3 to PM7, PM12, PM14) • Port registers (P0 to P7, P12 to P14) • Pull-up resistor option ...
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Table 4-5. Settings of Port Mode Register and Output Latch When Using Alternate Function Pin Name P00 TI000 P01 TI010 TO00 Note P02 SO11 Note P03 SI11 Note P04 SCK11 Note P05 SSI11 Note TI001 Note P06 TI011 Note TO01 ...
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Port registers (P0 to P7, P12 to P14) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is ...
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Pull-up resistor option registers (PU0, PU1, PU3 to PU5, PU7, PU12, and PU14) These registers specify whether the on-chip pull-up resistors of P00 to P06, P10 to P17, P30 to P33, P40 to P43, P50 to P53, P70 to ...
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Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as ...
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Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three system clock oscillators are available. • X1 oscillator The X1 oscillator oscillates a clock of f STOP ...
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Figure 5-1. Block Diagram of Clock Generator Main OSC Main clock control mode register register (MCM) (MOC) MCC CLS MSTOP MCS MCM0 STOP X1 X1 oscillator f XP Operation X2 clock switch Internal oscillator f R Mask option Prescaler 1: ...
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Registers Controlling Clock Generator The following six registers are used to control the clock generator. • Processor clock control register (PCC) • Internal oscillation mode register (RCM) • Main clock mode register (MCM) • Main OSC control register (MOC) ...
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Figure 5-2. Format of Processor Clock Control Register (PCC) Address: FFFBH After reset: 00H Symbol <7> <6> PCC MCC FRC MCC 0 Oscillation possible 1 Oscillation stopped FRC 0 On-chip feedback resistor used 1 On-chip feedback resistor not used CLS ...
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Remarks 1. MCM0: Bit 0 of the main clock mode register (MCM Main system clock oscillation frequency (X1 input clock oscillation frequency or internal X oscillation clock frequency Internal oscillation clock frequency R 4. ...
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Main clock mode register (MCM) This register sets the CPU clock (X1 input clock/internal oscillation clock). MCM can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears this register to 00H. Figure 5-4. Format of ...
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Main OSC control register (MOC) This register selects the operation mode of the X1 input clock. This register is used to stop the X1 oscillator operation when the CPU is operating with the internal oscillation clock. Therefore, this register ...
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Oscillation stabilization time counter status register (OSTC) This is the status register of the X1 input clock oscillation stabilization time counter. If the internal oscillation clock is used as the CPU clock, the X1 input clock oscillation stabilization time ...
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Oscillation stabilization time select register (OSTS) This register is used to select the X1 oscillation stabilization wait time when STOP mode is released. The wait time set by OSTS is valid only after STOP mode is released with the ...
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System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator connected to the X1 and X2 pins. An external clock can be input to the X1 oscillator when the REGC pin is ...
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Caution When using the X1 oscillator and subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the Figures 5-8 and 5-9 to avoid an adverse effect from wiring capacitance. • Keep the wiring length ...
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Figure 5-10. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (e) Signals are fetched Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, ...
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When subsystem clock is not used not necessary to use the subsystem clock for low power consumption operations and watch operations, connect the XT1 and XT2 pins as follows. XT1: Connect directly ...
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Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode. • X1 input clock f XP • Internal oscillation clock f R • Subsystem clock f XT ...
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Figure 5-12. Timing Diagram of CPU Default Start Using Internal Oscillator X1 input clock ( Internal oscillation clock ( Subsystem clock ( RESET CPU clock Operation stopped: 17 oscillation stabilization time: 2 ...
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A status transition diagram of this product is shown in Figure 5-13, and the relationship between the operation clocks in each operation status and between the oscillation control flag and oscillation status of each clock are shown in Tables 5-3 ...
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Figure 5-13. Status Transition Diagram (2/4) (2) When “Internal oscillator can be stopped by software” is selected by mask option Status 6 CPU clock Oscillation XP stopped f : Oscillating/ R oscillation stopped MCC = 0 ...
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Figure 5-13. Status Transition Diagram (3/4) (3) When “Internal oscillator cannot be stopped” is selected by mask option (when subsystem clock is not used) Interrupt HALT instruction Status 3 MCM0 = 0 CPU clock Oscillating XP ...
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Figure 5-13. Status Transition Diagram (4/4) (4) When “Internal oscillator cannot be stopped” is selected by mask option Status 5 CPU clock Oscillation stopped Oscillating R MCC = 0 MCC = 1 HALT ...
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Table 5-3. Relationship Between Operation Clocks in Each Operation Status Status X1 Oscillator MSTOP = 0 MSTOP = 1 Operation MCC = 0 MCC = 1 Mode Reset Stopped STOP HALT Oscillating Stopped Notes 1. When “Cannot be stopped” is ...
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Time Required to Switch Between Internal Oscillation Clock and X1 Input Clock Bit 0 (MCM0) of the main clock mode register (MCM) is used to switch between the internal oscillation clock and X1 input clock. In the actual switching ...
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Time Required for CPU Clock Switchover The CPU clock can be switched using bits (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC). The actual switchover operation is not performed immediately ...
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Clock Switching Flowchart and Register Setting 5.8.1 Switching from internal oscillation clock to X1 input clock Figure 5-14. Switching from Internal Oscillation Clock to X1 Input Clock (Flowchart) Register value after reset Internal oscillation X1 oscillation stabilization clock operation ...
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Switching from X1 input clock to internal oscillation clock Figure 5-15. Switching from X1 Input Clock to Internal Oscillation Clock (Flowchart) Register setting in X1 input clock operation Yes: RSTOP = 1 X1 input clock operation RSTOP = 0 ...
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Switching from X1 input clock to subsystem clock Figure 5-16. Switching from X1 Input Clock to Subsystem Clock (Flowchart) Register setting in X1 input clock operation X1 input clock operation Subsystem clock Note Set CSS to 1 after confirming ...
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Switching from subsystem clock to X1 input clock Figure 5-17. Switching from Subsystem Clock to X1 Input Clock (Flowchart) No: X1 oscillating Subsystem clock operation X1 input clock operation CHAPTER 5 CLOCK GENERATOR PCC.4 (CSS MCM = ...
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Register settings The table below shows the statuses of the setting flags and status flags when each mode is set. f Mode CPU X1 input Internal oscillator oscillating Note 2 clock Internal oscillator stopped Internal X1 oscillating oscillation clock ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 µ The PD780131 and 780132 incorporate 16-bit timer/event counter 00, and the 780136, 780138, and 78F0138 incorporate 16-bit timer/event counters 00 and 01. 6.1 Functions of 16-Bit Timer/Event Counters 00 and 01 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.2 Configuration of 16-Bit Timer/Event Counters 00 and 01 16-bit timer/event counters 00 and 01 include the following hardware. Table 6-1. Configuration of 16-Bit Timer/Event Counters 00 and 01 Item Timer counter ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-2. Block Diagram of 16-Bit Timer/Event Counter 01 µ ( PD780133, 780134, 78F0134, 780136, 780138, 78F0138 Only) Internal bus Capture/compare control register 01 (CRC01) CRC012CRC011 CRC010 To CR011 Noise elimi- TI011/TO01/P06 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (1) 16-bit timer counter 0n (TM0n) TM0n is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the input clock. Figure 6-3. ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Table 6-2. CR00n Capture Trigger and Valid Edges of TI00n and TI01n Pins (1) TI00n pin valid edge selected as capture trigger (CRC0n1 = 1, CRC0n0 = 1) CR00n Capture Trigger Falling ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) 16-bit timer capture/compare register 01n (CR01n) CR01n is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is used as a capture ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.3 Registers Controlling 16-Bit Timer/Event Counters 00 and 01 The following six registers are used to control 16-bit timer/event counters 00 and 01. • 16-bit timer mode control register 0n (TMC0n) • ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-6. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address FFBAH After reset: 00H R/W Symbol TMC00 TMC003 TMC003 TMC002 TMC001 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-7. Format of 16-Bit Timer Mode Control Register 01 (TMC01) Address FFB6H After reset: 00H R/W Symbol TMC01 TMC013 TMC013 TMC012 TMC011 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Capture/compare control register 0n (CRC0n) This register controls the operation of the 16-bit timer capture/compare registers (CR00n, CR01n). CRC0n can be set by a 1-bit or 8-bit memory manipulation instruction. RESET ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-9. Format of Capture/Compare Control Register 01 (CRC01) Address: FFB8H After reset: 00H Symbol 7 6 CRC01 0 0 CRC012 0 Operates as compare register 1 Operates as capture register CRC011 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-10. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FFBDH After reset: 00H Symbol 7 <6> TOC00 0 OSPT00 OSPT00 0 No one-shot pulse output trigger 1 One-shot pulse ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-11. Format of 16-Bit Timer Output Control Register 01 (TOC01) Address: FFB9H After reset: 00H Symbol 7 <6> TOC01 0 OSPT01 OSPT01 0 No one-shot pulse output trigger 1 One-shot pulse ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (4) Prescaler mode register 0n (PRM0n) This register is used to set the 16-bit timer counter 0n (TM0n) count clock and TI00n and TI01n input valid edges. PRM0n can be set by ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Cautions 1. When the internal oscillation clock is selected as the clock to be supplied to the CPU, the clock of the internal oscillator is divided and supplied as the count clock. ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-13. Format of Prescaler Mode Register 01 (PRM01) Address: FFB7H After reset: 00H Symbol 7 6 PRM01 ES111 ES110 ES111 ES110 ES011 ES010 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Remarks input clock oscillation frequency X 2. TI001, TI011: 16-bit timer/event counter 01 input pin 3. Figures in parentheses are for operation with f (5) Port mode register ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4 Operation of 16-Bit Timer/Event Counters 00 and 01 6.4.1 Interval timer operation Setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown in Figure 6-15 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-15. Control Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 0n (TMC0n TMC0n3 TMC0n (b) Capture/compare control register 0n ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-16. Interval Timer Configuration Diagram Note Note Note ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4.2 PPG output operations Setting 16-bit timer mode control register 0n (TMC0n) and capture/compare control register 0n (CRC0n) as shown in Figure 6-18 allows operation as PPG (Programmable Pulse Generator) output. Setting ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-18. Control Register Settings for PPG Output Operation (a) 16-bit timer mode control register 0n (TMC0n TMC0n (b) Capture/compare control register 0n (CRC0n) ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-19. Configuration Diagram of PPG Output Note Note Note ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00n pin and TI01n pin using 16-bit timer counter 0n (TM0n). There are ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (1) Pulse width measurement with free-running counter and one capture register When 16-bit timer counter 0n (TM0n) is operated in free-running mode, and the edge specified by prescaler mode register 0n (PRM0n) ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-23. Configuration Diagram for Pulse Width Measurement with Free-Running Counter Note Note Note f /2 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 0n (TM0n) is operated in free-running mode possible to simultaneously measure the pulse widths of the two ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-26. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) t Count clock 0000H 0001H TM0n count value TI00n pin input CR01n capture value INTTM01n TI01n pin ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 0n (TM0n) is operated in free-running mode possible to measure the pulse width of the ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-28. Timing of Pulse Width Measurement Operation with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) t Count clock TM0n count value 0000H 0001H TI00n pin input CR01n capture ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-29. Control Register Settings for Pulse Width Measurement by Means of Restart (a) 16-bit timer mode control register 0n (TMC0n TMC0n (b) Capture/compare ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4.4 External event counter operation Setting The basic operation setting procedure is as follows. <1> Set the CRC0n register (see Figure 6-31 for the set value). <2> Set the count clock by ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-31. Control Register Settings in External Event Counter Mode (with Rising Edge Specified) (a) 16-bit timer mode control register 0n (TMC0n TMC0n3 TMC0n ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-32. Configuration Diagram of External Event Counter Noise eliminator f X Valid edge of TI00n Note OVF0n is set to 1 only when CR00n is set to FFFFH. Figure 6-33. External ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4.5 Square-wave output operation Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM0n register. <2> Set the CRC0n register (see Figure 6-34 for ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-34. Control Register Settings in Square-Wave Output Mode (2/2) (c) 16-bit timer output control register 0n (TOC0n) 7 OSPT0n OSPE0n TOC0n4 LVS0n TOC0n ES1n1 ES1n0 ES0n1 ES0n0 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.4.6 One-shot pulse output operation 16-bit timer/event counter 0n can output a one-shot pulse in synchronization with a software trigger or an external trigger (TI00n pin input). Setting The basic operation setting ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-36. Control Register Settings for One-Shot Pulse Output with Software Trigger (a) 16-bit timer mode control register 0n (TMC0n TMC0n (b) Capture/compare control register 0n ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-37. Timing of One-Shot Pulse Output Operation with Software Trigger Set TMC0n to 04H (TM0n count starts) Count clock TM0n count 0000H 0001H CR01n set value N CR00n set value M ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-38. Control Register Settings for One-Shot Pulse Output with External Trigger (a) 16-bit timer mode control register 0n (TMC0n TMC0n (b) Capture/compare control register 0n ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 6-39. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) When TMC0n is set to 08H (TM0n count starts) t Count clock TM0n count value 0000H 0001H ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 6.5 Cautions for 16-Bit Timer/Event Counters 00 and 01 (1) Timer start errors An error one clock may occur in the time required for a match signal to be ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (6) Operation of OVF0n flag <1> The OFV0n flag is also set the following case. When any of the following modes is selected: the mode in which clear & ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (8) Timer operation <1> Even if 16-bit timer counter 0n (TM0n) is read, the value is not captured by 16-bit timer capture/compare register 01n (CR01n). <2> Regardless of the CPU’s operation mode, ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.1 Functions of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 have the following functions. • Interval timer • External event counter • Square-wave output • PWM output ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-2. Block Diagram of 8-Bit Timer/Event Counter 51 8-bit timer compare register 51 (CR51) TI51/TO51/P33/INTP4 8-bit timer counter ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.2 Configuration of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 include the following hardware. Table 7-1. Configuration of 8-Bit Timer/Event Counters 50 and 51 Item Timer register ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer compare register 5n (CR5n) CR5n can be read and written by an 8-bit memory manipulation instruction. Except in PWM mode, the value set in CR5n is constantly compared with ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 The following four registers are used to control 8-bit timer/event counters 50 and 51. • Timer clock selection register 5n (TCL5n) • 8-bit ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-6. Format of Timer Clock Selection Register 51 (TCL51) Address: FF8CH After reset: 00H Symbol 7 6 TCL51 0 0 TCL512 TCL511 ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer mode control register 5n (TMC5n) TMC5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (TM5n) count operation control <2> 8-bit timer ...
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-8. Format of 8-Bit Timer Mode Control Register 51 (TMC51) Address: FF43H After reset: 00H Symbol <7> 6 TMC51 TCE51 TMC516 TCE51 0 After clearing to 0, count operation disabled (counter ...