VSC8132QR Vitesse Semiconductor Corp., VSC8132QR Datasheet

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VSC8132QR

Manufacturer Part Number
VSC8132QR
Description
2.488 Gb/s 1:32 SONET/SDH Demux,3.3V
Manufacturer
Vitesse Semiconductor Corp.
Datasheet

Specifications of VSC8132QR

Case
QFP
G52250-0, Rev 3.1
12/7/00
Preliminary Data Sheet
VSC8132
Features
General Description
77.76Mb/s parallel data outputs D[31:0] for SONET/SDH applications. A 2.488GHz HSPECL input clock
(CLKI+) is used to time the incoming data and 3 TTL clock outputs, at frequencies of 77.76MHz, 51.84MHz,
and 38.88MHz, are generated for upstream devices (DATACLK78, CLK51, CLK38). Odd or even parity is per-
formed on the incoming high-speed data via the TTL Parity Select input (PARSEL), and a TTL Parity output
(PARITY) is provided to indicate parity of the input data. Frame Detect on the incoming data is controlled via
the Frame Detect Inhibit (OOFN) and Reset (RESET) TTL inputs. A frame detect monitors the incoming data
steam and screens for 2 bits in A1 byte out of the 8 bits and 2 bits of A2 byte out of the 8 bits. When a Frame
Detect occurs, a synchronization TTL output (SYNC) will be set. Alarm indicators are used to monitor the
activity of the clock and data with TTL compatible control inputs (ALMRESET) and outputs (DTALARM,
CKALARM).
mally-enhanced 128-pin, 14x20x2mm PQFP package.
VSC8132 Block DIagram
The VSC8132 demultiplexes a 2.488Gb/s HSPECL serial input datastream (DI+) to 32-bit wide, TTL
Only a single 3.3V power supply is required for device operation. The VSC8132 is packaged in a ther-
• 2.488Gb/s 1:32 Demultiplexer
• SONET STS-48/SDH STM-16
• HSPECL Differential Serial Data and Clock
• 32-Bit TTL Parallel Data Outputs with Odd/
• Frame Detect Synchronization
Inputs
Even Parity Check
ALMRESET
PARSEL
RESET
OOFN
CLKI+
CLKI–
DI+
DI–
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
VITESSE
SEMICONDUCTOR CORPORATION
Demux
1:32
Internet: www.vitesse.com
• 77.76, 51.84, and 38.88MHz TTL Clock Outputs
• Single 3.3V supply
• Loss of Clock Alarm
• Loss of Data Alarm
• 2.05W Max Power Dissipation
• 128-Pin PQFP Package
Generation
Framing
Alarms
Parity
Clock
and
2.488Gb/s 1:32 SONET/SDH Demux
DATA[3:0]
SYNC
PARITY
DATACLK78
CLK51
CLK38
DTALARM
CKALARM
Page 1

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VSC8132QR Summary of contents

Page 1

Preliminary Data Sheet VSC8132 Features • 2.488Gb/s 1:32 Demultiplexer • SONET STS-48/SDH STM-16 • HSPECL Differential Serial Data and Clock Inputs • 32-Bit TTL Parallel Data Outputs with Odd/ Even Parity Check • Frame Detect Synchronization General Description The VSC8132 ...

Page 2

SONET/SDH Demux Functional Description High-Speed Clock and Data Interface The incoming high-speed data and high-speed clock are received by high-speed inputs DI+ and CLKI+. The inputs are internally biased to accommodate AC-coupling. The data and clock inputs are ...

Page 3

Preliminary Data Sheet VSC8132 Low-Speed Data Interface The 77.76Mb/s parallel data outputs D[31:0] are clocked out of the VSC8132 on the falling clock edge of the 77.76MHz output clock (DATA78CLK). The data and clock are TTL levels. The MSB (D31) ...

Page 4

SONET/SDH Demux Decoupling of the power supplies is a critical element in maintaining the proper operation of the part recommended that the V power supply be decoupled using a 0.1 F and 0.01 F capacitor placed ...

Page 5

Preliminary Data Sheet VSC8132 (1) CLK78 (Out) SYNC PULSE (Out) OOFN (In) NOTE: (1) No missing clock pulse for CLK78 when VSC8132 is working as a dumb demux. Once frame occurs and OOFN is set HIGH, the no framing will ...

Page 6

SONET/SDH Demux DC Characteristics Table 2: DC Characteristics (Over recommended operating conditions) Parameters Description V Output HIGH Voltage (TTL) OHttl V Output LOW Voltage (TTL) OLttl V Input HIGH Voltage (TTL) IHttl V Input LOW Voltage (TTL) ILttl ...

Page 7

Preliminary Data Sheet VSC8132 Package Pin Descriptions VCC VEECTERM VCC 8 CLKI+ 9 CLKI VEE 12 DI+ 13 DI- 14 VEEDTERM 15 VEE 16 VEE ...

Page 8

SONET/SDH Demux Table 3: Pin Identifications Pin Name VCC VEECTERM VCC 9 CLKI+ 10 CLKI VEE 13 DI+ 14 DI- 15 VEEDTERM ...

Page 9

Preliminary Data Sheet VSC8132 Pin Name VCC 40 VEE 41 CKALARM 42 VEE 43 VCC 44 OOFN CLK51- 49 CLK51+ 50 VCC 51 VEE ...

Page 10

SONET/SDH Demux Pin Name 69 VEE 70 TH78DT25 71 TH78DT24 72 VCC 73 TH78DT23 74 TH78DT22 75 VCC 76 TH78DT21 77 TH78DT20 78 VEE 79 TH78DT19 80 TH78DT18 81 VCC 82 TH78DT17 83 TH78DT16 84 VCC 85 TH78DT15 ...

Page 11

Preliminary Data Sheet VSC8132 Pin Name 105 TH78DT3 106 TH78DT2 107 VCC 108 TH78DT1 109 TH78DT0 110 VEE 111 DATACLK78 112 SYNC 113 VCC 114 THPAR 115 THTRIST5 116 PARSEL 117 THTRIST1 118 VCC 119 VEE 120 THTRIST4 121 ALMRESET ...

Page 12

SONET/SDH Demux Package Information PIN 128 PIN 1 EXPOSED HEATSINK EXPOSED INTRUSION 0.127 MAX. 10 TYP TYP. Notes: 1) Drawing is not to scale 2) All dimensions Package represented is ...

Page 13

Preliminary Data Sheet VSC8132 Package Thermal Considerations The VSC8132 has been enhanced with a copper heat slug to provide a low thermal resistance path from the die to the exposed surface of the heat spreader. The thermal resistance is shown ...

Page 14

SONET/SDH Demux The results of this calculation are listed in Table 6. Table 6: Maximum Ambient Air Temperature without Heatsink Max Ambient Temperature Airflow None 100 lfpm 200 lfpm 400 lfpm 600 lfpm Note that ambient air temperature ...

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