VSC8140TW Vitesse Semiconductor Corp., VSC8140TW Datasheet
VSC8140TW
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VSC8140TW Summary of contents
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Data Sheet VSC8140 Features • 2.48832Gb/s 16-Bit Transceiver • Targeted for SONET OC-48 / SDH STM-16 Applications • LVPECL Low-Speed Interface • On-chip PLL-Based Clock Generator • High-Speed Clock Output With Power-Down Option • Supports Parity at the 16-Bit Parallel ...
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SONET/SDH Transceiver with Integrated Clock Generator Functional Description Transmitter Low-Speed Interface The Upstream Device should use the TXCLK16O as the timing source for its final output latch (see Figure 1). The Upstream Device should then generate a TXCLK16I ...
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Data Sheet VSC8140 PLL locked to reference clock. Minimum 5 CLK16 cycles RESET Holding RESET “low” for a minimum of 5 CLK16 cycles, then setting “high” enables FIFO operation. Holding RESET constantly “low” bypasses the FIFO for transparent mode operation. ...
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SONET/SDH Transceiver with Integrated Clock Generator Figure 5: AC Termination of Low-Speed LVPECL RXCLK16O, RXCLK16_32O, TXCLK16O Outputs VSC8140 Receiver Low-Speed Interface The demultiplexed serial stream is made available by a 16-bit single-ended LVPECL interface RXOUT[15:0] with accompanying differential ...
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Data Sheet VSC8140 Figure 7: Traditional DC Termination of Low-Speed LVPECL RXOUT[15:0] Outputs VSC8140 The RXOUT[15:0] output drivers can also be appropriately AC-coupled by a number of methods, how- ever, DC-coupling is preferred since there is no guarantee of transition ...
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SONET/SDH Transceiver with Integrated Clock Generator Figure 9: AC Termination of Low-Speed LVPECL RXOUT[15:0] Outputs V CC VSC8140 V EE Parity Systems employing internal parity are supported by the VSC8140. On the transmit side, a parity check is ...
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Data Sheet VSC8140 RXIN+ RXIN- RXCLKIN+ RXCLKIN- TXOUT+ TXOUT- TXCLKOUT+ TXCLKOUT- FACLOOP Facility Loopback The facility loopback function is controlled by the FACLOOP signal. When the FACLOOP signal is set high, the Facility Loopback mode is activated and the high-speed ...
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SONET/SDH Transceiver with Integrated Clock Generator RXIN+ RXIN- RXCLKIN+ RXCLKIN- EQULOOP TXOUT+ TXOUT- TXCLKOUT+ TXCLKOUT- RXIN+ RXIN- RXCLKIN+ RXCLKIN- TXOUT TXOUT- TXCLKOUT+ TXCLKOUT- FACLOOP EQULOOP Split Loopback Equipment and Facility Loopback modes can be enabled simultaneously. ...
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Data Sheet VSC8140 When LOOPTIM1 is asserted high, the RXCLK16_32O or RXCLK16O output can be tied to the LPTIM- CLK input. In order to meet jitter transfer, the RXCLK16_32O or RXCLOCK16O needs to be filtered PLL circuit ...
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SONET/SDH Transceiver with Integrated Clock Generator Transmitter High-Speed Data and Clock Outputs The high-speed data and clock output drivers (TXOUT and TXCLKOUT) consist of a differential pair designed to drive a 50 transmission line. The transmission line should ...
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Data Sheet VSC8140 Figure 15: Termination of Low-Speed LVPECL TXIN[15:0] Inputs VREFIN VREFOUT Low-Speed Inputs The incoming low-speed inputs are received by single-ended LVPECL inputs TXIN[15:0]. A reference voltage is ...
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SONET/SDH Transceiver with Integrated Clock Generator Figure 16: High-Speed Clock and High-Speed Data Inputs TERM TYP = 100nF IN C TYP = 100nF AC High-Speed Clock and High-Speed Data Inputs The incoming ...
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Data Sheet VSC8140 Supplies The VSC8140 is specified as a PECL device with a single positive 3.3V supply. Should the user desire to use the device in an ECL environment with a negative 3.3V supply, then V 3.3V. If used ...
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SONET/SDH Transceiver with Integrated Clock Generator AC Characteristics Figure 18: Transmitter Parallel Data Timing Waveforms TXCLK16I+ Parallel Data Clock Input TXIN[0:15]+, TXPRTYIN Parallel Data Inputs TXCLK16O+ Parallel Data Clock Output Figure 19: Transmitter Serial Data and Clock Phase ...
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Data Sheet VSC8140 Figure 21: Differential and Single-Ended Input / Output Voltage Measurement Differential swing Differential swing is specified as equal in magnitude to single-ended swing. Table 1: Transmitter AC Characteristics Parameters Description T TXCLK16I/TXCLK16O ...
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SONET/SDH Transceiver with Integrated Clock Generator RXCLK16O+ Parallel Data Clock Output RXOUT[0:15]+ Parallel Data Outputs RXCLK32O+ Parallel Data Clock Output Figure 23: Receiver Setup and Hold Time Requirements RXIN+ Differential Serial Data Input RXCLKIN+ Differential Clock Input Table ...
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Data Sheet VSC8140 DC Characteristics Table 3: DC Characteristics (Over recommended operating conditions) Description Parameters Output HIGH voltage (TXOUT, V OHHSO TXCLKOUT) Output LOW voltage (TXOUT, V OLHSO TXCLKOUT) Output differential voltage (TXCLKOUT) V ODHSO Output differential voltage (TXOUT) V ...
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SONET/SDH Transceiver with Integrated Clock Generator Figure 24: Parametric Measurement Information PECL Rise and Fall Time T r Absolute Maximum Ratings Power Supply Voltage (V )...........................................................................................................-0.5V to +3. Input Voltage (differential inputs).....................................................................................-0. Input ...
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Data Sheet VSC8140 Package Pin Descriptions Table 4: Package Pin Identification - 128 PQFP Pin # Name 1 OVERFLOW 2 VEET 3 VCCT 4 VEE 5 HSDREF 6 VEE 7 RXIN+ 8 RXIN- 9 VCC 10 VEE 11 VEE 12 ...
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SONET/SDH Transceiver with Integrated Clock Generator Table 4: Package Pin Identification - 128 PQFP Pin # Name 37 VEE 38 FACLOOP 39 LOOPTIM0 40 PARMODE 41 FIFORESET 42 LOOPTIM1 43 REF_FREQSEL 44 LPTIMCLK+ 45 LPTIMCLK- 46 VCC_ANA 47 ...
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Data Sheet VSC8140 Table 4: Package Pin Identification - 128 PQFP Pin # Name 72 VEE 73 TXIN8 74 TXIN7 75 TXIN6 76 TXIN5 77 TXIN4 78 VCC 79 TXIN3 80 TXIN2 81 VEE 82 TXIN1 83 TXIN0 84 VCC ...
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SONET/SDH Transceiver with Integrated Clock Generator Table 4: Package Pin Identification - 128 PQFP Pin # Name 109 RXOUT14 110 VEE 111 RXOUT15 112 RXPARITYOUT 113 VCC 114 RXCLK16O- 115 RXCLK16O+ 116 VEE 117 VCC 118 RXCLK16_32O- 119 ...
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Data Sheet VSC8140 Package Information PIN 128 PIN 1 EXPOSED INTRUSION 0.127 MAX. EXPOSED HEATSINK PIN 38 10 TYP TYP. Notes: 1) Drawing is not to scale 2) All dimensions Package represented ...
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SONET/SDH Transceiver with Integrated Clock Generator Package Pin Descriptions Table 5: Package Pin Identification - 208 BGA Pin # Name B17 OVERFLOW B16 VEET B15 VCCT C14 VEE D13 HSDREF A16 VEE B14 RXIN+ B13 RXIN- A14 VCC ...
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Data Sheet VSC8140 Table 5: Package Pin Identification - 208 BGA Pin # Name B3 VCC D4 VCC C3 VEE C1 FACLOOP F4 LOOPTIM0 F3 PARMODE D1 FIFORESET E1 LOOPTIM1 G4 REF_FREQSEL G3 VEE F2 LPTIMCLK+ G2 LPTIMCLK- F1 VCC_ANA ...
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SONET/SDH Transceiver with Integrated Clock Generator Table 5: Package Pin Identification - 208 BGA Pin # Name T3 VCC P5 TXIN13 R5 TXIN12 T4 TXIN11 P6 TXIN10 T5 TXIN9 R6 VEE U5 TXIN8 R7 TXIN7 T6 TXIN6 U6 ...
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Data Sheet VSC8140 Table 5: Package Pin Identification - 208 BGA Pin # Name U14 RXOUT8 U15 RXOUT9 R13 VCC N16 VCC P17 RXOUT10 L14 RXOUT11 L15 RXOUT12 M16 VCC L16 RXOUT13 M17 RXOUT14 K14 VEE K15 RXOUT15 K16 RXPARITYOUT ...
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SONET/SDH Transceiver with Integrated Clock Generator Table 5: Package Pin Identification - 208 BGA Pin # Name C16 NC C15 NC C13 NC C12 NC C10 NC C9 ...
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Data Sheet VSC8140 Table 5: Package Pin Identification - 208 BGA Pin # Name M15 NC M14 NC N17 NC N15 NC N14 P16 NC P15 NC P14 NC P13 NC ...
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SONET/SDH Transceiver with Integrated Clock Generator Table 5: Package Pin Identification - 208 BGA Pin # Name NOTES: (1) There has been a change in the naming of the pins of the ...
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Data Sheet VSC8140 Package Information 11 CORNER 45 DEGREE 0.5MM CHAMFER (4 PLCS) DETAIL A SIDE VIEW P DETAIL A NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. "e" REPRESENTS THE BASIC SOLDER BALL GRID PITCH. 3. "M" REPRESENTS THE ...
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SONET/SDH Transceiver with Integrated Clock Generator Package Thermal Considerations This package has been enhanced with a copper heat slug to provide a low thermal resistance path from the die to the exposed surface of the heat spreader. The ...
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Data Sheet VSC8140 The results of this calculation are listed below: Table 8: Maximum Ambient Air Temperature without Heatsink Airflow None 100 lfpm 200 lfpm 400 lfpm Note that ambient air temperature varies throughout the system based on the positioning ...
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SONET/SDH Transceiver with Integrated Clock Generator Manual Soldering When manually soldering the device to the printed circuit board, contact time should be limited to 10 sec- o onds 240 C. Layout Considerations Refer to Application ...