X24F032 Intersil Corporation, X24F032 Datasheet

no-image

X24F032

Manufacturer Part Number
X24F032
Description
Manufacturer
Intersil Corporation
Datasheet
64K/32K/16K
FUNCTIONAL DIAGRAM
SerialFlash Memory and Block Lock
Protection are trademarks of Xicor, Inc.
FEATURES
6686-3.8 8/29/96 T3/C0/D0 SH
Xicor, 1995, 1996 Patents Pending
1.8V to 3.6V or 5V “Univolt” Read and
Program Power Supply Versions
Low Power CMOS
—Active Read Current Less Than 1mA
—Active Program Current Less Than 3mA
—Standby Current Less Than 1 A
Internally Organized 8K/4K/2K x 8
New Programmable Block Lock Protection
—Software Write Protection
—Programmable hardware Write Protect
Block Lock (0, 1/4, 1/2, or all of the Flash
Memory array)
2 Wire Serial Interface
Bidirectional Data Transfer Protocol
32 Byte Sector Programming
Self Timed Program Cycle
High Reliability
—Endurance: 100,000 cycles per byte
—Data Retention: 100 Years
Available Packages
—8-Lead PDIP
—8-Lead SOIC (JEDEC)
—14-Lead TSSOP (X24F032/016)
—20-Lead TSSOP (X24F064)
—Typical Programming Time of 5ms
Per Sector
AN76 • AN78 • AN81 • AN87
A V A I L A B L E
A
PPLICATION
SerialFlash
N
OTE
S
S
S
SDA
SCL
TM
0
2
1
/S
/S
PP
/S
0
2
1
Memory with Block Lock
X24F064/032/016
AND CONTROL
COMMAND
DECODE
LOGIC
CONTROL LOGIC
PROGRAMMING
1
DESCRIPTION
The X24F064/032/016 is a CMOS SerialFlash
Memory Family, internally organized 8K/4K/2K x 8.
The family features a serial interface and software
protocol allowing operation on a simple two wire bus.
Device select inputs (S
devices to share a common two wire bus.
A Program Protect Register accessed at the highest
address location, provides three new programming
protection features: Software Programming Protection,
Block Lock Protection, and Hardware Programming
Protection. The Software Programming Protection
feature prevents any nonvolatile writes to the device
until the WEL bit in the program protect register is set.
The Block Lock
individually protect four blocks of the array by program-
ming two bits in the programming protect register. The
Programmable Hardware Program Protect feature
allows the user to install each device with PP tied to
V
then enable the hardware programming protection by
programming a PPEN bit in the program protect
register. After this, selected blocks of the array,
including the program protect register itself, are
permanently protected from being programmed.
CC
, program the entire memory array in place, and
PROGRAM
REGISTER
PROTECT
DECODE
LOGIC
X
TM
TM
Protection feature allows the user to
Protection
SECTOR DECODE LOGIC
0
Characteristics subject to change without notice
, S
8K/4K/2K x 8 Bit
32
DATA REGISTER
HIGH VOLTAGE
1
SECTORED
CONTROL
, S
MEMORY
ARRAY
2
) allow up to eight
6686 ILL F01.5
8

Related parts for X24F032

X24F032 Summary of contents

Page 1

... Retention: 100 Years • Available Packages —8-Lead PDIP —8-Lead SOIC (JEDEC) —14-Lead TSSOP (X24F032/016) —20-Lead TSSOP (X24F064) FUNCTIONAL DIAGRAM SerialFlash Memory and Block Lock Protection are trademarks of Xicor, Inc. Xicor, 1995, 1996 Patents Pending 6686-3 ...

Page 2

... DIP & SOIC SCL SDA 14-LEAD TSSOP X24F032 8-LEAD DIP & SOIC SCL SDA 20-LEAD TSSOP ...

Page 3

X24F064/032/016 DEVICE OPERATION The X24F064/032/016 supports a bidirectional bus ori- ented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the re- ceiving device as the receiver. The device controlling the transfer is ...

Page 4

X24F064/032/016 Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the device into the standby power mode ...

Page 5

... Following a start condition the master must output the address of the slave it is accessing (see Figure 4). The next two bits are the device select bits. A system could have up to eight X24F032/016’s on the bus four 24F064’s on the bus. The device addresses are defined by the state of the S ...

Page 6

X24F064/032/016 Flow 1. ACK Polling Sequence PROGRAM OPERATION COMPLETED ENTER ACK POLLING ISSUE START ISSUE SLAVE ADDRESS AND R ACK NO RETURNED? YES NEXT NO OPERATION A WRITE? YES ISSUE SECTOR ADDRESS PROCEED After the receipt of each ...

Page 7

X24F064/032/016 Current Address Read Internally, the X24F064/032/016 contains an ad- dress counter that maintains the address of the last byte read, incremented by one byte. Therefore, if the last read was from address n, the next read opera- tion accesses ...

Page 8

X24F064/032/016 Sequential Read Sequential reads can be initiated as either a current address read or random access read. The first byte is transmitted as with the other modes, however, the master now responds with an acknowledge, indicating it requires additional ...

Page 9

... X24F064/032/016 PROGRAM PROTECT REGISTER The Program Protect Register (PPR) is accessed at the highest address of each device: X24F064 = 1FFF X24F032 = 0FFF X24F016 = 07FF Figure 10. Program Protect Register PPEN 0 0 BL1 BL0 PPR.1 = WEL – Write Enable Latch (Volatile Write enable latch reset, programming disabled 1 = Write enable latch set, programming enabled If WEL = 0 then “ ...

Page 10

X24F064/032/016 Block Lock Bits The Block Lock Bits BL0 and BL1 determine which blocks of the memory are write-protected: Table 1. Block Lock Bits BL1 BL0 Array Locked 0 0 None 0 1 Upper 1 Upper 1/2 1 ...

Page 11

X24F064/032/016 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias X24F064/032/016 ...................... – +135 C Storage Temperature........................ – +150 C Voltage on any Pin with Respect to V .................................... –1V to +7V SS D.C. Output Current..............................................5mA Lead Temperature (Soldering, ...

Page 12

X24F064/032/016 A.C. CONDITIONS OF TEST Input Pulse Levels V CC Input Rise and Fall Times Input and Output Timing Levels A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read & Write Cycle Limits Symbol f SCL Clock ...

Page 13

X24F064/032/016 Bus Timing SCL t SU:STA SDA IN SDA OUT Program Cycle Limits Symbol Parameter (6) t Program Cycle Time PR The program cycle time is the time from a valid stop condition of a write sequence to the end ...

Page 14

X24F064/032/016 PACKAGING INFORMATION 8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL 0.015 (0.38) MAX. TYP. 0.010 (0.25) NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH ...

Page 15

X24F064/032/016 PACKAGING INFORMATION 8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S PIN 1 INDEX 0.010 (0.25) 0.020 (0.50) 0 – 8 0.016 (0.410) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 0.150 (3.80) 0.158 (4.00) PIN ...

Page 16

X24F064/032/016 PACKAGING INFORMATION See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 14-LEAD PLASTIC, TSSOP PACKAGE TYPE V .025 (.65) BSC .169 (4.3) .177 (4.5) .193 (4.9) .200 (5.1) .0075 (.19) .002 (.05) .0118 (.30) .006 (.15) ...

Page 17

X24F064/032/016 PACKAGING INFORMATION 20-LEAD PLASTIC, TSSOP PACKAGE TYPE V 0 – 8 See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) .025 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .252 (6.4) .300 (6.6) .047 (1.20) ...

Page 18

... P = 8-Lead Plastic DIP S = 8-Lead SOIC (JEDEC 20-Lead TSSOP 8-Lead Plastic DIP Blank = 8-Lead SOIC (JEDEC 14/20-Lead TSSOP X Blank = 1.8V to 3.6V + 1.8V to 3.6V, – + 4.5V to 5.5V + 4.5V to 5.5V, – + X24F032 X24F016 P = 8-Lead Plastic DIP S = 8-Lead SOIC (JEDEC 14-Lead TSSOP ...

Related keywords