IDT74FCT388915T100J

Manufacturer Part NumberIDT74FCT388915T100J
Description3.3V low skew PLL-based CMOS clock driver (with 3-state)
ManufacturerIntegrated Device Technology, Inc.
IDT74FCT388915T100J datasheet
 


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3.3V LOW SKEW PLL-BASED CLOCK DRIVER
Integrated Device Technology, Inc.
FEATURES:
• 0.5 MICRON CMOS Technology
• Input frequency range: 10MHz – f2Q Max. spec
(FREQ_SEL = HIGH)
• Max. output frequency: 150MHz
• Pin and function compatible with FCT88915T, MC88915T
• 5 non-inverting outputs, one inverting output, one 2x
output, one 2 output; all outputs are TTL-compatible
• 3-State outputs
• Output skew < 350ps (max.)
• Duty cycle distortion < 500ps (max.)
• Part-to-part skew: 1ns (from t
PD
• 32/–16mA drive at CMOS output voltage levels
• V
= 3.3V
0.3V
CC
• Inputs can be driven by 3.3V or 5V components
• Available in 28 pin PLCC, LCC and SSOP packages
DESCRIPTION:
The IDT54/74FCT388915T uses phase-lock loop technol-
ogy to lock the frequency and phase of outputs to the input
reference clock. It provides low skew clock distribution for
high performance PCs and workstations. One of the outputs
FUNCTIONAL BLOCK DIAGRAM
FEEDBACK
Phase/Freq.
SYNC (0)
0
M
Detector
u
x
1
SYNC (1)
REF_SEL
0
PLL_EN
FREQ_SEL
OE/RST
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
1995 Integrated Device Technology, Inc.
3.3V LOW SKEW PLL-BASED
CMOS CLOCK DRIVER
(WITH 3-STATE)
is fed back to the PLL at the FEEDBACK input resulting in
essentially zero delay across the device. The PLL consists of
the phase/frequency detector, charge pump, loop filter and
VCO. The VCO is designed for a 2Q operating frequency
range of 40MHz to f2Q Max.
The IDT54/74FCT388915T provides 8 outputs with 350ps
skew. The
runs at twice the Q frequency and Q/2 runs at half the Q
frequency.
The FREQ_SEL control provides an additional 2 option in
the output path. PLL _EN allows bypassing of the PLL, which
is useful in static test modes. When PLL_EN is low, SYNC
max. spec)
input may be used as a test clock. In this test mode, the input
frequency is not limited to the specified range and the polarity
of outputs is complementary to that in normal operation
(PLL_EN = 1). The LOCK output attains logic HIGH when the
PLL is in steady-state phase and frequency lock. When OE/
is low, all the outputs are put in high impedance state and
RST
registers at Q,
The IDT54/74FCT388915T requires one external loop filter
component as recommended in Figure 3.
Charge Pump
1
Mux
( 1)
1
M
u
Divide
( 2)
x
0
-By-2
9.8
9.8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT388915T
70/100/133/150
PRELIMINARY
output is inverted from the Q outputs. The 2Q
Q5
and Q/2 outputs are reset.
Q
LOCK
Voltage
Controlled
Oscilator
LF
2Q
Q0
D
D
Q
Q
CP
CP
Q
Q
R
Q1
D
Q
CP
R
Q2
D
Q
CP
R
Q3
D
Q
CP
R
Q4
D
Q
CP
R
Q5
D
Q
CP
R
Q/2
D
Q
CP
R
AUGUST 1995
3052 drw 01
DSC-4243/1
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IDT74FCT388915T100J Summary of contents