MC68HC68T1P Motorola, MC68HC68T1P Datasheet

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MC68HC68T1P

Manufacturer Part Number
MC68HC68T1P
Description
Real-time clock plus RAM
Manufacturer
Motorola
Datasheet

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Part Number
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Quantity
Price
Part Number:
MC68HC68T1P
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Real-Time Clock plus RAM with
Serial Interface
CMOS
clock/calendar, a 32 x 8 static RAM, and a synchronous, serial, three–wire
interface for communication with a microcontroller or processor. Operating in a
burst mode, successive Clock/RAM locations can be read or written using only
a single starting address. An on–chip oscillator allows acceptance of a
selectable crystal frequency or the device can be programmed to accept a
50/60 Hz line input frequency.
capability for sensing power–up/power–down conditions, a capability useful for
battery–backup systems. The device has an interrupt output capable of
signaling a microcontroller or processor of an alarm, periodic interrupt, or power
sense condition. An alarm can be set for comparison with the seconds, minutes,
and hours registers. This alarm can be used in conjunction with the power
supply enable (PSE) output to initiate a system power–up sequence if the V SYS
pin is powered to the proper level.
interrupt control register. This applies a reset to the CPU via the CPUR pin, sets
the clock out (CLKOUT) and PSE pins low, and disables the serial interface.
This condition is held until a rising edge is sensed on the V SYS input pin,
signaling system power coming on, or by activation of a previously enabled
interrupt if the V SYS pin is powered up.
processor to toggle the slave select (SS) pin of the MC68HC68T1 periodically
without performing a serial transfer. If this condition is not met, the CPUR line
resets the CPU.
MICROWIRE is a trademark of National Semiconductor Inc.
REV 2
2/96
MOTOROLA
The MC68HC68T1 HCMOS Clock/RAM peripheral contains a real–time
The LINE and system voltage (V SYS ) pins give the MC68HC68T1 the
A software power–down sequence can be initiated by setting a bit in the
A watchdog circuit can be enabled that requires the microcontroller or
Motorola, Inc. 1996
Full Clock Features — Seconds, Minutes, Hours (AM/PM), Day–of–Week,
Date, Month, Year (0 – 99), Auto Leap Year
32–Byte General Purpose RAM
Direct Interface to Motorola SPI and National MICROWIRE
Ports
Minimum Timekeeping Voltage: 2.2 V
Burst Mode for Reading/Writing Successive Addresses in Clock/RAM
Selectable Crystal or 50/60 Hz Line Input Frequency
Clock Registers Utilize BCD Data
Buffered Clock Output for Driving CPU Clock, Timer, Colon, or LCD
Backplane
Power–On Reset with First Time–Up Bit
Freeze Circuit Eliminates Software Overhead During a Clock Read
Three Independent Interrupt Modes — Alarm, Periodic, or Power–Down
CPU Reset Output — Provides Orderly Power–Up/Power–Down
Watchdog Circuit
Pin–for–Pin Replacement for CDP68HC68T1
Chip Complexity: 8500 FETs or 2125 Equivalent Gates
Also See Application Notes ANE425 “Use of the MC68HC68T1 RTC with
M6805 Microprocessor”, AN457 “Providing a Real–Time Clock for the
MC68302”, and AN1065 “Use of the MC68HC68T1 Real–Time Clock with
Multiple Time Bases”
t
Serial Data
MC68HC68T1
16
16
MC68HC68T1P
MC68HC68T1DW SOG Package
ORDERING INFORMATION
CLKOUT
1
CPUR
MOSI
MISO
1
SCK
V SS
INT
SS
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
Order this document
SOG PACKAGE
Plastic DIP
by MC68HC68T1/D
PLASTIC DIP
16
15
14
13
12
11
10
DW SUFFIX
CASE 751G
9
CASE 648
P SUFFIX
MC68HC68T1
V DD
XTAL out
XTAL in
V BATT
V SYS
LINE
POR
PSE
1

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MC68HC68T1P Summary of contents

Page 1

... MC68302”, and AN1065 “Use of the MC68HC68T1 Real–Time Clock with Multiple Time Bases” MICROWIRE is a trademark of National Semiconductor Inc. REV 2 2/96 MOTOROLA Motorola, Inc. 1996 MC68HC68T1 ORDERING INFORMATION MC68HC68T1P MC68HC68T1DW SOG Package PIN ASSIGNMENT CLKOUT 1 CPUR 2 INT 3 SCK 4 MOSI 5 ...

Page 2

... BLOCK DIAGRAM SECOND MINUTE CLOCK SELECT CLOCK 8–BIT DATA BUS INTERRUPT COMPARATOR SECOND MINUTE LATCH LATCH STATUS REGISTER RAM SERIAL INTERFACE PIN PIN FREEZE CIRCUIT AM/PM CALENDAR AND HOUR LOGIC LOGIC DAY/ HOUR MONTH DATE HOUR YEAR LATCH MOTOROLA ...

Page 3

... Maximum RMS Operating Supply Current External Frequency Source Driving XTAL in , XTAL out Open I batt Maximum RMS Standby Current Crystal Operation * Timekeeping function only, no read/write accesses. Data in the registers and RAM retained. MOTOROLA Value Unit – 0 7.0 V – 0 0.5 V – 0 0.5 ...

Page 4

... Figure V DD Guaranteed No. V Limit Unit 1, 2 3.0 200 ns 4.5 100 6.0 100 1, 2 3.0 200 ns 4.5 100 6.0 100 1, 2 3.0 250 ns 4.5 125 6.0 125 1, 2 3.0 200 ns 4.5 100 6.0 100 1, 2 3.0 200 ns 4.5 200 6.0 200 1, 2 3.0 400 ns 4.5 200 6.0 200 3.0 — ns 4.5 100 6.0 100 3.0 — s 4.5 2 6.0 2 MOTOROLA ...

Page 5

... NOTE: Measurement points are and V IH unless otherwise noted on the AC Electrical Characteristics table. TEST POINT DEVICE OUTPUT UNDER TEST Includes all probe and fixture capacitance. Figure 3. Test Circuit MOTOROLA t rec Figure 1. Write Cycle t rec ...

Page 6

... Power control is composed of two operations, power– sense and power–down/power–up. Two pins are involved in power sensing, the LINE input pin and the INT output pin. Two additional pins, PSE and V SYS , are utilized during power–down/power–up operation. MOTOROLA ...

Page 7

... Power–Down Power–down is a processor–directed operation. The power–down bit is set in the interrupt control register to initi- MOTOROLA ate power–down operation. During power–down, the power supply enable (PSE) output, normally high, is driven low. The CLKOUT pin is driven low. The CPUR output, connected to the processor reset input pin, is also driven low ...

Page 8

... NOT USED $2A NOT USED $2B NOT USED $2C NOT USED $2D NOT USED $2E NOT USED $2F $30 $31 $32 HEXADECIMAL SECONDS $A0 MINUTES $A1 HOURS $A2 $A3 $A4 MONTH $A5 YEAR $A6 NOT USED $A7 $A8 $A9 HOURS ALARM $AA NOT USED $AB NOT USED $AC NOT USED $AD NOT USED $AE NOT USED $AF NOT USED $B0 $B1 $B2 MOTOROLA ...

Page 9

... N/A $A9 X N/A $AA $B0 N/A 7 $00 T0 $1F $80 T0 $9F D7 NOTE Don’t Care for Write for Read N/A = Not Applicable MOTOROLA READ/WRITE REGISTERS DB0 TENS 0 – 5 UNITS 0 – 9 TENS 0 – 5 UNITS 0 – 9 PM/AM UNITS 0 – TENS 0 – UNITS 1 – 7 TENS 0 – 3 UNITS 0 – ...

Page 10

... BCD Data Range BCD Date* Example 00 – – – 92 (AM – B2 (PM) 00 – – – – – – – – 12 (AM – 32 (PM) 00 – XTAL Min Max — 7.8 ms 15.6 ms 31.3 ms MOTOROLA ...

Page 11

... NOTE Hz p–p sine–wave voltage is an acceptable signal to present at the LINE input pin. Figure 8. Power Sensing Functional Diagram MSB 1 INTERRUPT CONTROL REGISTER SERIAL INTERFACE REAL–TIME CLOCK MC68HC68T1 Figure 9. Software Power–Down Functional Diagram MOTOROLA XTAL in XTAL out INT V DD LINE REAL–TIME CLOCK MC68HC68T1 MSB LSB 1 (STATUS REGISTER) ...

Page 12

... SIGNAL PSE ALARM CIRCUIT CPUR PERIODIC INTERRUPT CLKOUT SIGNAL POWER SENSE CIRCUIT SERIAL INTERFACE REAL–TIME CLOCK MC68HC68T1 V DD BACKUP PSE SWITCH POWER SWITCH/ MODE CONTROL CPUR CLKOUT V SYS SERIAL INTERFACE REAL–TIME CLOCK MC68HC68T1 MISO MOSI V BATT MISO MOSI MOTOROLA ...

Page 13

... SCK, with the most sig- nificant bit (MSB) first. In Motorola’s microcomputers with SPI, the state of the CPOL bit determines which is the active edge of SCK. If SCK is high when SS goes high, the state of the CPOL bit is high. ...

Page 14

... Figure 12.) XTAL in 5 – XTAL out C2 10 – REAL–TIME CLOCK MC68HC68T1 Figure 12. Recommended Oscillator Circuit (C1, C2 Values Depend Upon the Crystal Frequency) LSB CLK CLK CLK OUT OUT OUT resistor that is MOTOROLA ...

Page 15

... When power sense is activated, a logic low must be written to this location followed by a high to re–enable power sense. MOTOROLA W for 32 kHz Alarm The output of the alarm comparator is enabled when this bit is set high ...

Page 16

... Any transfer of data requires the address of the byte to specify a write or read Clock or RAM location, followed by one or more bytes of data. Data is transferred out of MISO for a read operation and into MOSI for a write operation (see Figures 14 and 15). MISO High–Z High–Z Next Data Bit Shifted Out* MOTOROLA ...

Page 17

... SCK* Î Î MSB Î Î MOSI D7 D6 Î Î Î Î Î Î MSB Î Î MISO D7 D6 Î Î * SCK can be either polarity. Figure 15. Read/Write Data Transfer Waveforms MOTOROLA SHIFT SHIFT MSB ...

Page 18

... DATA BYTE n Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î DATA BYTE n MOTOROLA ...

Page 19

... BRIDGE/ LOW VOLTAGE REGULATOR AC LINE NOTE 1 NOTES: 1. Clock circuit driven by line input frequency. 2. Power–on reset circuit included to detect power failure MC68HC11 MCU is used, delete the capacitor at the RESET pin. MOTOROLA APPLICATION CIRCUITS 100 k NOTE POR 0 INT ...

Page 20

... Clock Out pins to be held low and disconnects the serial interface. 6. When power returns and V SYS rises above V BATT + 0.7 V, power–up is initiated. The CPU reset is released and serial communication is established IRQ MC68HC05C4 1 RESET 39 OSC 1 28 PORT (e.g., PC0) 31 MISO 32 MOSI 33 SCK MOTOROLA ...

Page 21

... NOTE 1 NOTES: 1. See Figure 12 for 32.768 kHz operation. This configuration, where the MC68HC68T1 supplies the MCU clock, usually requires MHz crystal MC68HC11 MCU is used, delete the capacitor at the RESET pin. Figure 20. Rechargeable Battery–Backup System MOTOROLA NC 100 k m 0.1 F ...

Page 22

... Voltage at pin must not exceed absolute maximum V in specification. MC68HC68T1 SYS 9 PSE 2 CPUR 1 CLKOUT 3 INT SPI Figure 21. Automotive System ENABLED POWER PORT MC68HC05C4 1 RESET NOTE 2 39 OSC 1 2 IRQ SPI 27 PORT MOTOROLA ...

Page 23

... V NON–RECHARGEABLE BATTERY – 0 0 Actual values may vary, depending on recommendations of crystal manufacturer. Figure 22. Non–Rechargeable Battery–Backup System MOTOROLA LIMIT D BLOCK W 100 BATT SYS 11 LINE 6 10 POR MISO 5 W MOSI 215 XTAL out ...

Page 24

... V DD and V SYS are removed. The CLKOUT, CPUR, and PSE are not active immediately when V DD and V SYS is applied. The problem is related to the power up procedure (battery–backup mode or single–supply mode). See these sections in the data sheet for more information. MOTOROLA ...

Page 25

... PL 0.25 (0.010 SOG (SMALL OUTLINE GULL–WING) PACKAGE - - - 0.25 (0.010 MOTOROLA PACKAGE DIMENSIONS P SUFFIX PLASTIC DIP (DUAL IN–LINE PACKAGE) CASE 648– SEATING -T- PLANE SUFFIX CASE 751G–01 0.25 (0.010 ...

Page 26

... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “ ...

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