STA013 STMicroelectronics, STA013 Datasheet
STA013
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STA013 Summary of contents
Page 1
... Input Interface. The decoded signal is a stereo, mono, or dual channel digital output that can be sent directly to a D/A converter, by the PCM Out- put Interface. This interface is software program- mable to adapt the STA013 digital output to the most common DACs architectures used on the market. The functional STA013 chip partitioning is de- scribed in Fig ...
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... STA013 - STA013B - STA013T Figure 1. Block Diagram: MPEG 2.5 Layer III Decoder Hardware Partitioning. RESET 26 5 SDI SERIAL 6 SCKR BUFFER INPUT INTERFACE 7 BIT_EN 8 SRC_INT OUT_CLK/DATA_REQ THERMAL DATA Symbol R Thermal resistance Junction to Ambient th j-amb ABSOLUTE MAXIMUM RATINGS Symbol V Power Supply DD V Voltage on Input pins ...
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... A1 = SDI B2 = SCKR D4 = BIT_EN D1 = SRC_INT E2 = SDO F2 = SCKT H1 = LRCKT H3 = OCLK F3 = VSS_2 E4 = VDD_2 G4 = VSS_3 G5 = VDD_3 F5 = PVDD G6 = PVSS D99AU1085 LFBGA64 STA013 - STA013B - STA013T 33 N.C. 32 SCL 31 SDA 30 VSS_1 29 VDD_1 28 N.C. 27 OUT_CLK/DATA_REC 26 VSS_5 25 RESET 24 SCANEN 23 N.C. D99AU1019 G7 = FILT G8 = XTO ...
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... Note: SRC_INT signal is used by STA013 internal software in Broadcast Mode only; in Multimedia mode SRC_INT must be connected functional mode TESTEN must be connected to VDD, SCANEN to ground. DD 4/38 Pin Name Type VDD_1 Supply Voltage VSS_1 Ground 2 SDA I Serial Data + Acknowledge ...
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... DD Leakage < Test Condition I = Xma ol Test Condition V = 0V; pin numbers and 26 Test Condition Sampling_freq 24 kHz Sampling_freq 32 kHz Sampling_freq 48 kHz STA013 - STA013B - STA013T = 0 to 70° unless otherwise Value 2.4 to 3.6V Min. Typ. Max. Unit - - 2000 V Min. Typ. ...
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... Figure 4. Test Load Circuit I OL OUTPUT FUNCTIONAL DESCRIPTION 2.1 - Clock Signal The STA013 input clock is derivated from an ex- ternal source or from a industry standard crystal oscillator, generating input frequencies of 10, 14.31818 or 14.7456 MHz. Symbol Parameter V Low Level Input Voltage IL V High Level Input Voltage ...
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... The operation is done by STA013 line shold be embedded software and it is transparent to the N user. The STA013 PLL can drive directly most of the commercial DACs families, providing an over sampling clock, OCLK, obtained dividing the VCO frequency with a software programmable dividers. STA013 - STA013B - STA013T ...
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... Data can be output either with the most significant bit first (MS) or least significant bit first (LS), selected by writing into a flag of the PCMCONF register. Figure 8 gives a description of the several STA013 PCM Output Formats. The sample rates set decoded by STA013 is de- scribed in Table 1. 16 SCLK Cycles 16 SCLK Cycles L M ...
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... This control is done by a specific buffer manage- ment, controlled by STA013 embedded software. The data source, by monitoring the DATA_REQ line, send to STA013 the input data, when the signal is high (default configuration). The communication is stopped DATA_REQ line is low ...
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... SCL line is low. 3.2 - DEVICE ADDRESSING To start communication between the master and the STA013, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8 bits (MSB first) corresponding to the device select address and read or write mode ...
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... This mode can be initiated with either a current address read or a random address read. How- ever in this case the master does acknowledge the data byte output and the STA013 continues to output the next byte in sequence. To terminate the streams of bytes the master does not acknowledge the last received byte, but ...
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... STA013 - STA013B - STA013T REGISTERS (continued) HEX_COD DEC_COD $43 67 HEAD_H[23:16] $44 68 HEAD_M[15:8] $45 69 HEAD_L[7:0] $46 70 DLA $47 71 DLB $48 72 DRA $49 73 DRB $50 80 MFSDF_441 $51 81 PLLFRAC_441_L $52 82 PLLFRAC_441_H $54 84 PCM DIVIDER $55 85 PCMCONF $56 86 PCMCROSS $59 89 ANC_DATA_1 [7:0] $5A 90 ANC_DATA_2 [15:8] $5B 91 ANC_DATA_3 [23:16] ...
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... The M and N registers are used to configure the STA013 PLL by DSP embedded software and N registers are R/W type but they are completely controlled, on STA013, by DSP soft- ware. REQ_POL Address: 0x0C Type: R/W Software Reset: 0x01 Hardware Reset: 0x00 STA013 - STA013B - STA013T b5 ...
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... Software Reset: 0x00 Hardware Reset: 0x00 MSB don’t care normal operation reset When this register is written, a soft reset occours. The STA013 core command register and the in- terrupt register are cleared. The decoder goes in LSB to idle mode ...
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... X = don’t care normal operation write into I The INTERRUPT is used to give STA013 the command to write into the I2C/Ancillary Data Buffer (Registers: 0x59 ... 0x5D). Every time the Master has to extract the new buffer content (5 bytes) it writes into this register, setting non-zero value ...
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... STA013 - STA013B - STA013T ANCCOUNT_L Address: 0x41 Type: RO Software Reset: 0x00 Hardware Reset: 0x00 MSB AC7 AC6 AC5 AC4 AC3 ANCCOUNT_H Address: 0x42 Type: RO Software Reset: 0x00 Hardware Reset: 0x00 ANCCOUNT_H MSB AC15 AC14 AC13 AC12 AC11 AC10 AC9 ...
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... Indicates the type of de-emphasis that shall be used. 160 forbidden emphasis ’00’ ’01’ ’10’ MPEG2.5 ’11’ 11. reserved STA013 - STA013B - STA013T mode specified stereo joint stereo (intensity_stereo and/or ms_stereo) dual_channel single_channel (mono) emphasis specified none 50/15 microseconds reserved CCITT J,17 17/38 ...
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... STA013 - STA013B - STA013T DLA Address: 0x46 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB DLA7 DLA6 DLA5 DLA4 DLA register is used to attenuate the level of audio output at the Left Channel using the butter- fly shown in Fig. 12. When the register is set to Figure 12 ...
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... The VCO output frequency, when decoding 44.1KHz bitstream, is divided by (MFSDF_441 +1) PLLFRAC_441_L Address: 0x51 Type: R/W LSB Software Reset: 0x00 Hardware Reset: 0x00 MSB b7 PF7 STA013 - STA013B - STA013T LSB b0 Description DRA0 OUTPUT ATTENUATION 0 NO ATTENUATION 1 -1dB 0 -2dB : : 0 -96dB (0xFF), the ...
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... STA013 - STA013B - STA013T PLLFRAC_441_H Address: 0x52 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB PF15 PF14 PF13 PF12 PF11 PF10 PF9 The registers are considered logically concate- nated and contain the fractional values for the PLL, for 44.1KHz reference frequency. ...
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... INV_LRCLK=1 ’01’: 18 bit mode (32 slots transmitted) ’10’: 20 bit mode (32 slots transmitted) ’11’: 24 bit mode (32 slots transmitted) The PCM samples precision in STA013 can 18-20-24 bits. When STA013 operates in 16 (18-20-24) bits mode, the number of bits transmitted during a LRCLT period is 32 (64). ...
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... Right and Left channels are toggled The value is changed by the internal STA013 Core, to set the clocks frequencies, according to the incoming bitstream. This value can be even set by the user to select the PCM interface con- figuration. The VCO output frequency is divided by (X+1). ...
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... Kbit/sec. SOFTVERSION LSB Address: 0x71 Type: RO FC2 FC1 FC0 MSB b7 LSB SV7 SV6 After the STA013 boot, this register contains the version code of the embedded software. FC8 STA013 - STA013B - STA013T AB5 AB4 AB3 AB2 b6 ...
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... Setting this register to 1, STA013 leaves the idle state, starting the decoding process. The Microcontroller is allowed to set the RUN flag, once all the control registers have been in- itialized. TREBLE_FREQUENCY_LOW Address: 0x77 Type: RW Software Reset: 0x00 Hardware Reset: 0x00 ...
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... Signed number (2 complement) This register is used to select the enhancement or attenuation STA013 has to perform on Treble Frequency range at the digital signal. A decrement (increment decimal unit corre- sponds to a step of attenuation (enhancement) of 1.5dB. LSB The allowed Attenuation/Enhancement range [-18dB, +18dB] ...
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... Signed number (2 complement) This register is used to select the enhancement or attenuation STA013 has to perform on Bass Frequency range at the digital signal. A decrement (increment decimal unit corre- sponds to a step of attenuation (enhancement) of 1.5dB. LSB The allowed Attenuation/Enhancement range [-18dB, +18dB] ...
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... QUANTISATION DECODING & DESCALING SIDE INFORMATION DECODING pling frequencies. The time duration of the Layer III frames is shown in Tab 2. 44 STA013 - STA013B - STA013T audio, the full signal is ATTENUATION -1.5dB step 0dB -1.5dB -3dB -4.5dB -15dB -16.5dB -18dB INVERSE IMDCT FILTERBANK ...
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... ANC_DATA_4 0x5D ANC_DATA_5 Since the content of Ancillary Data into an MPEG Frame STA013 can extract is max. 56 bytes, a 5.3. I/O CELL DESCRIPTION 1) CMOS Tristate Output Pad Buffer, 4mA, with Slew Rate Control / Pin numbers 9, 10, 11, 20 CMOS Bidir Pad Buffer, 4mA, with Slew Rate Control / Pin numbers 3, 12 ...
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... OCLK) b) OCLK in input. OCLK (INPUT) SDO SCKT LRCLK Thi min = 3ns Tlo min = 3ns Toclk min = 25ns tsdo = 5.5 + pad_timing (Cload_SDO) ns tsckt = 6 + pad_timing (Cload_SCKT) ns tlrckt = 5.5 + pad_timing (Cload_LRCKT) ns STA013 - STA013B - STA013T t sdo t sckt t lrclk Pad-timing versus load Load (pF 100 Cload_XXX is the load the XXX output ...
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... STA013 - STA013B - STA013T 5.4.2. Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 0 BIT_EN SCKR SDI 5.4.2. Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 1 BIT_EN SCKR SDI tsdi_setup_min = 2ns tsdi_hold_min = 3ns tsckr_min_hi = 10ns tsckr_min_low = 10ns tsckr_min_lperiod = 50ns t_biten (min) = 2ns 5.4.3. SRC_INT This is an asynchronous input used in "broadcast’ mode. ...
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... MODE see {TAB 5 to TAB12} INPUT SERIAL CLOCK POLARITY CONFIGURATION DATA REQUEST PIN ENABLE DATA REQUEST POLARITY CONFIGURATION RUN STA013 - STA013B - STA013T D98AU974 THE OVERALL SETTING STEPS ARE INCLUDED IN THE STA013 CONFIGURATION FILE AND CAN BE DOWNLOADED IN ONE STEP. STM PROVIDES A SPECIFIC ...
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... STA013 - STA013B - STA013T Table 5: PLL Configuration Sequence For 10MHz Input Clock 256 Oversapling Clock REGISTER NAME ADDRESS 6 reserved 11 reserved 97 MFSDF (x) 80 MFSDF-441 101 PLLFRAC-H 82 PLLFRAC-441-H 100 PLLFRAC-L 81 PLLFRAC-441-L 5 PLLCTRL Table 6: PLL Configuration Sequence For 10MHz Input Clock 384 Oversapling Rathio REGISTER ...
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... Oversapling Rathio REGISTER NAME ADDRESS 6 reserved 11 reserved 97 MFSDF (x) 80 MFSDF-441 101 PLLFRAC-H 82 PLLFRAC-441-H 100 PLLFRAC-L 81 PLLFRAC-441-L 5 PLLCTRL STA013 - STA013B - STA013T Table 11: PLL Configuration Sequence For 14.7456MHz Input Clock 384 Oversapling Rathio REGISTER VALUE ADDRESS 101 157 82 211 100 ...
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... Note:1 STA013 is a device based on an integrated DSP core. Some of the I2C registers default values are loaded after an internal DSP boot operation. The bootstrap time is 60 micro second. Only after this time lenght, the data in the register can be considered stable. Note 2: ...
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... DIM. MIN. TYP. MAX. MIN. A 2.65 a1 0.1 0.3 0.004 b 0.35 0.49 0.014 b1 0.23 0.32 0.009 C 0 (typ.) D 17.7 18.1 0.697 E 10 10.65 0.394 e 1.27 e3 16.51 F 7.4 7.6 0.291 L 0.4 1.27 0.016 S 8 (max.) inch MECHANICAL DATA TYP. MAX. 0.104 0.012 0.019 0.013 0.020 0.713 0.419 0.050 0.65 0.299 0.050 STA013 - STA013B - STA013T OUTLINE AND SO28 35/38 ...
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... STA013 - STA013B - STA013T mm DIM. MIN. TYP. MAX. A 1.60 A1 0.05 0.15 0.002 A2 1.35 1.40 1.45 0.053 B 0.30 0.37 0.45 0.012 C 0.09 0.20 0.004 D 11.80 12.00 12.20 0.464 D1 9.80 10.00 10.20 0.386 D3 8.00 E 11.80 12.00 12.20 0.464 E1 9.80 10.00 10.20 0.386 E3 8.00 e 0.80 L 0.45 0.60 0.75 0.018 L1 1.00 k 0˚(min.), 3.5˚(typ.), 7˚(max 36/38 inch MIN. TYP. MAX. 0.063 0.006 0.055 0.057 0.015 0.018 0.008 0.472 ...
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... BALL 1 IDENTIFICATION (64 PLACES) e inch TYP. MAX. 0.067 0.016 0.018 0.043 0.20 0.315 0.220 0.031 Body 1.7mm 0.315 0.220 0.047 0. STA013 - STA013B - STA013T OUTLINE AND MECHANICAL DATA LFBGA64 D LFBGA64M E 37/38 ...
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... STA013 - STA013B - STA013T Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...