MPC932 Freescale Semiconductor, Inc, MPC932 Datasheet

no-image

MPC932

Manufacturer Part Number
MPC932
Description
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Advance Information
Low Voltage PLL Clock Driver
targetted for zero delay applications. The device provides 6 outputs for
driving clock loads plus a single dedicated PLL feedback clock output.
The dedicated feedback output gives the user six choices of input
multiplcation factors: x1, x1.25, x1.5, x2, x2.5 and x3.
are synchronized to the internal clock such that upon assertion the shut
down signals will hold the clocks LOW without generating a runt pulse on
the outputs. The shut down pins provide a means of powering down
certain portions of a system or a means of disabling outputs when the full
compliment are not required for a specific design. The shut down pins will
disable the outputs when driven LOW. A common shut down pin is
provided to disable all of the outputs (except the feedback output) with a
single control signal.
factors: x1, x1.25, x1.5, x2, x2.5 and x3. In the x1.25 and x2.5 modes, the QFB output will not provide a 50% duty cycle. The
phase detector of the MPC932 only monitors rising edges of its feedback signals, thus for this function a 50% duty cycle is not
required. As the QFB signal can also be used to drive other clocks in a system it is important the user understand that the duty
cycle will not be 50%. In the x1 and x1.5 modes the QFB output will produce 50% duty cycle signals.
a high impedance state to allow for back driving the outputs during system test. In addition the PLL_EN pin allows the user to
bypass the PLL and drive the outputs directly through the Ref_CLK input. Note the Ref_CLK signal will be routed through the
dividers so that it will take several transitions on the Ref_CLK input to create a transition on the outputs.
compatible and the outputs produce rail–to–rail 3.3V swings. For series terminated applications each output can drive two series
terminated 50Ω transmission lines. For parallel terminated lines the device can drive terminations of 50Ω into VCC/2. The device
is packaged in a 32–lead TQFP package to provide the optimum combination of performance, board density and cost.
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
11/96
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1996
6 Low Skew Clock Outputs
1 Dedicated PLL Feedback Output
Individual Output Enable Control
Fully Integrated PLL
Output Frequency Up TO 120MHz
32–lead TQFP Packaging
3.3V VCC
The MPC932 is a 3.3V compatible PLL based clock driver device
The MPC932 provides individual output enable control. The enables
Two feedback select pins are provided to select the multiplication factor of the PLL. The MPC932 provides six multiplication
The MPC932 provides two pins for use in system test and debug operations. The MR/OE input will force all of the outputs into
The MPC932 is fully 3.3V compatible and requires no external loop filter components. All of the inputs are LVCMOS/LVTTL
100ps Cycle–Cycle Jitter
1
REV 0
PLL CLOCK DRIVER
LOW VOLTAGE
MPC932
TQFP PACKAGE
CASE 873A-02
FA SUFFIX

Related parts for MPC932

MPC932 Summary of contents

Page 1

... In the x1 and x1.5 modes the QFB output will produce 50% duty cycle signals. The MPC932 provides two pins for use in system test and debug operations. The MR/OE input will force all of the outputs into a high impedance state to allow for back driving the outputs during system test. In addition the PLL_EN pin allows the user to bypass the PLL and drive the outputs directly through the Ref_CLK input ...

Page 2

... MPC932 Pinout: 32-Lead TQFP Package (Top View VCCO GNDO MPC932 29 SD2 30 SD0:1 31 MODE 32 VCCA PLL_EN REF_CLK PLL 200–480MHz FB_In MODE MR/OE COM_SD MOTOROLA GND_QFB 15 QFB 14 VCCO_QFB 13 FB_In 12 SD3 11 SD4 MODE 10 SD5 ...

Page 3

... Maximum PLL Supply Current The MPC932 outputs can drive series or parallel terminated 50Ω (or 50Ω /2) transmission lines on the incident edge (see Applications Info section). 3. Inputs have pull–up/pull–down resistors which affect input current. TIMING SOLUTIONS BR1333 — ...

Page 4

... MPC932 MPC932 AC CHARACTERISTICS ( 3.3V 5%) Symbol Characteristic f ref Input Reference Frequency t os Output-to-Output Skew f VCO VCO Lock Range f max Maximum Output Frequency t pd Reference to EXT_FB Average Delay TCLK t pw Output Duty Cycle (Note 4 Output Rise/Fall Time (Note 4.) ...

Page 5

... V CC /2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC932 clock driver. For the series terminated case however there current draw, thus the outputs can drive multiple series terminated lines. ...

Page 6

... Figure 6 should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC932 OUTPUT BUFFER 7Ω Figure 6. Optimized Dual Line Termination ...

Page 7

... N É É É É É É SECTION AE– MPC932 DETAIL Y NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS – ...

Page 8

... JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 8 MPC932/D TIMING SOLUTIONS BR1333 — REV 5 ...

Related keywords