UPD78F9177A Renesas Electronics Corporation., UPD78F9177A Datasheet
UPD78F9177A
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UPD78F9177A Summary of contents
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User’s Manual µ PD789167, 789177, 789167Y, 789177Y Subseries 8-Bit Single-Chip Microcontrollers µ PD789166 µ PD789167 µ PD789176 µ PD789177 µ PD78F9177 µ PD78F9177A µ PD789166(A) µ PD789167(A) µ PD789176(A) µ PD789177(A) µ PD78F9177A(A) Document No. U14186EJ6V0UD00 (6th edition) Date Published ...
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User’s Manual U14186EJ6V0UD ...
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VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care to prevent chattering noise ...
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These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. 2 Purchase of NEC Electronics I C components conveys a license ...
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Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and ...
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Readers This manual is intended for user engineers who wish to understand the functions of µ the develop its application systems and programs. Target products: • • • • µ The the target devices in this manual. The generic terms ...
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Organization The parts: this manual and the instruction manual (common to the 78K/0S Series). µ PD789167, 789177, 789167Y, • Pin functions • Internal block functions • Interrupts • Other internal peripheral functions • Electrical specifications How to Read This ...
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To learn the details of the instruction functions of the 78K/0S Series → Refer to 78K/0S Series Instructions User's Manual (U11047E) separately ◊ To know the electrical specifications of the 789177Y Subseries → Refer to CHAPTER 23 ELECTRICAL SPECIFICATIONS ...
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Differences between PD789167, 789177, 789167Y, and 789177Y Subseries µ The PD789167, 789177, 789167Y, and 789177Y Subseries differ in their package type, A/D converter resolution, and serial interface configuration. Item Package IC2 pin A/D converter resolution Serial interface 3-wire serial ...
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Conventions Data significance: Active low representation: Note: Caution: Remark: Numerical representation: Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices µ PD789167, 789177, 789167Y, ...
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Documents Related to Development Tools (Hardware) (User’s Manuals) IE-78K0S-NS In-Circuit Emulator IE-78K0S-NS-A In-Circuit Emulator IE-789177-NS-EM1 Emulation Board Documents Related to Flash Memory Writing PG-FP3 Flash Memory Programmer User’s Manual PG-FP4 Flash Memory Programmer User’s Manual Other Related Documents SEMICONDUCTORS SELECTION ...
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CHAPTER 1 GENERAL ( PD789167 AND 789177 SUBSERIES)....................................................19 1.1 Expanded-Specification Products and Conventional Products ...........................................19 1.2 Features ......................................................................................................................................20 1.3 Applications................................................................................................................................20 1.4 Ordering Information .................................................................................................................21 1.5 Quality Grades............................................................................................................................22 1.6 Pin Configuration (Top View)....................................................................................................23 1.7 78K/0S Series Lineup.................................................................................................................26 1.8 Block Diagram ...
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V (flash memory version only) ................................................................................................... 51 PP 3.2.16 IC0 (mask ROM version only)....................................................................................................... 51 3.2.17 IC3 ............................................................................................................................................... 51 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins.........................................52 CHAPTER 4 PIN FUNCTIONS ( 4.1 Pin Function List ........................................................................................................................54 ...
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Special-function register (SFR) addressing .................................................................................. 81 5.4.4 Register addressing...................................................................................................................... 82 5.4.5 Register indirect addressing ......................................................................................................... 83 5.4.6 Based addressing ......................................................................................................................... 84 5.4.7 Stack addressing .......................................................................................................................... 84 CHAPTER 6 PORT FUNCTIONS ...........................................................................................................85 6.1 Port Functions............................................................................................................................85 6.2 Port Configuration .....................................................................................................................87 6.2.1 ...
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Buzzer output operation.............................................................................................................. 128 8.5 Notes on 16-Bit Timer 90 .........................................................................................................129 8.5.1 Notes on using 16-bit timer 90 .................................................................................................... 129 8.5.2 Restrictions on rewriting of 16-bit compare register 90............................................................... 131 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS .............................................................133 ...
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A/D Converter Control Registers ................................................................................180 13.4 10-Bit A/D Converter Operation..............................................................................................182 13.4.1 Basic operation of 10-bit A/D converter ...................................................................................... 182 13.4.2 Input voltage and conversion result ............................................................................................ 183 13.4.3 Operation mode of 10-bit A/D converter ..................................................................................... 185 13.5 Cautions ...
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CHAPTER 17 INTERRUPT FUNCTIONS ............................................................................................293 17.1 Interrupt Function Types.........................................................................................................293 17.2 Interrupt Sources and Configuration .....................................................................................293 17.3 Interrupt Function Control Registers.....................................................................................296 17.4 Interrupt Processing Operation ..............................................................................................301 17.4.1 Non-maskable interrupt request acknowledgment operation ...................................................... 301 17.4.2 Maskable interrupt request acknowledgment operation.............................................................. 303 ...
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CHAPTER 25 ELECTRICAL SPECIFICATIONS ( CHAPTER 26 CHARACTERISTICS CURVES ( CHAPTER 27 ELECTRICAL SPECIFICATIONS ( 78F9177AY(A)) ...............................................................................................................387 CHAPTER 28 ELECTRICAL SPECIFICATIONS ( CHAPTER 29 CHARACTERISTICS CURVES ( CHAPTER 30 ELECTRICAL SPECIFICATIONS ( CHAPTER 31 PACKAGE DRAWINGS.................................................................................................439 CHAPTER 32 RECOMMENDED SOLDERING ...
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CHAPTER 1 GENERAL ( 1.1 Expanded-Specification Products and Conventional Products The expanded-specification products and conventional products refer to the following products. Expanded-specification product... Products with a rank • Mask ROM versions for which orders were received after December 1, 2001 ...
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CHAPTER 1 GENERAL ( 1.2 Features • ROM and RAM capacity Product Name µ PD789166, 789176, 789166(A), 789176(A), 789166(A1), 789176(A1), 789166(A2), 789176(A2) µ PD789167, 789177, 789167(A), 789177(A), 789167(A1), 789177(A1), 789167(A2), 789177(A2) µ PD78F9177, 78F9177A, 78F9177A(A), 78F9177A(A1) • Minimum instruction execution ...
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CHAPTER 1 GENERAL ( 1.4 Ordering Information Part Number µ PD789166GB-×××-8ES µ PD789166GA-×××-9EU µ PD789167GB-×××-8ES µ PD789167GA-×××-9EU µ PD789176GB-×××-8ES µ PD789176GA-×××-9EU µ PD789177GB-×××-8ES µ PD789177GA-×××-9EU µ PD789166GB-×××-8ES-A µ PD789166GA-×××-9EU-A µ PD789167GB-×××-8ES-A µ PD789167GA-×××-9EU-A µ PD789176GB-×××-8ES-A µ PD789176GA-×××-9EU-A µ PD789177GB-×××-8ES-A µ ...
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CHAPTER 1 GENERAL ( 1.5 Quality Grades Part Number µ PD789166GB-×××-8ES µ PD789166GA-×××-9EU µ PD789167GB-×××-8ES µ PD789167GA-×××-9EU µ PD789176GB-×××-8ES µ PD789176GA-×××-9EU µ PD789177GB-×××-8ES µ PD789177GA-×××-9EU µ PD789166GB-×××-8ES-A µ PD789166GA-×××-9EU-A µ PD789167GB-×××-8ES-A µ PD789167GA-×××-9EU-A µ PD789176GB-×××-8ES-A µ PD789176GA-×××-9EU-A µ PD789177GB-×××-8ES-A µ ...
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CHAPTER 1 GENERAL ( 1.6 Pin Configuration (Top View) 44-pin plastic LQFP (10 × 10) • µ PD789166GB-×××-8ES µ PD789167GB-×××-8ES µ PD789176GB-×××-8ES µ PD789177GB-×××-8ES µ PD789166GB-×××-8ES-A µ PD789167GB-×××-8ES-A µ PD789176GB-×××-8ES-A µ PD789177GB-×××-8ES-A P60/ANI0 P61/ANI1 P62/ANI2 P63/ANI3 P64/ANI4 P65/ANI5 P66/ANI6 P67/ANI7 ...
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CHAPTER 1 GENERAL ( • 48-pin plastic TQFP (fine pitch) (7 × 7) µ PD789166GA-×××-9EU µ PD789167GA-×××-9EU µ PD789176GA-×××-9EU µ PD789177GA-×××-9EU P60/ANI0 P61/ANI1 P62/ANI2 P63/ANI3 P64/ANI4 P65/ANI5 P66/ANI6 P67/ANI7 AV SS P10 P11 IC3 Cautions 1. Connect the IC0 (internally ...
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CHAPTER 1 GENERAL ( ANI0 to ANI7: Analog input ASCK20: Asynchronous serial input AV : Analog power supply Analog reference voltage REF AV : Analog ground SS BZO90: Buzzer output CPT90: Capture trigger input IC0, IC3: Internally ...
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CHAPTER 1 GENERAL ( 1.7 78K/0S Series Lineup The 78K/0S Series products are shown below. The subseries names are indicated in frames. Y Subseries products support SMB. Small-scale package, general-purpose applications µ 44-pin PD789046 µ 42-/44-pin PD789026 µ 30-pin PD789088 ...
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CHAPTER 1 GENERAL ( The major functional differences between the subseries are listed below. Series for General-purpose applications and LCD drive Function ROM Capacity Subseries Name µ Small-scale PD789046 16 KB package, µ PD789026 general- ...
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CHAPTER 1 GENERAL ( Series for ASSP Function ROM Capacity Subseries Name µ USB PD789800 8 KB µ Inverter PD789842 control µ On-chip bus PD789852 controller 32 KB µ PD789850A ...
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CHAPTER 1 GENERAL ( 1.8 Block Diagram TI80/SS20/P25 8-bit timer/ event counter 80 TO80/P26 TI81/INTP0/CPT90/P30 8-bit timer/ event counter 81 TO81/INTP1/P31 TO82/INTP3/BZO90/P33 8-bit timer 82 CPT90/INTP0/TI81/P30 TO90/INTP2/P32 16-bit timer 90 BZO90/INTP3/TO82/P33 Watch timer Watchdog timer SCK20/ASCK20/P20 SO20/T D20/P21 X SIO20 ...
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CHAPTER 1 GENERAL ( 1.9 Outline of Functions Part Number Item Internal memory ROM High-speed RAM Minimum instruction execution time General-purpose registers Instruction set Multiplier I/O ports A/D converter Serial interface Timers Timer output Buzzer output Vectored interrupt Maskable sources ...
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CHAPTER 1 GENERAL ( The timers are outlined below. Operating Interval timer mode External event counter Function Timer output PWM output Square-wave output Buzzer output Capture Interrupt sources Notes 1. The watch timer can perform both watch timer and interval ...
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CHAPTER 1 GENERAL ( 1.10 Differences Between Standard Quality Grade Products and (A) Products, (A1) Products, and (A2) Products Standard quality grade products, (A) products, (A1) products, and (A2) products indicate the following products respectively. Standard quality grade products... µ ...
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CHAPTER 2 GENERAL ( 2.1 Expanded-Specification Products and Conventional Products The expanded-specification products and conventional products refer to the following products. Expanded-specification product... Products with a rank • Mask ROM versions for which orders were received after December 1, 2001. ...
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CHAPTER 2 GENERAL ( 2.2 Features • ROM and RAM capacity Product Name µ PD789166Y, 789176Y, 789166Y(A), 789176Y(A) µ PD789167Y, 789177Y, 789167Y(A), 789177Y(A) µ PD78F9177Y, 78F9177AY, 78F9177AY(A) • Minimum instruction execution time changeable from high-speed (0.2 Note operation ) to ...
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CHAPTER 2 GENERAL ( 2.4 Ordering Information Part Number µ PD789166YGB-×××-8ES µ PD789166YGA-×××-9EU µ PD789167YGB-×××-8ES µ PD789167YGA-×××-9EU µ PD789176YGB-×××-8ES µ PD789176YGA-×××-9EU µ PD789177YGB-×××-8ES µ PD789177YGA-×××-9EU µ PD789166YGB-×××-8ES-A µ PD789166YGA-×××-9EU-A µ PD789167YGB-×××-8ES-A µ PD789167YGA-×××-9EU-A µ PD789176YGB-×××-8ES-A µ PD789176YGA-×××-9EU-A µ PD789177YGB-×××-8ES-A µ ...
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CHAPTER 2 GENERAL ( 2.5 Quality Grades Part Number µ PD789166YGB-×××-8ES µ PD789166YGA-×××-9EU µ PD789167YGB-×××-8ES µ PD789167YGA-×××-9EU µ PD789176YGB-×××-8ES µ PD789176YGA-×××-9EU µ PD789177YGB-×××-8ES µ PD789177YGA-×××-9EU µ PD789166YGB-×××-8ES-A µ PD789166YGA-×××-9EU-A µ PD789167YGB-×××-8ES-A µ PD789167YGA-×××-9EU-A µ PD789176YGB-×××-8ES-A µ PD789176YGA-×××-9EU-A µ PD789177YGB-×××-8ES-A µ ...
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CHAPTER 2 GENERAL ( 2.6 Pin Configuration (Top View) 44-pin plastic LQFP (10 × 10) • µ PD789166YGB-×××-8ES µ PD789167YGB-×××-8ES µ PD789176YGB -×××-8ES µ PD789177YGB -×××-8ES P60/ANI0 P61/ANI1 P62/ANI2 P63/ANI3 P64/ANI4 P65/ANI5 P66/ANI6 P67/ANI7 AV SS P10 10 P11 11 ...
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CHAPTER 2 GENERAL ( 48-pin plastic TQFP (fine pitch) (7 × 7) • µ PD789166YGA-×××-9EU µ PD789167YGA-×××-9EU µ PD789176YGA-×××-9EU µ PD789177YGA-×××-9EU µ PD789166YGA-×××-9EU-A µ PD789167YGA-×××-9EU-A µ PD789176YGA-×××-9EU-A µ PD789177YGA-×××-9EU-A P60/ANI0 P61/ANI1 P62/ANI2 P63/ANI3 P64/ANI4 P65/ANI5 P66/ANI6 P67/ANI7 AV SS P10 ...
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CHAPTER 2 GENERAL ( ANI0 to ANI7: Analog input ASCK20: Asynchronous serial input AV : Analog power supply Analog reference voltage REF AV : Analog ground SS BZO90: Buzzer output CPT90: Capture trigger input IC0, IC2: Internally ...
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CHAPTER 2 GENERAL ( 2.7 78K/0S Series Lineup The 78K/0S Series products are shown below. The subseries names are indicated in frames. Y Subseries products support SMB. Small-scale package, general-purpose applications µ 44-pin PD789046 µ 42-/44-pin PD789026 µ 30-pin PD789088 ...
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CHAPTER 2 GENERAL ( The functions of the Y Subseries are listed below. Function ROM Capacity Subseries Name Small-scale 3-wire/UART µ PD789177Y package, µ PD789167Y general- purpose application + A/D converter PD789167Y AND ...
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CHAPTER 2 GENERAL ( 2.8 Block Diagram TI80/SS20/P25 8-bit timer/ event counter 80 TO80/P26 TI81/INTP0/CPT90/P30 8-bit timer/ TO81/INTP1/P31 event counter 81 TO82/INTP3/BZO90/P33 8-bit timer 82 CPT90/INTP0/TI81/P30 TO90/INTP2/P32 16-bit timer 90 BZO90/INTP3/TO82/P33 Watch timer Watchdog timer SCK20/ASCK20/P20 SO20/T D20/P21 X SIO20 ...
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CHAPTER 2 GENERAL ( 2.9 Outline of Function Part Number Item Internal memory ROM High-speed RAM Minimum instruction execution time General-purpose registers Instruction set Multiplier I/O ports A/D converter Serial interface Timers Timer output Buzzer output Vectored interrupt Maskable sources ...
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CHAPTER 2 GENERAL ( The timers are outlined below. Operating Interval timer mode External event counter Function Timer output PWM output Square-wave output Buzzer output Capture Interrupt sources Notes 1. The watch timer can perform both watch timer and interval ...
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CHAPTER 2 GENERAL ( 2.10 Differences Between Standard Quality Grade Products and (A) Products Standard quality grade products and (A) products indicate the following products. Standard quality grade products... µ (A) products... PD789166Y(A), 789167Y(A), 789176Y(A), 789177Y(A), 78F9177AY(A) Table 2-2 shows ...
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CHAPTER 3 PIN FUNCTIONS ( 3.1 Pin Function List (1) Port pins Pin Name I/O P00 to P05 I/O Port 0 6-bit I/O port I/O mode can be specified in 1-bit units. When used as an input port, an on-chip ...
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CHAPTER 3 PIN FUNCTIONS ( (2) Non-port pins Pin Name I/O INTP0 Input External interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified INTP1 INTP2 INTP3 SI20 Input Serial ...
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CHAPTER 3 PIN FUNCTIONS ( 3.2 Description of Pin Functions 3.2.1 P00 to P05 (Port 0) These pins constitute a 6-bit I/O port and can be set to input or output port mode in 1-bit units by using port mode ...
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CHAPTER 3 PIN FUNCTIONS ( (g) ASCK20 This is the serial clock input pin of the asynchronous serial interface. Caution When using P20 to P26 as serial interface pins, the I/O mode and output latch must be set according to ...
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CHAPTER 3 PIN FUNCTIONS ( 3.2.6 P60 to P67 (Port 6) These pins constitute an 8-bit input-only port. They can function as A/D converter input pins as well as a general- purpose input port. (1) Port mode In port mode, ...
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CHAPTER 3 PIN FUNCTIONS ( 3.2.15 V (flash memory version only) PP High voltage application pin for flash memory programming mode setting and program write/verify. Connect this pin in either of the following ways. • Independently connect ...
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CHAPTER 3 PIN FUNCTIONS ( 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the I/O circuit configuration of each ...
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CHAPTER 3 PIN FUNCTIONS ( Figure 3-1. Pin I/O Circuits Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 5-H V DD0 Pull-up P-ch enable V DD0 Data P-ch Output N-ch disable V SS0 Input enable Type 8-C V DD0 ...
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CHAPTER 4 PIN FUNCTIONS ( 4.1 Pin Function List (1) Port pins Pin Name I/O P00 to P05 I/O Port 0 6-bit I/O port I/O mode can be specified in 1-bit units. When used as an input port, an on-chip ...
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CHAPTER 4 PIN FUNCTIONS ( (2) Non-port pins Pin Name I/O INTP0 Input External interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified INTP1 INTP2 INTP3 SI20 Input Serial ...
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CHAPTER 4 PIN FUNCTIONS ( 4.2 Description of Pin Functions 4.2.1 P00 to P05 (Port 0) These pins constitute a 6-bit I/O port and can be set to input or output port mode in 1-bit units by using port mode ...
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CHAPTER 4 PIN FUNCTIONS ( (g) ASCK20 This is the serial clock input pin of the asynchronous serial interface. (h) SCL0 This is the clock I/O pin of SMB0. (i) SDA0 This is the data I/O pin of SMB0. Caution ...
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CHAPTER 4 PIN FUNCTIONS ( 4.2.6 P60 to P67 (Port 6) These pins constitute an 8-bit input-only port. They can function as A/D converter input pins as well as a general- purpose input port. (1) Port mode In port mode, ...
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CHAPTER 4 PIN FUNCTIONS ( 4.2.15 V (flash memory version only) PP High voltage apply pin for flash memory programming mode setting and program write/verify. Connect this pin in either of the following ways. • Independently connect ...
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CHAPTER 4 PIN FUNCTIONS ( 4.3 Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 4-1. For the I/O circuit configuration of each ...
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CHAPTER 4 PIN FUNCTIONS ( Figure 4-1. Pin I/O Circuits Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 5-H V DD0 Pull-up P-ch enable V DD0 Data P-ch Output N-ch disable V SS0 Input enable Type 8-C V DD0 ...
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CHAPTER 5 CPU ARCHITECTURE 5.1 Memory Space Products in the PD789167, 789177, 789167Y, and 789177Y Subseries can each access memory space. Figures 5-1 through 5-3 show the memory maps. Figure 5-1. Memory Map ( PD789166, ...
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Figure 5-2. Memory Map ( PD789167, PD789177, PD789167Y, and PD789177Y Special-function registers Internal high-speed RAM ...
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Figure 5-3. Memory Map ( PD78F9177, PD78F9177Y, PD78F9177A, and PD78F9177AY Special-function registers Internal high-speed RAM ...
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Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The PD789167, 789177, 789167Y, and 789177Y Subseries provide the following internal ROM (or flash memory) ...
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Internal data memory (internal high-speed RAM) space The PD789167, 789177, 789167Y, and 789177Y Subseries provide a 512-byte internal high-speed RAM. The internal high-speed RAM can also be used as a stack memory. 5.1.3 Special-function register (SFR) area Special-function registers ...
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CHAPTER 5 CPU ARCHITECTURE Figure 5-5. Data Memory Addressing Modes ( PD789167, PD789177, PD789167Y, and PD789177Y Special-function registers (SFR) 256 8 bits ...
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Figure 5-6. Data Memory Addressing Modes ( PD78F9177, PD78F9177Y, PD78F9177A, and PD78F9177AY Special-function registers (SFR) 256 8 bits ...
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Processor Registers The PD789167, 789177, 789167Y, and 789177Y Subseries provide the following on-chip processor registers. 5.2.1 Control registers The control registers have special functions to control the program sequence statuses and stack memory. The control registers include a program ...
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Interrupt enable flag (IE) This flag controls interrupt request acknowledgment operations of the CPU. When the interrupt disabled (DI) status is set. All interrupt requests except non-maskable interrupt are disabled. When the interrupt ...
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Stack pointer (SP) This is a 16-bit register used to hold the start address of the memory stack area. Only the internal high- speed RAM area can be set as the stack area. Figure 5-9. Stack Pointer Configuration 15 ...
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General-purpose registers The general-purpose registers consist of eight 8-bit registers ( and H). In addition that each register can be used as an 8-bit register, two 8-bit registers in pairs can be used ...
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Special-function registers (SFR) Unlike a general-purpose register, each special-function register has a special function. They are allocated to the 256-byte area FF00H to FFFFH. The special-function registers can be manipulated, like the general-purpose registers, with operation, transfer, and bit ...
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Table 5-3. Special-Function Registers (1/2) Address Special-Function Register (SFR) Name FF00H Port 0 FF01H Port 1 FF02H Port 2 FF03H Port 3 FF05H Port 5 FF06H Port 6 FF10H 16-bit multiplication result storage register 0 FF11H FF14H A/D conversion result ...
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Table 5-3. Special-Function Registers (2/2) Address Special-Function Register (SFR) Name FF54H 8-bit compare register 81 FF55H 8-bit timer counter 81 FF57H 8-bit timer mode control register 81 FF58H 8-bit compare register 82 FF59H 8-bit timer counter 82 FF5BH 8-bit timer ...
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Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time ...
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Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed. CALL !addr16 and BR !addr16 instructions ...
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Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by the immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched. ...
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Operand Address Addressing The following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 5.4.1 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand ...
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Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space where this addressing is applied to is the 256-byte space FE20H to FF1FH. ...
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Special-function register (SFR) addressing [Function] The memory-mapped special-function registers (SFR) are addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte space FF00H to FFFFH. However, the SFRs mapped at FF00H to FF1FH ...
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Register addressing [Function] The general-purpose registers are accessed as operands. The general-purpose register to be accessed is specified by the register specification code and functional name in the instruction code. Register addressing is carried out when an instruction with ...
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Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register pair specify code in the instruction code. This addressing ...
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Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as ...
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Port Functions µ The PD789167, 789177, 789167Y, and 789177Y Subseries are provided with the ports shown in Figure 6-1. These ports are used to enable several types of control. Table 6-1 lists the functions of each port. These ports, ...
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Pin Name I/O P00 to P05 I/O Port 0 6-bit I/O port I/O mode can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register ...
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Port Configuration Ports have the following hardware configuration. Parameter Control registers Port mode registers (PMm Pull-up resistor option register 0 (PU0) Pull-up resistor option registers B2, B3 (PUB2, PUB3) Ports Total: 31 (CMOS ...
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Port 1 This is a 2-bit I/O port with output latches. Port 1 can be set to input or output mode in 1-bit units by using the port mode register 1 (PM1). When the P10 and P11 pins are ...
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Port 2 This is a 7-bit I/O port with output latches. Port 2 can be set to input or output mode in 1-bit units by using port mode register 2 (PM2). For the P20 to P22, P25, and P26 ...
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WR PUB2 PUB21 RD WR PORT Output latch (P21 PM21 Alternate function PUB2: Pull-up resistor option register B2 PM: Port mode register RD: Port 2 read signal WR: Port 2 write signal 90 CHAPTER 6 PORT FUNCTIONS Figure ...
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Figure 6-6. Block Diagram of P22 and P25 WR PUB2 PUB22, PUB25 Alternate function RD WR PORT Output latch (P22, P25 PM22, PM25 PUB2: Pull-up resistor option register B2 PM: Port mode register RD: Port 2 read signal ...
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Figure 6-7. Block Diagram of P23 and P24 Alternate Note function RD WR PORT Output latch (P23, P24 PM23, PM24 Alternate Note function PM: Port mode register RD: Port 2 read signal WR: Port 2 write signal Note ...
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WR PUB2 PUB26 RD WR PORT Output latch (P26 PM26 Alternate function PUB2: Pull-up resistor option register B2 PM: Port mode register RD: Port 2 read signal WR: Port 2 write signal CHAPTER 6 PORT FUNCTIONS Figure 6-8. ...
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Port 3 This is a 4-bit I/O port with output latches. Port 3 can be set to input or output mode in 1-bit units by using port mode register 3 (PM3). For the P30 to P33 pins, on-chip pull-up ...
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Figure 6-10. Block Diagram of P31 and P32 WR PUB3 PUB31, PUB32 Alternate function RD WR PORT Output latch (P31, P32 PM31, PM32 Alternate function PUB3: Pull-up resistor option register B3 PM: Port mode register RD: Port 3 ...
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WR PUB3 PUB33 Alternate function RD WR PORT Output latch (P33 PM33 Alternate function Alternate function PUB3: Pull-up resistor option register B3 PM: Port mode register RD: Port 3 read signal WR: Port 3 write signal 96 CHAPTER ...
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Port 5 This is a 4-bit N-ch open-drain I/O port with output latches. Port 5 can be set to input or output mode in 1-bit units by using port mode register 5 (PM5). For a mask ROM version, whether ...
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Port 6 This is an 8-bit input port. The port is also used as an analog input to the A/D converter. Figure 6-13 shows a block diagram of port 6. Figure 6-13. Block Diagram of P60 to P67 RD ...
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Port Function Control Registers The following two types of registers are used to control the ports. • Port mode registers (PM0 to PM3, and PM5) • Pull-up resistor option registers (PU0, PUB2, and PUB3) (1) Port mode registers (PM0 ...
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Table 6-3. Port Mode Register and Output Latch Settings for Using Alternate Functions Pin Name Name P25 TI80 P26 TO80 P30 INTP0 TI81 CPT90 P31 INTP1 TO81 P32 INTP2 TO90 P33 INTP3 TO82 BZO90 Caution When using the pins of ...
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Pull-up resistor option registers B2 and B3 (PUB2 and PUB3) These registers specify whether an on-chip pull-up resistor is connected to each pin of ports 2 and 3. The pin specified by PUB2 or PUB3 is connected to on-chip ...
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Operation of Port Functions The operation of a port differs depending on whether the port is set to input or output mode, as described below. 6.4.1 Writing to I/O port (1) In output mode A value can be written ...
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CHAPTER 7 CLOCK GENERATOR 7.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are used. • Main system clock oscillator <Expanded-specification products> ...
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Figure 7-1. Block Diagram of Clock Generator Internal bus FRC SCC Suboscillation mode register (SCKM) XT1 Subsystem f XT clock oscillator XT2 X1 Main system clock oscillator X2 STOP Processor clock control register (PCC) 104 CHAPTER 7 CLOCK GENERATOR Prescaler ...
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Registers Controlling Clock Generator The clock generator is controlled by the following registers. • Processor clock control register (PCC) • Suboscillation mode register (SCKM) • Subclock control register (CSS) (1) Processor clock control register (PCC) PCC selects the CPU ...
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Suboscillation mode register (SCKM) SCKM specifies whether to use a feedback resistor for the subsystem clock, and controls the oscillation of the clock. SCKM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SCKM to ...
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Subclock control register (CSS) CSS specifies whether the main system or subsystem clock oscillator used. It also specifies how the CPU clock operates. CSS is set with a 1-bit or 8-bit memory manipulation instruction. RESET input ...
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System Clock Oscillators 7.4.1 Main system clock oscillator The main system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected across the X1 and X2 pins. An external clock can also be input to ...
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Subsystem clock oscillator The subsystem clock oscillator is oscillated by the crystal resonator (32.768 kHz TYP.) connected across the XT1 and XT2 pins. An external clock can also be input to the circuit. In this case, input the clock ...
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Examples of incorrect oscillator connection Figure 7-7 shows examples of incorrect oscillator connections. Figure 7-7. Examples of Incorrect Oscillator Connection (1/2) (a) Wiring too long V X1 SS0 (c) Wiring near high alternating current SS0 Remark ...
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Figure 7-7. Examples of Incorrect Oscillator Connection (2/2) (e) Signals are fetched X1 V SS0 Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor to the XT2 pin in series. ...
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Clock Generator Operation The clock generator generates the following clocks and controls operation modes of the CPU, such as standby mode. • Main system clock f X • Subsystem clock f XT • CPU clock f CPU • Clock ...
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Changing Setting of System Clock and CPU Clock 7.6.1 Time required for switching between system clock and CPU clock The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC) and bit ...
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Switching between system clock and CPU clock The following figure illustrates how the CPU clock and system clock switch. Figure 7-8. Switching Between System Clock and CPU Clock V DD RESET Interrupt request signal System clock CPU clock <1> ...
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Timer 90 Functions 16-bit timer 90 has the following functions. • Timer interrupt • Timer output • Buzzer output • Count value capture (1) Timer interrupt An interrupt is generated when a count value and compare value matches. ...
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Timer 90 Configuration 16-bit timer 90 consists of the following hardware. Table 8-1. Configuration of 16-Bit Timer 90 Item 16 bits × 1 (TM90) Timer counter Registers Compare register: Capture register: Timer outputs 1 (TO90) Control registers 16-bit ...
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TOF90 CPT901 CPT900 TOC90 TCL901TCL900 TOE90 Synchronization circuit CTP90/INTP0 /TI81/P30 16-bit capture register Edge detector 90 (TCP90) ...
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The value specified in CR90 is compared with the count in 16-bit timer register 90 (TM90). If they match, an interrupt request (INTTM90) is issued by CR90. CR90 is set with an 8-bit or ...
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Registers Controlling 16-Bit Timer 90 The following three registers control 16-bit timer 90. • 16-bit timer mode control register 90 (TMC90) • Buzzer output control register 90 (BZC90) • Port mode register 3 (PM3) (1) 16-bit timer mode control ...
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Figure 8-2. Format of 16-Bit Timer Mode Control Register 90 Symbol 7 <6> TMC90 TOD90 TOF90 CPT901 CPT900 TOC90 TCL901 TCL900 TOE90 TOD90 0 Timer output Timer output of 1 TOF90 0 Reset or cleared ...
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Remarks Main system clock oscillation frequency Subsystem clock oscillation frequency XT (2) Buzzer output control register 90 (BZC90) This register selects the buzzer frequency based on fcl selected with the count clock select ...
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Table 8-2. Buzzer Frequency of 16-Bit Timer 90 BCS902 BCS901 BCS900 156 kHz 78.1 kHz 9.76 kHz 4.88 kHz 2.44 kHz 1.22 ...
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Operation of 16-Bit Timer 90 8.4.1 Operation as timer interrupt 16-bit timer 90 can generate interrupts repeatedly each time the free-running counter value reaches the value set to CR90. Since this counter is not cleared and holds the count ...
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Table 8-3. Interval Time of 16-Bit Timer 90 TCL901 TCL900 operation 1/f XT Note Expanded-specification products ...
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Operation as timer output 16-bit timer 90 can invert the timer output repeatedly each time the free-running counter value reaches the value set to CR90. Since this counter is not cleared and holds the count even after the timer ...
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Capture operation The capture operation consists of latching the count value of 16-bit timer register 90 (TM90) into a capture register in synchronization with a capture trigger, and retaining the count value. Set TMC90 as shown in Figure 8-9 ...
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The count value of 16-bit timer counter 90 (TM90) is read out with a 16-bit manipulation instruction. TM90 readout is performed via a counter read buffer. The counter read buffer latches the TM90 count ...
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Buzzer output operation The buzzer frequency is set using buzzer output control register 90 (BZC90) based on the count clock selected with TCL901 and TCL900 of TMC90 (source clock). A square wave of the set buzzer frequency is output. ...
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Notes on 16-Bit Timer 90 8.5.1 Notes on using 16-bit timer 90 Usable functions differ according to the settings of the count clock selection, CPU clock operation, system clock oscillation status, and BZOE90 (bit 0 of buzzer output control ...
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Make the following settings to enable low-current consumption when stopping the main system clock oscillation and releasing the HALT mode. Count clock: Subsystem clock CPU clock: Subsystem clock Main system clock: Oscillation stopped BZOE90: 1 (Buzzer output enable) At this ...
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Restrictions on rewriting of 16-bit compare register 90 (1) When rewriting the compare register (CR90), be sure to disable interrupts (TMMK90 = 1), and disable inversion control of timer output (TOC90 = 0) first. If CR90 is rewritten with ...
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B> Rewriting by 16-bit access <1> Disable interrupt (TMMK90 = 1), and disable inversion control of timer output (TOC90 = 0) <2> Rewrite CR90 (16 bits) <3> Wait for more than one cycle of the count clock <4> ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 9.1 Functions of 8-Bit Timer/Event Counters 8-bit timer/event counters 80 and 81 and 8-bit timer 82 have the following functions. • Interval timer (TM80, TM81, TM82) • External event ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (2) External event counter The number of pulses of an externally input signal can be counted. (3) Square wave output A square wave of arbitrary frequency can be output. Table 9-4. Square ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 9.2 Configuration of 8-Bit Timer/Event Counters 8-bit timer/event counters consist of the following hardware. Table 9-7. Configuration of 8-Bit Timer/Event Counters Item 8 ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Figure 9-1. Block Diagram of 8-Bit Timer/Event Counter 80 Internal bus 8-bit compare register 80 (CR80) Match f Clear X 8-bit timer counter (TM80) TI80/P25/ SS20 OVF ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Figure 9-3. Block Diagram of 8-Bit Timer 82 Internal bus 8-bit compare register 82 (CR82) Match Clear 8-bit timer counter (TM82 ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 9.3 8-Bit Timer/Event Counters Control Registers The following two types of registers are used to control the 8-bit timer/event counter. • 8-bit timer mode control registers 80, 81, and ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (2) 8-bit timer mode control register 81 (TMC81) TMC81 determines whether to enable or disable 8-bit timer counter 81 (TM81), specifies the count clock for TM81, and controls the operation of the ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (3) 8-bit timer mode control register 82 (TMC82) TMC82 determines whether to enable or disable 8-bit timer counter 82 (TM82) and specifies the count clock for TM82. It also controls the operation ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (4) Port mode registers 2 and 3 (PM2 and PM3) PM2 and PM3 specify whether each bit of port 2 and port 3 is used for input or output. To use the ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 9.4 Operation of 8-Bit Timer/Event Counters 9.4.1 Operation as interval timer The interval timer repeatedly generates an interrupt at time intervals specified by the count value set in 8-bit ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Table 9-9. Interval Time of 8-Bit Timer/Event Counter 81 TCL811 TCL810 Minimum Interval Time µ (1.6 s) [3.2 X µ (25.6 X ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 9.4.2 Operation as external event counter The external event counter counts the number of external clock pulses input to the TI80/P25/SS20 or TI81/P30/INTP0/CPT90 pin by using 8-bit timer counters ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 9.4.3 Operation as square wave output The 8-bit timer/event counter can generate output square waves of an arbitrary frequency at intervals specified by the count value set in 8-bit compare registers 8n ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Table 9-13. Square Wave Output Range of 8-Bit Timer 82 TCL821 TCL820 Minimum Pulse Width (3 (12 1/f ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 9.4.4 PWM output operation PWM output enables generation of an interrupt repeatedly at intervals specified by the count value set in 8-bit compare register 8n (CR8n) in advance. To use 8-bit timer/event ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS Count clock TM8n 00H 01H M CR8n TCE8n OVF INTTM8n Note TO8n M = 01H to FFH Note The initial value of TO8n is low for output enable (TOE8n = 1). Caution ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 9.5 Notes on Using 8-Bit Timer/Event Counters (1) Error on starting timer An error 1.5 clocks is included in the time between when the timer is ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (2) Count value if external clock input from TI8n pin is selected When the rising edge of the external clock signal input from the TI8n pin is selected as the count clock, ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (3) Setting of 8-bit compare register 8n 8-bit compare register 8n (CR8n) can be set to 00H. Therefore, one pulse can be counted when an 8-bit timer/event counter operates as an event ...
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CHAPTER 9 8-BIT TIMER/EVENT COUNTERS (4) Timer operation after compare register is rewritten during PWM output When 8-bit compare register 8n (CR8n) is rewritten during PWM output, if the new value is smaller than that of 8-bit ...
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Watch Timer Functions The watch timer has the following functions. • Watch timer • Interval timer The watch and interval timers can be used at the same time. Figure 10 block diagram of the watch timer. Figure ...
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Watch timer The 4.19 MHz main system clock or 32.768 kHz subsystem clock is used to issue an interrupt request (INTWT) at 0.5-second intervals. Caution When the main system clock is operating at 5.0 MHz, it cannot be used ...
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Watch Timer Control Register The watch timer mode control register (WTM) is used to control the watch timer. • Watch timer mode control register (WTM) WTM selects a count clock for the watch timer and specifies whether to enable ...
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Watch Timer Operation 10.4.1 Operation as watch timer The main system clock (4.19 MHz) or subsystem clock (32.768 kHz) is used to enable the watch timer to operate at 0.5-second intervals. The watch timer is used to generate an ...
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Figure 10-3. Watch Timer/Interval Timer Operation Timing 5-bit counter 0H Start Count clock Watch timer interrupt INTWT Watch timer interrupt time (0.5 s) Interval timer interrupt INTWTI Interval timer (T) Caution When operation of the watch ...
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Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (WDTM). (1) Watchdog timer The watchdog ...
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Watchdog Timer Configuration The watchdog timer consists of the following hardware. Table 11-3. Configuration of Watchdog Timer Item Control registers Timer clock selection register 2 (TCL2) Watchdog timer mode register (WDTM) Figure 11-1. Block Diagram of Watchdog Timer f ...
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Watchdog Timer Control Registers The following two types of registers are used to control the watchdog timer. • Timer clock selection register 2 (TCL2) • Watchdog timer mode register (WDTM) (1) Timer clock selection register 2 (TCL2) This register ...
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Watchdog timer mode register (WDTM) This register sets an operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears WDTM to 00H. ...
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Watchdog Timer Operation 11.4.1 Operation as watchdog timer The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The count clock (inadvertent loop detection time interval) ...
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Operation as interval timer When bits 4 and 3 (WDTM4, WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1, respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at ...
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CHAPTER 12 8-BIT A/D CONVERTER ( 12.1 8-Bit A/D Converter Functions The 8-bit A/D converter is an 8-bit resolution converter that converts an analog input to a digital signal. This converter can control eight channels (ANI0 to ANI7) of analog ...
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CHAPTER 12 8-BIT A/D CONVERTER ( Figure 12-1. Block Diagram of 8-Bit A/D Converter ANI0/P60 ANI1/P61 ANI2/P62 ANI3/P63 ANI4/P64 ANI5/P65 ANI6/P66 ANI7/P67 3 ADS02 ADS01 ADS00 ADCS0 FR02 A/D input selection register 0 (ADS0) (1) Successive approximation register (SAR) SAR ...
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CHAPTER 12 8-BIT A/D CONVERTER ( (4) Voltage comparator The voltage comparator compares an analog input with the voltage output by the series resistor string. (5) Series resistor string The series resistor string is configured between AV which analog inputs ...
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CHAPTER 12 8-BIT A/D CONVERTER ( 12.3 8-Bit A/D Converter Control Registers The following two registers are used to control the 8-bit A/D converter. • A/D converter mode register 0 (ADM0) • A/D input selection register 0 (ADS0) (1) A/D ...
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CHAPTER 12 8-BIT A/D CONVERTER ( (2) A/D input selection register 0 (ADS0) ADS0 specifies the port used to input the analog voltage to be converted to a digital signal. ADS0 is set with a 1-bit or 8-bit memory manipulation ...
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CHAPTER 12 8-BIT A/D CONVERTER ( 12.4 8-Bit A/D Converter Operation 12.4.1 Basic operation of 8-bit A/D converter <1> Select a channel for A/D conversion, using A/D input selection register 0 (ADS0). <2> The voltage supplied to the selected analog ...
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CHAPTER 12 8-BIT A/D CONVERTER ( Figure 12-4. Basic Operation of 8-Bit A/D Converter Sampling time A/D converter Sampling operation 80H SAR Undefined ADCR0 INTAD0 A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is ...
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CHAPTER 12 8-BIT A/D CONVERTER ( Figure 12-5. Relationship Between Analog Input Voltage and A/D Conversion Result 255 254 253 A/D conversion result (ADCR0 512 256 512 User’s Manual U14186EJ6V0UD PD789167 AND 789167Y SUBSERIES) ...
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CHAPTER 12 8-BIT A/D CONVERTER ( 12.4.3 Operation mode of 8-bit A/D converter The A/D converter is initially in select mode. In this mode, A/D input selection register 0 (ADS0) is used to select an analog input channel from ANI0 ...
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CHAPTER 12 8-BIT A/D CONVERTER ( 12.5 Cautions Related to 8-Bit A/D Converter (1) Current consumption in standby mode In standby mode, the A/D converter stops operating. Setting bit 7 (ADCS0) of A/D converter mode register 0 (ADM0 ...
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CHAPTER 12 8-BIT A/D CONVERTER ( (5) Timing of undefined A/D conversion result The A/D conversion value may become undefined if the timing of the completion of A/D conversion and that to stop the A/D conversion operation conflict. Therefore, read ...
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CHAPTER 12 8-BIT A/D CONVERTER ( (6) Noise prevention To maintain a resolution of 8 bits, watch out for noise on the AV output impedance of the analog input source, the larger the effect from noise. To reduce noise, attach ...
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CHAPTER 12 8-BIT A/D CONVERTER ( (10) Interrupt request flag (ADIF0) Changing the content of A/D converter mode register 0 (ADM0) does not clear the interrupt request flag (ADIF0). If the analog input pins are changed during A/D conversion, therefore, ...
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CHAPTER 13 10-BIT A/D CONVERTER ( 13.1 10-Bit A/D Converter Functions The 10-bit A/D converter is a 10-bit resolution converter that converts an analog input to a digital signal. This converter can control eight channels (ANI0 to ANI7) of analog ...
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CHAPTER 13 10-BIT A/D CONVERTER ( Figure 13-1. Block Diagram of 10-Bit A/D Converter ANI0/P60 ANI1/P61 ANI2/P62 ANI3/P63 ANI4/P64 ANI5/P65 ANI6/P66 ANI7/P67 3 ADS02 ADS01 ADS00 ADCS0 FR02 A/D input selection register 0 (ADS0) (1) Successive approximation register (SAR) SAR ...
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CHAPTER 13 10-BIT A/D CONVERTER ( (3) Sample-and-hold circuit The sample-and-hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends them to the voltage comparator. The sampled analog input voltage is held during A/D conversion. ...
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CHAPTER 13 10-BIT A/D CONVERTER ( 13.3 10-Bit A/D Converter Control Registers The following two registers are used to control the 10-bit A/D converter. • A/D converter mode register 0 (ADM0) • A/D input selection register 0 (ADS0) (1) A/D ...
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CHAPTER 13 10-BIT A/D CONVERTER ( (2) A/D input selection register 0 (ADS0) ADS0 specifies the port used to input the analog voltage to be converted to a digital signal. ADS0 is set with a 1-bit or 8-bit memory manipulation ...
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CHAPTER 13 10-BIT A/D CONVERTER ( 13.4 10-Bit A/D Converter Operation 13.4.1 Basic operation of 10-bit A/D converter <1> Select a channel for A/D conversion, using A/D input selection register 0 (ADS0). <2> The voltage supplied to the selected analog ...
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CHAPTER 13 10-BIT A/D CONVERTER ( Figure 13-4. Basic Operation of 10-Bit A/D Converter Sampling time A/D converter Sampling operation 300H 200H SAR Undefined 100H ADCR0 INTAD0 A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 ...
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CHAPTER 13 10-BIT A/D CONVERTER ( Figure 13-5. Relationship Between Analog Input Voltage and A/D Conversion Result 1,023 1,022 1,021 A/D conversion result (ADCR0 184 PD789177 AND 789177Y SUBSERIES 2,043 ...
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CHAPTER 13 10-BIT A/D CONVERTER ( 13.4.3 Operation mode of 10-bit A/D converter The A/D converter is initially in select mode. In this mode, A/D input selection register 0 (ADS0) is used to select an analog input channel from ANI0 ...
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CHAPTER 13 10-BIT A/D CONVERTER ( 13.5 Cautions Related to 10-Bit A/D Converter (1) Current consumption in standby mode In standby mode, the A/D converter stops operating. Stopping conversion (bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) = ...
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CHAPTER 13 10-BIT A/D CONVERTER ( (5) Timing of undefined A/D conversion result The A/D conversion value may become undefined if the timing of the completion of A/D conversion and that to stop the A/D conversion operation conflict. Therefore, read ...
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CHAPTER 13 10-BIT A/D CONVERTER ( (6) Noise prevention To maintain a resolution of 10 bits, watch out for noise on the AV output impedance of the analog input source, the larger the effect from noise. To reduce noise, attach ...
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CHAPTER 13 10-BIT A/D CONVERTER ( (10) Interrupt request flag (ADIF0) Changing the content of A/D converter mode register 0 (ADM0) does not clear the interrupt request flag (ADIF0). If the analog input pins are changed during A/D conversion, therefore, ...
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CHAPTER 14 SERIAL INTERFACE 20 14.1 Functions of Serial Interface 20 Serial interface 20 has the following three modes. • Operation stop mode • Asynchronous serial interface (UART) mode • 3-wire serial I/O mode (1) Operation stop mode This mode ...
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Serial operation mode register 20 (CSIM20) CSIE20 SSE20 DAP20 DIR20 CSCK20 CKP20 SI20/P22/ RxD20 Output latch (P21) SO20/P21/ TxD20 Parity detection Stop bit detection Reception data counter Start bit detection SS20/P25/ CSIE20 TI80 Clock phase SCK20/P20/ control ASCK20 Note See ...
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Figure 14-2. Block Diagram of Baud Rate Generator 20 Reception detection clock Transmission shift clock Reception shift clock TXE20 RXE20 CSIE20 Reception detected Transmission 1/2 clock counter 1/2 Reception clock counter TPS203 TPS202 TPS201 TPS200 Baud rate generator control register ...
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CHAPTER 14 SERIAL INTERFACE 20 (1) Transmission shift register 20 (TXS20) TXS20 is a register in which transmission data is prepared. The transmission data is output from TXS20 bit serially. When the data length is seven bits, bits 0 to ...
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Control Registers of Serial Interface 20 Serial interface 20 is controlled by the following registers. • Serial operation mode register 20 (CSIM20) • Asynchronous serial interface mode register 20 (ASIM20) • Asynchronous serial interface status register 20 (ASIS20) • ...
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Asynchronous serial interface mode register 20 (ASIM20) ASIM20 is used to make the settings related to the asynchronous serial interface mode. ASIM20 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ASIM20 to 00H. Figure ...
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Table 14-2. Operating Mode Settings of Serial Interface 20 (1) Operation stop mode ASIM20 CSIM20 PM22 TXE20 RXE20 CSIE20 DIR20 CSCK20 × × × Note Other than above (2) 3-wire serial I/O mode ASIM20 CSIM20 PM22 ...
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CHAPTER 14 SERIAL INTERFACE 20 (3) Asynchronous serial interface status register 20 (ASIS20) ASIS20 indicates the type of a reception error error occurs while asynchronous serial interface mode is set. ASIS20 is set with a 1-bit or 8-bit ...
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Baud rate generator control register 20 (BRGC20) BRGC20 is used to specify the serial clock for serial interface 20. BRGC20 is set with an 8-bit memory manipulation instruction. RESET input clears BRGC20 to 00H. Figure 14-6. Format of Baud ...
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CHAPTER 14 SERIAL INTERFACE 20 The baud rate transmit/receive clock to be generated is either a signal scaled from the system clock signal scaled from the clock input to the ASCK20 pin. (a) Generation of baud rate transmit/receive ...
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Generation of baud rate transmit/receive clock from external clock input to ASCK20 pin The transmit/receive clock is generated by scaling the clock input from the ASCK20 pin. The baud rate of a clock generated from the clock input to ...