ALC650 REALTEK, ALC650 Datasheet
ALC650
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ALC650 Summary of contents
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... ALC650-VF ALC650-VF-LF SIX-CHANNEL AC’97 AUDIO CODEC DATASHEET Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211. Fax: +886-3-577-6047 www.realtek.com.tw Rev. 1.3 06 December 2005 Track ID: JATR-1076-21 ...
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... In that event, please contact your Realtek representative for additional information that may help in the development process. REVISION HISTORY Revision Release Date 1.3 2005/12/06 Six-Channel AC’97 2.3 Audio Codec Summary Update section 6.1.12 MX1A Record Select, page 11. Update section 12. Ordering Information, page 42. ii ALC650 DataSheet Rev1.3 ...
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... MX38 Surround Master Volume.............................................................................................. 18 6.1.25 MX3A S/PDIF Output Channel Status and Control .......................................................................... 18 6.1.26 MX64 Surround DAC Volume ................................................................................................. 19 6.1.27 MX66 Center/LFE DAC Volume ............................................................................................. 19 6 ENDOR EFINED EGISTERS 6.2.1 MX60 S/PDIF Input Channel Status [15:0] .............................................................................. 19 Six-Channel AC’97 2.3 Audio Codec Table of Contents V I ................................................................. 3 ERSION DENTIFICATION ........................................................................................................... 19 iii ALC650 DataSheet Rev1.3 ...
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... ESET 9 .......................................................................................................................................... 35 NPUT 9 DDRESSED EGISTER 9 ......................................................................................................................... 36 OWER DOWN ODE 9 ....................................................................................................................................... 36 EST ODE 9.7.1 ATE In Circuit Test Mode.......................................................................................................... 36 9.7.2 Vendor Specific Test Mode ........................................................................................................ 36 10. APPLICATION CIRCUITS.............................................................................................................. 37 11. MECHANICAL DIMENSIONS ....................................................................................................... 41 12. ORDERING INFORMATION ......................................................................................................... 42 Six-Channel AC’97 2.3 Audio Codec .......................................................................................................... 27 A ................................................................................................. 35 CCESS iv ALC650 DataSheet Rev1.3 ...
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... Power Down) control for use in notebook and PC applications. The ALC650 integrates a 50mW/20ohm headset audio amplifier into the CODEC, which can save BOM costs. The ALC650 also supports an AC’97 2.2 compliant SPDIF out function which allows easy connection of the PC to consumer electronic products, such as AC3 decoder/speaker and minidisk. ...
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... Block Diagram Six-Channel AC’97 2.3 Audio Codec ALC650 DataSheet 2 Rev1.3 ...
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... Pin Assignments 4.1 Lead (Pb)-Free Package and Version Identification Lead (Pb)-free package is indicated by an ‘L’ in the location marked ‘T’ in the figures above. The version number is shown in the location marked ‘VV’. Six-Channel AC’97 2.3 Audio Codec ALC650 DataSheet 3 Rev1.3 ...
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... Analog input (1Vrms) / Analog output (1Vrms) Analog input (1Vrms) for front panel MIC input Analog output (1Vrms) Analog output (1Vrms) Analog output (1Vrms) Analog output (1Vrms) Analog output (1Vrms) Analog output (1Vrms) Analog output (1Vrms) 4 ALC650 DataSheet Characteristic Definition =0.3Vdd, V =0.4Vdd L H =0.3Vdd, V =0.4Vdd ...
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... The minimum value is 3.0V The maximum value is 5.5V The minimum value is 3.0V (DVdd-0.3) The maximum value is 3.6V (DVdd+0.3) The minimum value is 3.0V (DVdd-0.3) The maximum value is 3.6V (DVdd+0.3) Description Internal pull high 5 ALC650 DataSheet Characteristic Definition TOTAL: 9 Pins Characteristic Definition TOTAL: 8 Pins Characteristic Definition TOTAL: 1 Pin Rev1.3 ...
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... ALC650 DataSheet DEFAULT ID6 ID5 ID4 ID3 ID2 ID1 ID0 X X MR4 MR3 MR2 MR1 MR0 X X MM4 MM3 MM2 MM1 MM0 X X PB3 PB2 PB1 ...
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... MR/ML are 5-bit R/W variables. The 6th bit implementation is optional. For this reason, when 6th bit is written equivalent to writing low 5-bit with 1. For example, writing 1xxxxx will read back 01111. Six-Channel AC’97 2.3 Audio Codec Function Function 1: Mute (-∞ dB) 7 ALC650 DataSheet Rev1.3 ...
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... The purpose of this register is to allow the PC Beep signals to pass through the ALC650, eliminating the need for an external system speaker/buzzer. The PC BEEP pin is directly routed (internally hardwired) to the LINE-OUTL & R pins. If the PC speaker/buzzer is eliminated recommended to connect the external speakers at all times so the POST codes can be heard during reset ...
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... Line-In Right Volume (NR[4:0]) in 1.5 dB steps For NL/NR, 00h +12 dB Gain 08h 0dB gain 1Fh -34.5dB Gain Six-Channel AC’97 2.3 Audio Codec Function 1: Mute (-∞ dB) +12 dB Gain 0dB gain -34.5dB Gain Function 1: Mute (-∞ dB) +12 dB Gain 0dB gain -34.5dB Gain Function 1: Mute (-∞ dB) 9 ALC650 DataSheet Rev1.3 ...
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... AUX Left Volume (AL[4:0]) in 1.5 dB steps 7:5 - Reserved 4:0 R/W AUX Right Volume (AR[4:0]) in 1.5 dB steps For AL/AR, 00h +12 dB Gain 08h 0dB gain 1Fh -34.5dB Gain Six-Channel AC’97 2.3 Audio Codec Function 1: Mute (-∞ dB) +12 dB Gain 0dB gain -34.5dB Gain 1: Mute (-∞ dB) Function 1: Mute (-∞ dB) 10 ALC650 DataSheet Rev1.3 ...
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... AUX LEFT 4 LINE LEFT 5 STEREO MIXER OUTPUT LEFT 6 MONO MIXER OUTPUT 7 PHONE For RRS 0 MIC 1 CD RIGHT 2 VIDEO RIGHT 3 AUX RIGHT 4 LINE RIGHT 5 STEREO MIXER OUTPUT RIGHT 6 MONO MIXER OUTPUT 7 PHONE Six-Channel AC’97 2.3 Audio Codec Function 1: Mute (-∞ dB) Function 11 ALC650 DataSheet Rev1.3 ...
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... Note that the 3D bit in the general purpose register (bit 13) must be set enable this function. Bit Type 15:2 - Reserved. Read as 0 1:0 R/W Depth control (DP[1:0]) 3D effect control Six-Channel AC’97 2.3 Audio Codec Function 1: Mute (-∞ dB) 0Fh +22.5dB 00h 0 dB (No Gain) Function 0: Off Function DP[1: ALC650 DataSheet Function 0%(off) 50% 75% 100% Rev1.3 ...
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... Power down PCM DAC (front DAC) 1: Power down PCM ADC and input MUX 0: Not yet 0: Not yet LDAC ADC DAC Mixer * Blank: Don’t care High: output high 13 ALC650 DataSheet Vref ACLINK Int CLK EAPD High Rev1.3 ...
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... ID1 and ID0 echo the configuration of the CODEC as defined by the programming of pins 47 and 48 externally. “00” returned defines the CODEC as the primary CODEC, while any other code identifies the CODEC as one of three secondary CODEC possibilities. SDAC/LDAC/CDAC=1 tells the controller that the ALC650 is a multi-channel CODEC as defined by the Intel spec. Bit ...
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... Only front DACs supports 96KHz sample rate when DRA=1. MX2A.1 just selects clock source for front DACs. Software must set MX2C/MX2E/MX30 as BB80h, and mute surround DACs and CEN/LFE DACs. ☼ If VRA = 0, ALC650 AD/DA operate at fixed 48KHz sampling rate. Otherwise, it operates with variable sampling rate defined in MX2C, MX2E, MX30 and MX32. Six-Channel AC’97 2.3 Audio Codec ...
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... MX2C PCM Front/Center Output Sample Rate Default: BB80H The ALC650 allows adjustment of the front center output sample rate. This register is used to adjust the sample rate. By changing the values, sampling rates from 8000 to 48000 can be chosen. Bit Type 15:0 R/W FOSR [15:0]Output sampling rate The ALC650 supports the following sampling rates as required in the PC99 design guide ...
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... MX30 PCM LFE Output Sample Rate Default: BB80H The ALC650 allows adjustment of the PCM LFE output sample rate. This register is used to adjust the sample rate. By changing the values, sampling rates from 8000 to 48000 can be chosen. (See table under Section 6.1.19) Bit Type ...
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... The V bit in sub-frame is always send indicate the invalid data is not suitable for receiver 14 R DRS (Double Rate S/PDIF) The ALC650 does not support double rate S/PDIF, this bit is always 0. 13:12 R/W SPSR [1:0] (S/PDIF Sample Rate) 00: Sample rate set to 44.1KHz. Fs[0:3]=0000 01: Reserved 10: Sample rate set to 48 ...
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... These registers, as not defined in the AC’97 specifications, are available to Realtek and Realtek customers for specialized functionality. 6.2.1 MX60 S/PDIF Input Channel Status [15:0] Default: 0000H S/PDIF Input is implemented on the ALC650 Rev later only, and this register is for use with that product only. Bit Type 15 ...
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... MX62 S/PDIF Input Channel Status [29:15] Default: 0000H S/PDIF Input is implemented on the ALC650 Rev later only, and this register is for use with that product only. Bit Type 15 R Vbit in Sub-frame of SPDIF-In: This bit reflects the Validity status of SPDIF-In, and is effective only when SPDIF-In is locked ...
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... The default source of S/PDIF output is data sent by controller. When this bit is set, S/PDIF data comes from ALC650’s ADC is used to transfer analog input into S/PDIF output. To keep data concurrence, software must guarantee that the sample rates in MX32 and MX3A[13:12] are the same. SPCV is no longer valid for an S/PDIF configuration. If software doesn’ ...
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... LFE Pin- MIC1 MIC1 CEN-OUT CEN-OUT 22 ALC650 DataSheet Surr Right Center LFE DAC slot DAC slot DAC slot SPDIF Out Surround DAC ADC SPDIF Input - + Pin-24 ...
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... GPIO0 Primitiveness Control 0: Set GPIO0 as input pin 1: Set GPIO0 as output pin Note that GPIO1 is not physically connected to a pad, so the system designer should not try to use it. Six-Channel AC’97 2.3 Audio Codec Function 1: Enable 1: Enable 23 ALC650 DataSheet will trigger the GPIO interrupt in bit0 of Rev1.3 ...
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... When GPIO1/0 is used as an input pin, its status will also be reflected in bit2/1 of SDIN’s slot- 12. Once GPIO1/0 is used as output pin, the bit2/1 of SDATA_IN’s slot-12 is always 0. The GPIOx is internally pulled high by a weak resistor. (Weak resistor is about 50K ~ 100K ohm) Six-Channel AC’97 2.3 Audio Codec ALC650 DataSheet Function 24 Rev1.3 ...
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... The two registers (MX7C Vendor ID1 and MX7E Vendor ID2) contain four 8-bit ID codes. The first three codes have been assigned by Microsoft for Plug and Play definitions. The fourth code is a Realtek assigned code identifying the ALC650. The MX7C Vendor ID1 register contains the value 414Ch, which is the first and second characters of the Microsoft ID code. The MX7C Vendor ID2 register contains the value 4720h, which is the third of the Microsoft ID code ...
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... Type 15:14 - Reserved 13 R/W Ignore V bit in sub-frame of SPDIF-IN (Supported by the ALC650 Rev Disable, SPDIF-IN FIFO will keep the last valid data. (default) 1: Enable, SPDIF-IN FIFO will catch the SPDIF-In data in spite of the V bit. 12 R/W Vrefout Disable (Supported by the ALC650 Rev. E and Rev.F) 0: Vrefout is driven by the internal reference (Default) 1: Vrefout is in high-Z mode ...
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... Six-Channel AC’97 2.3 Audio Codec 0 C, with 50pF external load. Typical Maximum V -0.30 - DVdd+0. 1 1.7 / 1.0 - 2.0 / 1.2 0.40*DVdd 2 3.2 / 2.2 - 2.5 / 1.7 V 0.9DVdd - 50K 100K - - - Symbol Minimum Typical Maximum 1.0 - rst_low T 162.8 - rst2clk Cold reset timing diagram 27 ALC650 DataSheet Units V 0.30*DVdd 0.1DVdd V 200K Ohm 10 µA 10 µ Units - µ Rev1.3 ...
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... SYNC inactive to BIT_CLK Startup delay 7.2.3 AC-Link Clocks The ALC650 derives its clock internally from an externally connected 24.576MHz crystal or an oscillator through the XTAL_IN pin. Synchronization with the AC’97 controller is achieved through the BIT_CLK pin at 12.288MHz (half of the crystal frequency). The beginning of all audio sample packets, or “Audio Frames,” transferred over AC-Link is synchronized to the rising edge of the “ ...
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... Note: Combined rise or fall plus flight times are provided for worst case scenario modeling purpose. Six-Channel AC’97 2.3 Audio Codec Data Output and Input timing diagram Symbol Minimu Typical Maximum Symbol Minimu Typical Maximum setup hold Symbol Minimu Typical Maximum ALC650 DataSheet Units 15 ns Units - Units Rev1.3 ...
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... Signal Rise and Fall timing diagram Symbol Minimum Typical Trise - - clk Tfall - - clk Trise - - sync Tfall - - sync Trise - - din Tfall - - din Trise - - dout Tfall - - dout ALC650 DataSheet Maximum Units Rev1.3 ...
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... AC-Link Low Power Mode Timing The ALC650 AC-Link can be placed into low power mode by programming register 26h. Both BIT_CLK and SDATA_IN will be brought to and held at a logic low voltage level. The AC’97 controller can wake up the ALC650 by providing the proper reset signals. ...
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... CNR (Communication Network Riser) specifications Rev.1.0 pages 23~25 or AC’97 Rev.2.2 for detailed information. Six-Channel AC’97 2.3 Audio Codec 1 CODEC 2 CODEC 3 CODEC 4 CODEC 55pF 47.5pF Minimum Typical Maximum (h) ( (r) ( (r) (l) ( (f) (l) ( (h) (l) (h) 32 ALC650 DataSheet 62.5pF 75pF 85pF 55pF 60pF 62.5pF Unit 90% 10% Rev1.3 ...
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... ALC650 DataSheet Maximum Units - Vrms - Vrms - Vrms - Vrms - Vrms - Vrms - Vrms - dB FSA - dB FSA - dB FSA - dB FSA - 22,000 Hz 19,200 KΩ - KΩ - KΩ ...
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... When the ALC650 takes serial data from the AC’97 controller, it samples SDATA_OUT on the falling edge of BIT_CLK. When the ALC650 sends serial data to the AC’97 controller, it starts to drive SDATA_IN on the rising edge of BIT_CLK. The ALC650 will return any uninstalled bits or registers with 0 for the read operation. The ALC650 also stuffs the unimplemented slot or bit with 0 in SDATA-IN. Note that AC-LINK is MSB-justified. Refer to “ ...
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... CD Input It is crucial to take notice of differential CD Input. Below is an example of differential CD input. 9.5 Odd Addressed Register Access The ALC650 will return “0000h” when odd-addressed registers and unimplemented registers are read. Six-Channel AC’97 2.3 Audio Codec CODEC response Reset all hardware logic and all registers ...
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... Test Mode The ALC650 has two test modes. One is for ATE in circuit test and the other is for vendor specific tests. All AC-link signals are normally low through the trailing edge of RESET#. When coming out of RESET, an AC’97 CODEC enters the ATE in circuit test mode if SDATA_OUT is sampled high at the trailing edge of RESET#, and enters the vendor specific test mode if SYNC is sampled high at the trailing edge of RESET# ...
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... C26 1n 31 C29 C32 1u front-MIC 43 C34 1uf Center-Out 44 C36 1uf LFE-Out 45 GPIO0 R51 0 If 14.318M External_CLK is used (S/PDIF-In for ALC650 rev.E or later) SPDIFI (EAPD for ALC650 rev.D) SPDIFO C44 1uf Surround-Out-L Surround-Out-R C45 1uf AGND Rev1.3 ...
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... CD-IN R18 If LINE-IN is designed to be shared with Surround-Out, keep 2/3 are floated PH5 2 3 LINE IN CE1 CE2 (Can be Surr-Out) 100p 100p option 1: For ALC650 rev.D, select this bias circuit to share MIC-In and CEN/LFE-Out +5VA D2 DIODE R33 0 2N7000P/ R34 4.7K C6 1uF If MIC-IN is designed to be shared with CEN/LFE-Out, ...
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... Block-C (6 channel analog output in Mini Din connector SURR-OUT Front-L Front-R PH6 Block-D (Option: for different definition about LFE and Center) (ALC650 rev.E can switch LFE and Center output, this block can CEN/LFE be eliminated.) (Default: J8: 1-2, J9: 1-2) Center-Out Center-Jack-Out LFE-Out LFE-Jack-Out ...
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... Guaranteed transmission distance <= 7 feet Use T1,R5,R6: At least 10 feet of transmission distance R5 SPDIFO SPDIFO R6 100 360 Optional SPDIF Input/Output Connection (S/PDIF-In is only for the ALC650 Rev later) Six-Channel AC’97 2.3 Audio Codec The T1 transformer should be capable of operating from 1.5M to 7MHz (with lower shunt capacitor is preferred ...
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... CHECK 0.354 BSC 0.276 BSC 0.217 0.354 BSC 0.276 BSC 0.217 0.007 0.008 0.011 0.016 BSC 3.5 7 0.018 0.0236 0.030 0.0393 41 ALC650 DataSheet TITLE: LQFP-48 (7.0x7.0x1.6mm) LEADFRAME MATERIAL DOC. NO. VERSION 02 DWG NO. PKGC-065 DATE REALTEK SEMICONDUCTOR CORP. Rev1.3 ...
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... Ordering Information Part Number Package ALC650-VF 48-pin LQFP. Standard product ALC650-VF-LF ALC650-VF + Lead (Pb)-Free package Note: Above parts are tested under AVDD =5.0V. If customers have lower AVDD request, please contact Realtek sales representatives or agents. Realtek Semiconductor Corp. Headquarters No. 2, Innovation Road II Hsinchu Science Park, Hsinchu 300, Taiwan Tel ...