VPX3226E Micronas, VPX3226E Datasheet

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VPX3226E

Manufacturer Part Number
VPX3226E
Description
Video pixel decoder
Manufacturer
Micronas
Datasheet

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Edition Oct. 13, 1999
6251-483-1AI
MICRONAS
INTERMETALL
VPX 3226E,
VPX 3225E,
VPX 3224E
Video Pixel Decoders
ADVANCE INFORMATION

Related parts for VPX3226E

VPX3226E Summary of contents

Page 1

... MICRONAS INTERMETALL Edition Oct. 13, 1999 6251-483-1AI ADVANCE INFORMATION VPX 3226E, VPX 3225E, VPX 3224E Video Pixel Decoders ...

Page 2

... Separate Syncs/ITU-R601 2.7.1.2. Embedded Reference Headers/ITU-R656 21 2.7.1.3. Embedded Timing Codes (BStream) 21 2.7.2. Bus Shuffler 21 2.7.3. Output Multiplexer 21 2.7.4. Output Ports 22 2.8. Video Data Transfer 22 2.8.1. Single and Double Clock Mode 22 2.8.2. Clock Gating 23 2.8.3. Half Clock Mode 24 2.9. Video Reference Signals 24 2.9.1. HREF 24 2.9.2. VREF 24 2.9.3. Odd/Even Information (FIELD) 26 2.9.4. VACT 2 ADVANCE INFORMATION MICRONAS INTERMETALL ...

Page 3

... Boundary Scan Register 40 2.17.2.4. Bypass Register 40 2.17.2.5. Device Identification Register 40 2.17.2.6. Master Mode Data Register 40 2.17.3. Exception to IEEE 1149.1 40 2.17.4. IEEE 1149.1–1990 Spec Adherence 40 2.17.4.1. Instruction Register 40 2.17.4.2. Public Instructions 41 2.17.4.3. Self-Test Operation 41 2.17.4.4. Test Data Registers 41 2.17.4.5. Boundary-Scan Register 41 2.17.4.6. Device Identification Register 41 2.17.4.7. Performance 45 2.18. Enable/Disable of Output Signals MICRONAS INTERMETALL VPX 322xE 3 ...

Page 4

... Timing of all Pins connected to the Boundary-Scan-Register-Chain 67 5.7. Timing Diagram of the Digital Video Interface 67 5.7.1. Characteristics, Clock Signals 68 6. Control and Status Registers 68 6.1. Overview 71 6.1.1. Description 6.1.2. Description of FP Control and Status Registers Conditions for Low Power Mode 2 C Control and Status Registers ADVANCE INFORMATION MICRONAS INTERMETALL ...

Page 5

... Differences between VPX 322xE and VPX 3220A 88 7.3. Control Interface 88 7.3.1. Symbols 88 7.3.2. Write Data into I 88 7.3.3. Read Data from I 88 7.3.4. Write Data into FP Register 88 7.3.5. Read Data from FP Register 88 7.3.6. Sample Control Code 89 7.4. Xtal Supplier 90 7.5. Typical Application 92 8. Data Sheet History MICRONAS INTERMETALL 2 C Register 2 C Register VPX 322xE 5 ...

Page 6

... IEEE 1149.1 (JTAG) boundary scan interface – 8 input or user programmable output pins Software Support – MediaCVR Software Suite Video for Windows driver TV viewer applet, Teletext browser Intercast/Wavetop browser – WebTV for Windows Video capture and VBI services MICRONAS INTERMETALL 2 C ...

Page 7

... VPX 322xD family, but not with VPX 3220A, VPX 3216B, and VPX 3214C family. Clock Gen. DCO CVBS/Y ADC ADC Chroma SDA I2C JTAG SCL Fig. 1–1: Block diagram of the VPX 322xE MICRONAS INTERMETALL Sync Processing Text Slicer (not VPX 3224E Luma Filter Video Decoder ...

Page 8

... The clock generation is also a part of the analog front end. The crystal oscillator is controlled digitally by the FP; the clock frequency can be adjusted within 150 ppm. AGC +6/–4.5 dB clamp gain bias reference frequency generation ADVANCE INFORMATION digital CVBS or Luma ADC digital Chroma ADC system clocks DCVO 150 ppm 20.25 MHz MICRONAS INTERMETALL ...

Page 9

... IRE 32 Í Í Í Í Í Í Í Í Í 0 lower headroom = 4 steps = 0.2 dB Fig. 2–2: ADC ranges for CVBS/Luma and Chroma, PAL input signal MICRONAS INTERMETALL Input Level [ – 4 667 1333 2238 500 ...

Page 10

... In relation to the comb filter, this vertical peaking contributes greatly to an optimal two-dimensional reso- lution homogeneity. Bandpass Filter Bandpass/ Notch Filter Bandpass Filter MICRONAS INTERMETALL Luma Output Chroma Output ...

Page 11

... The last setting gives a very large boost to high frequen- cies provided for SECAM signals that are decoded using a SAW filter specified originally for the PAL stan- dard. Luma / CVBS IF Compensation DC-Reject Chroma Fig. 2–5: Color decoder MICRONAS INTERMETALL –5 –10 –15 –20 ...

Page 12

... The burst amplitude measurement is used to switch off the color if the burst amplitude is below a pro MHz grammable threshold. Thus, color will be killed for very noisy signals. The color amplitude killer has a program- mable hysteresis. ADVANCE INFORMATION C amplitudes and fed to the cross- b MICRONAS INTERMETALL ...

Page 13

... NTSC combfilter mode, Fig. 2–7 d), the delay line is in the composite signal path, thus allowing reduction of cross-color components, as well as cross-luminance. The loss of vertical resolution in the luminance channel is compensated by adding the vertical detail signal with removed color information. MICRONAS INTERMETALL VPX 322xE CVBS Luma Y Notch ...

Page 14

... HREF and VREF from the hori- zontal sync. PLL1 phase front comparator counter sync & lowpass generator clock front-end synthesizer timing syncs clamping color key FIFO_write MICRONAS INTERMETALL 8 10 MHz 8 10 MHz front sync skew vblank field clock H/V syncs ...

Page 15

... MICRONAS INTERMETALL 2.6. Component Processing Recovery of the YC C components by the decoder followed by horizontal resizing and skew compensation. Contrast enhancement with noise shaping can also be applied to the luminance signal ...

Page 16

... This automated selection is optimized for best visual performance. 16 ADVANCE INFORMATION dB 0 –10 –20 –30 – Fig. 2–13: Freq. response of 5 widely spaced filters dB 0 –2 –4 –6 –8 –10 –12 0 0.5 1 1.5 2 Fig. 2–14: Freq. response of 50 adjacent filters MICRONAS INTERMETALL 30 40 MHz 2.5 3 MHz ...

Page 17

... Fig. 2–15: Frequency response of peaking filter MICRONAS INTERMETALL 2.6. Color Space b r The color decoder outputs luminance and one multi- plexed chrominance signal at a sample clock of 20.25 MHz. Active video samples are flagged by a sepa- rate reference signal. Internally, the number of active samples is 1080 for all standards (525 lines and 625 lines) ...

Page 18

... Clock Generation n– n–1 MICRONAS INTERMETALL ADVANCE INFORMATION C 4:2:2 video format only. r Port A OE Port B PIXCLK LLC LLC2 HREF VREF VACT ...

Page 19

... EAV. The programmed windows how- ever are delayed by one line. Header suppression is always applied for SAV/EAV pairs. MICRONAS INTERMETALL VPX 322xE – For data within the VBI-window (e.g. sliced or raw tele- text data), the user can select between limitation or re- duction to 7-bit resolution with an additional LSB as- suring odd parity (0 and 255 never occur) ...

Page 20

... ADVANCE INFORMATION Bit No. LSB ... EAV EAV EAV EAV 80h 10h ... b r MICRONAS INTERMETALL ...

Page 21

... A and chrominance data on port B. With the MICRONAS INTERMETALL VPX 322xE bus shuffler, luminance can be switched to port B and chrominance to port A. In 8-bit double clock mode, shuf- fling can be used to swap the Y and C components selected with FP-RAM 0x150. Table 2– ...

Page 22

... LLC cycles are inserted before and after to allow trans- mission of SAV/EAV headers in ITU-R656 mode. ADVANCE INFORMATION Phase Information refers to the last pixel refers to the next pixel refers to the current pixel refers to the current pixel refers to the current pixel refers to the current pixel Y FEh 01h n MICRONAS INTERMETALL ...

Page 23

... Fig. 2–24: Output timing in single clock mode Video (Port A) VACT PIXCLK LLC Fig. 2–25: Output timing in double clock mode Luminance (Port A) Chrominance (Port B) VACT PIXCLK LLC Fig. 2–26: Output timing in half clock mode MICRONAS INTERMETALL n– n– ...

Page 24

... This filtering can be disabled with FP- RAM 0x140 [disoef]. In this case, the field information follows the odd/even property of the input video signal. MICRONAS INTERMETALL ...

Page 25

... Hz), PAL 265 266 Input CVBS (60 Hz), NTSC HREF VREF FIELD Fig. 2–29: VREF timing for EVEN fields for VPX 3224E and VPX 3225E; for VPX 3226E: 2 lines additional delay due to 4H comb filter MICRONAS INTERMETALL 361 t CLK13 ...

Page 26

... The duration of the inactive pe- riod of the HREF is fixed to 64 clock cycles. Data End DataDelay + HLen for NPix 720 720 790 Data End DataDelay + 2*HLen for NPix 360 not possible! 790 n–1 data delay ADVANCE INFORMATION D n data end MICRONAS INTERMETALL ...

Page 27

... Fig. 2–31: Transition between timing standards MICRONAS INTERMETALL 2.10.2. Scan Mode In the Scan Mode, the HREF and VREF signals are al- ways generated by free running hardware. They are therefore completely decoupled from the analog input. The output video data is always suppressed. ...

Page 28

... VACT signal is suppressed 28 floats to steady state frequency of internal PLL track the input signal floats to steady state frequency of internal PLL track the input video immediately available immediately after color decoder locks to input. ADVANCE INFORMATION MICRONAS INTERMETALL ...

Page 29

... Window 2 # lines out Fig. 2–32: Vertical dimensions of windows MICRONAS INTERMETALL The option, to separately specify the number of input lines and the number of output lines, enables vertical compression. In the VPX, vertical compression is per- formed via simple line dropping. A nearest neighbor al- gorithm selects the subset of the lines for output. The presence of a valid line is signalled by the ‘ ...

Page 30

... Within valid video frames, each field type can be disabled separately. ADVANCE INFORMATION 1 314 2 315 3 316 4 317 335 23 336 24 337 25 338 308 621 309 622 623 310 624 311 625 312 Field 2 MICRONAS INTERMETALL ...

Page 31

... NTSC 10–21 VITC NTSC 10–21 CGMS NTSC 20 MICRONAS INTERMETALL 2.13.2. Data Broadcast Systems Table 2–10 gives an overview of the most popular data 2 C broadcast systems throughout the world. The data slicer of the VPX can be programmed to acquire the different data systems via a set of I The various data broadcast systems are specified by a limited set of parameters: – ...

Page 32

... The field bit can be used to identify field dependent services such as CAPTION. The 10-bit line number corresponds to the standard line counting scheme of a PAL composite video signal; in case of NTSC, the value “3” is subtracted. MICRONAS INTERMETALL ...

Page 33

... C1, C2 reference BB, BC, BD mask B8, B9, BA tolerance CE byte_cnt CF 64 byte mode CF dump mode CF adaption C7 soft error correction C7 MICRONAS INTERMETALL Table 2–11: Slicer Output Format Byte Byte Number Format 1 line number high 2 line number low 3 framing code 4 1st data byte . ... byte_cnt+2 last data byte ...

Page 34

... Fig. 2–38: Horizontal dimensions of the window for raw VBI-data 1138 1140 1137 1139 MICRONAS INTERMETALL ...

Page 35

... Figure 2–39 shows the timing of data and reference signals in this mode. Luminance (Port A) Chrominance (Port B) VACT PIXCLK LLC Fig. 2–39: Timing during lines with sliced VBI-data (single clock mode) MICRONAS INTERMETALL VPX 322xE Table 2–13: Splitting of sliced data to luminance and chrominance output Bit No. Word MSB ...

Page 36

... The second class of registers are the ‘FP-RAM regis- ters’, the memory of the internal microcontroller (MICRONAS INTERMETALL’s Fast Processor). Data written into this class of registers is read and interpreted by the FP’s micro-code. Internally, these registers are 12 bits wide ...

Page 37

... FPDAT Read from ACK FPRD ACK FPDAT MICRONAS INTERMETALL sub-addr ACK ACK rent transmission into a wait state called clock synchro- nization. After a certain period of time, the VPX releases the clock and the interrupted transmission is carried on ...

Page 38

... Tri-State active Tri-State active Tri-State active 13.5 MHz Tri-State active 27 MHz Tri-State active program- mable output 2 C and FP registers are preserved and FP regis register 0xAA) of low 2 C speeds above 100 kbit/sec are 2 C can be used up to the MICRONAS INTERMETALL ...

Page 39

... These include capture, shifting, and update. See Fig. 5–1 of IEEE 1149.1 for TAP state diagram. MICRONAS INTERMETALL VPX 322xE 2.17.2.2. Instruction Register The instruction register chooses which one of the data registers is placed between the TDI and TDO pins when the select data register state is entered in the TAP con- troller ...

Page 40

... Device Identification Register This is an optional 32-bit register which contains the MICRONAS INTERMETALL identification code (JE- DEC controlled), part and revision number. This is useful in providing the tester with assurance that the correct part and revision are inserted into a PCB. ...

Page 41

... The scan chain order is specified in the section “Pin Connections”. 2.17.4.6. Device Identification Register (Section 12.3.1.b.vi of IEEE 1149.1-1990) The manufacturer’s identification code for MICRONAS INTERMETALL is “6C” (hex) tion scheme uses only the 7 LSBs and excludes the MSB, which is the parity bit. The part numbers are de- fined in Table 6– ...

Page 42

... Update DR TMS=1 TMS=0 TMS=1 ADVANCE INFORMATION $ Capture Shift Exit1 IR $B Pause Exit2 Update IR TMS=0 MICRONAS INTERMETALL ...

Page 43

... Attribute Instruction_Length of VPXE_44: entity is 3; Attribute Instruction_Opcode of VPXE_44: entity is ”EXTEST (000),” & MICRONAS INTERMETALL VPX 322xE ––define ports ––map pins to signals ––define JTAG Controls ––max frequency and levels TCK can be stopped at. ––define instr. length – ...

Page 44

... Count ––MICRONAS INTERMETAL Code-Parity ––Mandatory LSB –-BC_1 for output cell ––BC_4 for input cell ––Boundary scan length ––Boundary scan defin. ...

Page 45

... Remark: EXTEST mode is an instruction conforming to the standard for Boundary Scan Test IEEE 1149.1 – 1990 MICRONAS INTERMETALL Control: The tristate condition of groups of signals can also be controlled by setting the I is neither in EXTEST mode nor RESET state, then the ...

Page 46

... Plastic Leaded Chip Carrier Package (PLCC44) Weight approximately 2.5 g Dimensions 1.75 13.2 0.2 2.15 Fig. 3–2: 44-Pin Plastic Metric Quad Flat Pack (PMQFP44) Weight approx. 0.4 g Dimensions 1.27 = 12.7 1.27 2 8.6 1.9 0.05 4.05 0.1 16.5 0.1 4. 0.1 0.06 0.8 2.0 0.1 10 0.1 0.1 0.2 SPGS0006-3(P44)/1E ADVANCE INFORMATION 0.1 1 0.1 SPGS0027-2(P44/K)/1E MICRONAS INTERMETALL ...

Page 47

... MICRONAS INTERMETALL Pin Type Connection Short Description (if not used Boundary-Scan-Test Data Input IN NC Boundary-Scan-Test Clock Input OUT NC Boundary-Scan-Test Data Output LLC / 2 = 13.5 MHz Output Active VBI Data Qualifier Output OUT NC Horizontal Reference Output ...

Page 48

... Supply Voltage, Analog Circuitry AIN NC Analog Chroma Input SUPPLY X Ground, Analog Circuitry AIN NC Analog Video 1 Input AIN NC Analog Video 2 Input Reference X Reference Voltage Top, Video ADC AIN NC Analog Video 3 Input SUPPLY X Signal Ground, Analog Video Inputs IN NC Boundary-Scan-Test Mode Select ADVANCE INFORMATION MICRONAS INTERMETALL ...

Page 49

... Pins 20 – Video Qualifier Output, VACT (Fig. 3–8) This pin delivers a signal which qualifies active video samples. MICRONAS INTERMETALL VPX 322xE Pins – Video, Port B[7:0] (Fig. 3–8) Video output port to deliver chroma data. In 8-bit modes Port B can be activated as programmable output (see section 2 ...

Page 50

... Top View LLC B2 VACT ADVANCE INFORMATION VIN1 AVSS CIN AVDD XTAL1 XTAL2 VDD VSS RES SCL SDA PVDD PIXCLK PVSS MICRONAS INTERMETALL ...

Page 51

... Pin VSS Fig. 3–6: TMS, TDI VDD Pin VSS 2 Fig. 3– Interface SDA, SCL The characteristics of the Schmitt Triggers depend on the supply of VDD/VSS. MICRONAS INTERMETALL VPX 322xE PVDD P OUT Pin N PVSS Fig. 3–8: A[7:0], B[7:0], HREF, VREF, LLC, PIXCLK, VACT, TDO VDD ...

Page 52

... Fig. 3–11: Reference Voltage VRT VIN1 N VIN2 To ADC1 N VIN3 N AVSS clamping Fig. 3–12: Video Inputs ADC1 52 VIN1 N CIN N Fig. 3–13: Video Inputs ADC2 AVDD VIN1, VIN2, VIN3, CIN Fig. 3–14: Unselected Video Inputs ADVANCE INFORMATION AVDD To ADC2 AVSS bias VRT off MICRONAS INTERMETALL ...

Page 53

... Functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute maxi- mum ratings conditions for extended periods may affect device reliability. MICRONAS INTERMETALL VPX 322xE Pin Min ...

Page 54

... ADVANCE INFORMATION Pin Min. Typ. Max. Name – 0 – 65 AVDD 4.75 5.0 5.25 VDD 3.15 3.3 3.45 PVDD 3.15 3.6 XTAL1/2 20.250 Pin Min. Typ. Max. Name VIN1, 0 – 3.5 VIN2, VIN3, CIN VIN1, 680 VIN2, VIN3 CIN 1 VIN1, 75 100 VIN2, VIN3, CIN MICRONAS INTERMETALL Unit MHz Unit ...

Page 55

... C-Data Hold Time after Falling I2C6 Edge of Clock 4.2.3. Recommended Digital Inputs Levels of RES, OE, TCK, TMS, TDI Symbol Parameter V Input Voltage LOW IL V Input Voltage HIGH IH V Input Voltage HIGH IH MICRONAS INTERMETALL VPX 322xE Pin Min. Typ. Max. Name SCL, 0.3 SDA SDA 0.6 SCL 100 SCL, ...

Page 56

... The higher the capacitors, the L ) with an effective load capacitance ADVANCE INFORMATION Max. Unit 65 C – MHz 20 ppm 30 ppm – 16 20.25 MHz. Due to p ICLoad = Leff ICLoad LoadBoard MICRONAS INTERMETALL ...

Page 57

... Slew-rate (see section 5.1. on page 63) t Reset Hold Time after Startup2 the Oscillator is active (see section 5.1. on page 63) k Duty Cycle XTAL MICRONAS INTERMETALL = 3. 20.25 MHz for min./max. values SUPD Pin Name Min. AVDD VDD PVDD application dependent – AVDD, VDD, PVDD AVDD, VDD, PVDD Min ...

Page 58

... V =1.5 V VIN VIN Coupling-Cap. @ Inputs –2 dBr input signal level 1 MHz, –2 dBr signal level 1 MHz, 5 harmonics, –2 dBr signal level 1 MHz, all outputs, –2 dBr signal level Code Density, DC-ramp DC ramp –12 dBr, 4.4 MHz signal on DC Ramp DC-Ramp MICRONAS INTERMETALL ...

Page 59

... Boundary-Scan Test, Characteristics of all IO pins which are connected to the boundary scan register chain t Input Signals Setup Time at CAPTURE-DR S-PINS t Input Signals Hold Time at CAPTURE-DR H-PINS t TCK to Output Signals, D-PINS Delay for Valid Data t Turn-on Delay ON-PINS t Turn-off Delay OFF-PINS MICRONAS INTERMETALL Pin Min. Typ. Max. Unit Name SDA, – – 0.4 V SCL 0.6 V SDA 15 ...

Page 60

... ADVANCE INFORMATION Unit Test Conditions while IC remains in low power mode Unit Test Conditions MICRONAS INTERMETALL ...

Page 61

... Fall Time FA I (0) Output High Current (strength = (0) Output Low Current (strength = (7) Output High Current (strength = (7) Output Low Current (strength = 7) OL MICRONAS INTERMETALL Min. Typ. Max. Unit Test Conditions ...

Page 62

... The buffers are enabled depending on the desired driver strength. This opportunity offers the ad- vantage of adapting the driver strength to on-chip and off-chip constraints, e.g. to minimize the noise result- ing from steep signal transitions ADVANCE INFORMATION MICRONAS INTERMETALL ...

Page 63

... OE determines the I dress. The FIELD pin is internally pulled down. An external pull- up resistor defines a different power on configuration. FIELD defines the global wake-up mode of the VPX. With FIELD pulled down, the VPX goes into low power mode. MICRONAS INTERMETALL 95% t STARTUP1 t RES MIN RES ...

Page 64

... VPX 322xE 5.3. Control Bus Timing Diagram (Data: MSB first) SCL T I2C1 SDA as input SDA as output 2 Fig. 5– bus timing diagram I2C4 I2C3 T T I2C5 I2C6 T T IMOL2 IMOL1 MICRONAS INTERMETALL ADVANCE INFORMATION T I2C2 ...

Page 65

... Output Enable by Pin OFF Signals A[7:0], B[7:0] Synchronizing the OE signal with clock LLC: 2 controlled register ’OENA’ h’f2 bit[5] oeqdel = latoeq = 0 Signals A[7:0], B[7:0] latoeq = 1 Signals A[7:0], B[7:0] Fig. 5–4: Drive Control by OE input MICRONAS INTERMETALL t OFF1 t OFF1 VPX 322xE ON1 t ON1 65 ...

Page 66

... Fig. 5–5: Timing of Test Access Port TAP 5.6. Timing of all Pins connected to the Boundary-Scan-Register-Chain TCK Inputs Outputs Fig. 5–6: Timing with respect to input and output signals 66 F CYCL F F L–TAP H-TAP t t S-TAP H-TAP t D-TAP t ON-TAP t t S-PINS H-PINS t D-PINS t ON-PINS ADVANCE INFORMATION t OFF-TAP t OFF-PINS MICRONAS INTERMETALL ...

Page 67

... ADVANCE INFORMATION 5.7. Timing Diagram of the Digital Video Interface Clock Output LLC A[7:0], B[7:0] HREF, VREF, FIELD, VACT Fig. 5–7: Video output interface (detailed timing) 5.7.1. Characteristics, Clock Signals LLC LLC2 PIXCLK Fig. 5–8: Clocks: LLC, LLC2, PIXCLK (detailed timing) MICRONAS INTERMETALL t LLC LLC t t ...

Page 68

... Default values are initialized at reset. The mnemonics used in the Intermetall VPX demo software is given in the last column C-Registers MICRONAS INTERMETALL Group Name Chip Ident. JEDEC Chip Ident. PARTNUM Chip Ident. JEDEC2 FP Interface ...

Page 69

... Number of Pixels h’130 12 w/r Selection for peaking / coring h’131 12 w/r Brightness h’132 12 w/r Contrast h’134 12 w/r Start line even field MICRONAS INTERMETALL FP-RAM Group Output Status Status Status Stand. Sel. Stand. Sel. Stand. Sel. Stand. Sel. Comb Filter Color Proc. Status Color Proc. Color Proc. Status Status Color Proc ...

Page 70

... ADVANCE INFORMATION FP-RAM Group VBI-window VBI-window VBI-window VBI-window VBI-window Formatter HVREF HVREF HVREF Output Mux. Temp. Decim. ASR ASR Macrovision Macrovision Macrovision MICRONAS INTERMETALL Name end_even start_odd end_odd vbicontrol slsize ControlWord InfoWord format_sel pval_start pval_stop refsig outmux tdecframes asr_enable asr_status mcv_status mcv_start ...

Page 71

... C-Registers VPX Back-End Address Number Mode Function Hex of Bits h’ Manufacture ID in accordance with JEDEC Solid State Products Engineering Council, Washington DC MICRONAS INTERMETALL Code EC 16 bit part number (01: LSBs, 02: MSBs) h’ VPX 3226E h’ VPX 3225E VPX 3224E h’03 ...

Page 72

... ADVANCE INFORMATION Default Name DRIVER_B strb1 strb2 OENA aen ben clken zen llc2en oeqdel latoeq oeq_dis LLC lowpow iresen llc2 llc2_pol slowpow oldllc bstatus MICRONAS INTERMETALL ...

Page 73

... MICRONAS INTERMETALL 2 I C-Registers VPX Slicer Sync Slicer (of Data Slicer only) binary sync slicer level is compared with binary data (0 data 127) 0 vertical sync window enable 1 vertical sync window disable reserved (must be read don’ ...

Page 74

... ADVANCE INFORMATION Default Name accu 0 reset 0 dcen 1 acen 0 soften 1 acaden 1 fltaden coeff_rd level_rd soft_cnt standard 1 ttx 0 ntsc 0 full 1 vps 1 wss 0 caption1 0 caption2 0 disquit h’55 reference h’55 h’27 h’00 mask h’00 h’00 tolerance out_mode 43 byte_cnt 1 fill64 0 dump MICRONAS INTERMETALL ...

Page 75

... Note: For correct operation, do not change FP registers 20h and 21h while ASR is enabled. h’15e 12 r Status of automatic standard recognition bit[0] bit[1] bit[2] bit[3] bit[4] bit[4:0] MICRONAS INTERMETALL FP-RAM VPX Front-End Standard Selection standard 0 PAL B,G,H,I (50 Hz) 4.433618 1 NTSC M (60 Hz) 3.579545 2 SECAM (50 Hz) 4 ...

Page 76

... DC rejection filter 0/1 disable/enable vertical peaking coring ADVANCE INFORMATION Default Name insel 00 vis 1 cis 00 ifc 10 cbw 0 fntch 0 lowp 3 hpllmd 0 sfif 0 ldly h’e7 comb_uc 3 nosel 1 ddr 2 hdg 3 vdg 0 vpk 0 misc_cmb_tst dcr cor MICRONAS INTERMETALL ...

Page 77

... MICRONAS INTERMETALL FP-RAM VPX Front-End Color Processing 0..4094 (2070 corresponds to 100% saturation) 4095 disabled (test mode only) DVCO 100 enable lock 0 disable lock ...

Page 78

... Hex of Bits h’170 12 r Status of macrovision detection bit[0]: bit[1]: h’171 12 w/r first line of macrovision detection window h’172 12 w/r last line of macrovision detection window 78 FP-RAM VPX Front-End Macrovision Detection AGC pulse detected pseudo sync detected ADVANCE INFORMATION Default Name mcv_status 6 mcv_start 15 mcv_stop MICRONAS INTERMETALL ...

Page 79

... Number of Pixels bit[10:0]: bit[11]: MICRONAS INTERMETALL FP-RAM VPX Back-End Read Table for Window #1 Delay of VACT relative to the trailing edge of HREF Vertical Begin (first active video line within a field) min. line number for 625/50 standards: 7 min. line number for 525/60 standards: 10 max ...

Page 80

... Contrast Brightness: Clamping Level 0 clamping level = 32, 1 clamping level = 16 Bypass Brightness Adder Bypass Contrast Multiplier reserved (must be set to zero) ADVANCE INFORMATION Default Name 0 peaking1 01 0 brightness1 lim16_1 32 contrast1 contr1 noise1 clamp1 bribyp1 conbyp1 MICRONAS INTERMETALL ...

Page 81

... Number of Pixels bit[10:0]: bit[11]: MICRONAS INTERMETALL FP-RAM VPX Back-End Read Table for Window #2 Delay of VACT relative to the trailing edge of HREF Vertical Begin (first active video line within a field) min. line number for 625/50 standards: 7 min. line number for 525/60 standards: 10 max ...

Page 82

... Contrast Brightness: Clamping Level 0 clamping level = 32, 1 clamping level = 16 Bypass Brightness Adder Bypass Contrast Multiplier reserved (must be set to zero) ADVANCE INFORMATION Default Name 0 peaking2 01 0 brightness2 lim16_2 32 contrast2 contr1 noise1 clamp1 bribyp1 conbyp1 MICRONAS INTERMETALL ...

Page 83

... Slicer Data Size (0 corresponds to default value 64) MICRONAS INTERMETALL FP-RAM VPX Back-End Load Table for VBI-Window VBI-window enable the selected VBI-window is activated only if this flag is set 0: disable 1: enable VBI mode two modes for the output of VBI-data are supported ...

Page 84

... Info Word reserved Sync timing mode 0: Open 1: Scan Mode for VACT reference signal 0 current window size 1 programmable size reserved ADVANCE INFORMATION Default Name Control- Word 0 settm 0 vactmode 0 1 latwin1 1 latwin2 0 disvact 0 disoef 0 1 lattdec 1 lattm InfoWord acttm acttm actvact MICRONAS INTERMETALL ...

Page 85

... Address Number Mode Function Hex of Bits h’150 12 w/r Format Selection bit[1:0]: bit[2]: bit[3]: bit[4]: bit[5]: bit[6]: bit[7]: bit[8]: bit[9]: bit[10]: bit[11]: MICRONAS INTERMETALL FP-RAM VPX Back-End Formatter Format Selector 00 4:2:2, ITU-R601 4:2:2, ITU-R656 4:2:2, BStream b r Shuffler 0 Port Port ...

Page 86

... VACT pin 1 connect ‘VBI active’ to TDO pin reserved (must be set to zero) Temporal Decimation ADVANCE INFORMATION Default Name 40 pval_start 720 pval_stop refsig 0 hpol 0 vpol 0 vlen 0 disfield 0 llcgate 0 outmux bmp bmpon double vbiact 3000 tdecframes MICRONAS INTERMETALL ...

Page 87

... LLC to assure a fixed number of clock cycles per line. – clock-synchronized bus arbitration via OE (optional) External – 3.3 V digital supply voltage MICRONAS INTERMETALL VPX 322xE 7.2. Differences between VPX 322xE and VPX 3220A The following items indicate the differences between the VPX 322xE and the VPX 3220A: ...

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... ADVANCE INFORMATION poll busy bit[2] until it is cleared write FP register write address poll busy bit[2] until it is cleared write data into FP register poll busy bit[2] until it is cleared write FP register read address poll busy bit[2] until it is cleared MICRONAS INTERMETALL ...

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... MSC1393 HC49U Fox Electronics S50927-1(HC49U, 20.25 MHz) S50927-2(SMD, 20.25 MHz) Millennium MCRY-1042-S low profile HC49/S ECLIPTEK Co. ECX-5053-20.250M low profile ECX-5087-20.250M normal profile MICRONAS INTERMETALL Country Phone/Fax Canada +1-(905) 623 4101 USA +1-(305) 593 6033 +1-(305) 594 3973 fax Germany ...

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J1 MINI DIN4 2.2uH S-Video 330pF L2 2.2uH C5 330pF RCA L3 Composite J2 Video 3.3uH C8 330pF RCA L4 C10 Composite J3 Video 3.3uH R4 680nF C11 C12 75 330pF 330pF Place the ...

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... ADVANCE INFORMATION MICRONAS INTERMETALL VPX 322xE 91 ...

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... Product availability and delivery dates are ex- clusively subject to our respective order confirmation form; the same applies to orders based on development samples deliv- ered. By this publication, MICRONAS INTERMETALL GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. ...

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