CS4922-CL Cirrus Logic, Inc., CS4922-CL Datasheet
CS4922-CL
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CS4922-CL Summary of contents
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... G.729A with a separate download image. The flexible architecture of the CS4922 provides the ability to mix compressed audio with data from the auxiliary PCM port. ORDERING INFORMATION CS4922-CL CDB4922 VD4 SCK/SCL SDA/CDOUT CDIN CS REQ Serial Control Port (SPI or I Port ...
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... Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com. 2 CS4922 2 C MODE) .............10 ...
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... Figure 15 Figure 16. Control Port Timing, SPI Write .......................................................... 21 Figure 17. Control Port Timing, SPI Read .......................................................... 22 Figure 18. CS4922 Suggested Layout ............................................................... 24 Figure 19. CS4922 Surface Mount Decoupling Layout ...................................... 25 Figure 20. DAC Frequency Response ................................................................ 26 Figure 21. DAC Phase Response ...................................................................... 26 Figure 22. DAC Transition Band ......................................................................... 26 Figure 23. DAC Passband Ripple ....................................................................... 26 Control Port Timing ................................................................... 11 2 ® ...
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... Typ Max DNL - - 0.9 - 0.01 0.015 0.02 0.03 IDR 0.2 -3.0 - +0.2 2.66 2.88 3.2 2.7 3.0 3.3 - 100 - - - 100 - 100 140 (See Figures 20 through 23) Min Typ Max 0 - 0.476Fs - - 0.1 0.442Fs - 0.567Fs 0.567Fs - - 12/Fs - CS4922 Units Bits LSB % Vpp ppm/°C Deg Units ...
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... IND T Amax T stg (AGND, DGND = 0V; all voltages with respect Symbol VD+ Positive Digital VA+ Positive Analog | | VA VD VA+, VD 10%; measurements performed under A Symbol (Note 2) in CS4922 Min Max -0.3 6.0 -0.3 6 -0.3 (VD+) + 0.4 -55 125 -65 150 Min Typ Max 4.50 5.0 5.50 4.50 5 Min ...
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... C; VA+, VD+ = 5V; Inputs: Logic Symbol CLKIN CYCK CLKOUT = 20pF) L Symbol t (Note 3) rxf t fxf = 20pF) L Symbol f pio t rpio t fpio t rpo t fpo CS4922 Min Typ Max Units 27 MHz 256 Fs MHz ( VA+, VD+ = 5V; A Min Typ Max Units 200 ns 100 ...
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... csh (SPI) CS SCK/SCL = 20pF) L Symbol t bsu (Note 4) cssu t csh t rlow t (Note 5) rsc t sfcr 2 t rsc Figure 1. Boot Timing CS4922 ( VA+, VD Min Max Units 350 - ns 450 - ns 200 - ns 400 - SPI mode. t sfcr ...
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... CS4922 ( Symbol Min Max Units f - 350 kHz sck f - 2000 sck t ...
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... CS t css SCK/SCL CDIN CDOUT REQ SCK/SCL CDIN CDOUT t rh REQ t scrh t scl t sch A5 t cdisu t cdih t sccsh t csht 7 LSB LSB tri-state t cscdo t scrl Figure 2. SPI Control Port Timing CS4922 A0 R/W MSB MSB t scdov A6 t scdov 9 ...
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... START condition 20pF) L Symbol (Note 10) (slow mode) (fast mode) slow fast slow fast (Note 11) (Note 12) (Note 13) (Note 14) (Note 13) (Note 14 specifications recommend, please refer to the section on SCP CS4922 2 C MODE Min Max Units f 100 kHz scl 400 t 4.7 s buf t 4.0 ...
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... SCK/SCL t hdst REQ cssta SDA 7 SCK/SCL REQ t scrh sud low t hdd t high t r LSB ACK 8 t scrl susp 2 ® Figure Control Port Timing A0 ACK R/W t scsdv sca stop t cssto CS4922 MSB 0 11 ...
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... EDG bit in the ASICN register. The diagram is for EDG = 1. FSYNC SCLK SDATA pF) L Symbol (Note 15) (Note 15) (Note 15) (Note 15) t sfs t sfds t t sckl t t sss ssh t sclr Figure 4. Serial Audio Port Timing CS4922 ( VA+, VD Min Typ Max - - 12 sckl sckh sfds t ...
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... Notes: 16. Fs determined by clock input rate and configuration of on-chip PLL. 17. AUXCLK frequency selectable @ 32, 64, or 128 Fs via AUXCN register bits 1:0. AUXCLK AUXLR AUXOUT AUXIN Symbol (Note 16) (Note 17 sclk T lrun T doun T T disu diho Figure 5. Auxiliary Audio Port Timing CS4922 Min Typ Max tsclk - 1/(32Fs) - 1/(64Fs) 1/(128Fs) tlrun tdoun 0 - ...
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... REQ 2 SCK/SCL 4 SDA/CDOUT 1 CDIN RESET 40 BOOT 24 CLKOUT 30 PIO 10k 27 CLKIN 28 ALTCLK DGND1 DGND4 Figure 6. Typical Connection Diagram CS4922 34 VA+ > 1.0 F 600 + 38 AOUTL 0.0022 F NPO > 1.0 F 600 + 39 AOUTR 0.0022 F NPO > 1.0 F 600 + 37 AOUTM 0.0022 F NPO 8 AUXOUT 9 AUXIN SERIAL 10 CODEC ...
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... THEORY OF OPERATION 3.1 Introduction The CS4922 is a complete audio subsystem on a chip. It consists of a general-purpose Digital Signal Processor (DSP), and a number of supplementary analog and digital blocks. These supplementary blocks include a PLL clock multiplier, a serial au- dio input port, an auxiliary serial audio port ...
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... The total quantization noise and thermal noise from the analog filters integrated over the .417Fs to 128Fs (192Fs) is more than 50 dB below full scale power. Interpolation Modulator Filter Interpolation Modulator Filter Figure 8. DAC CS4922 Switched Capacitor AOUTL Filter Switched Capacitor AOUTR Filter ...
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... Auxiliary Digital Audio Port The CS4922 auxiliary port provides a path for the internal DSP core to directly read and write framed PCM digital audio data. The auxiliary port is de- signed to operate in a full duplex mode that can support simultaneous PCM input and output ...
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... However, I bus protocol is still required. In other words, the ad- dress bits and read/write bit are still required write to the CS4922 is specified, 8 bits of data on SDA will be shifted into the input shift register as shown in Figure 13. When the shift register is full, ...
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... If the second attempt fails the CS4922 should be issued a hardware reset to reinitialize the communication path. If the DSP core of the CS4922 wants to send a byte to the master, it first writes the byte to the Serial Control Port Output (SCPOUT) register. A write to the SCPOUT sets the request pin (REQ) active The master must recognize the request and issue a read operation to the DSP ...
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... The Philips I times of the SCL/SCK line The CS4922 does not meet this specification. If the I ter(s) has a rise time in excess the CS4922 will be unable to reliably communicate across the bus. In some systems a stronger pull-up resistor on the SCL/SCK line will provide the rise time needed for proper operation, but this is only helpful when the current rise time is near 50 ns ...
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... Serial Con- trol Port Input (SCPIN) register on the falling edge of the 8th data bit. If the DSP core of the CS4922 wants to send a byte to the master, it first writes the byte to the Serial Control Port Output (SCPOUT) register. A write to the SCPOUT sets the request pin (REQ) active low ...
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... CS4922. The MPEG application, for example, uses XF1 as a compressed data throttle indicator. When the XF1 pin is low, the host may continue to send com- pressed data to the CS4922. When XF1 is high, the AD6 AD5 AD4 AD3 ...
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... Please see the documentation for the application code being used in your system for a complete de- scription. 5 BOOT PROCEDURE The CS4922 is a RAM based audio decoder. Con- sequently, program and data RAM must be loaded from external memory after power up or any other time a new program needs to be downloaded. Dur- ...
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... Figures 18 and 19. The analog and digital grounds on the CS4922 are not connected internally; this should be accom- plished externally through a point-to-point connec- tion across the ground split as shown in Figure 18 ...
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... Figure 19. CS4922 Surface Mount Decoupling Layout CS4922 25 ...
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... DAC FILTER RESPONSE PLOTS Figures 20 through 23 show the overall frequency response, passband ripple and transition band for the CS4922 DACs. Figure 23 shows the DACs’ de- Figure 20. DAC Frequency Response Figure 22. DAC Transition Band 26 viation from linear phase the selected sample frequency ...
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... Analog power supply ground CS4922 11 35 top 12 34 view CS4922 CS VD4 DGND4 RESET BOOT AOUTR AOUTL AOUTM AGND2 NC VA+ AGND1 NC FLT PIO EXTCK ALTCLK CLKIN DGND3 VD3 CLKOUT FSYNC 27 ...
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... SCLK is used to clock the serial audio data on SDATA into the device. The active edge of SCLK is determined by the application code running on the CS4922. SDATA - Serial Audio Data Input, PIN 21. SDATA is an audio data input pin for the CS4922. The data is clocked in on the active edge of SCLK. Digital Audio Transmitter TX - Transmitter Output, PIN 5 ...
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... It is required that a pull-up be used (typically 2 pin 13. RESET - PIN 41. The CS4922 enters a reset state while RESET is low. When in reset condition, all internal registers are set to 0, the digital audio transmitter, serial control port, and ALTCLK pin are disabled, and the stereo DAC is muted. Normal operation is resumed one internal clock cycle after the rising edge of RESET ...
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... CDIN - Control Data Input, PIN 1. In SPI mode, CDIN is the data input for the serial control port. It has no function in I The pin should be connected to either digital power or ground when the CS4922 is used in I systems. Auxiliary Digital Audio Port AUXLR - Auxiliary Sample Clock, PIN 10. ...
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... Worst case variation in output signal level versus frequency over kHz. Units in dB. Out of Band Energy The ratio of the rms sum of the energy from 0. 2.1 Fs compared to the rms full-scale signal value. Tested with 48 kHz Fs giving a out-of-band energy range of 22 kHz to 100 kHz. CS4922 31 ...
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... JEDEC # : MS-018 CS4922 e D2/ MILLIMETERS MIN MAX 4.572 3.048 0.533 17.653 16.662 16.002 17.653 16.662 16.002 1.524 ...
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Notes • ...
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