CS61304A-IL1 Cirrus Logic, Inc., CS61304A-IL1 Datasheet
CS61304A-IL1
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CS61304A-IL1 Summary of contents
Page 1
... ISDN PRI applications. The transmitter features inter- nal pulse shaping and a low impedance output stage allowing the use of external resistors for transmitter im- pedance matching. Applications Primary Rate ISDN Network/Termination Equipment Channel Service Units ORDERING INFORMATION CS61304A-IP1 CS61304A-IL1 (CLKE) MODE TAOS CONTROL ...
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... TV+, RV+ = 5.0V 5%; GND = 0V) Symbol Min (Notes 2.0 IH (Notes (Notes 2.4 OH (Notes (RV+) - 0.2 IH (Note OUT CS61304A Min Max Units - 6 (RV+) + 0.3 V (RV+) + 0 -65 150 C Typ Max Units 5.0 5. ...
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... ABS((z +z )/( where series resistors terminated resistor across the secondary of the transmitter transformer CS61304A Min Typ Max 2.14 2.37 2.6 2.7 3.0 3.3 2.7 3.0 3.3 2.4 3.0 3.6 -0.237 - 0.237 -0 ...
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... 1.2 V and from 4. 3 CS61304A Typ Max 50k - - - - - peak peak peak 175 190 - - - - - - 0.30 0. RV+ ...
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... CS61304A Typ Max Units 6.176000 - MHz 1.544 - MHz - 500 1.544 - MHz ...
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... RPOS RNEG RDATA BPV RCLK Figure 2. Recovered Clock and Data Switching Characteristics 6 ( TV+, RV+ = 5%; Symbol (Note 33 90% 10% Figure 1. Signal Rise and Fall Characteristics t pw1 t pwl1 t pwh1 t t su1 h1 CS61304A Min Typ Max cdh t 240 - cl t 240 - ch t ...
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... Figure 3b. Alternate External Clock Characteristics cdh LSB BYTE DATA Figure 4. Serial Port Write Timing Diagram cdv Figure 5. Serial Port Read Timing Diagram PCS t su4 VALID INPUT DATA CS61304A t pw3 t pwh3 ACLKI t cch t cdh MSB BYTE t cdz HIGH pcsl ...
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... THEORY OF OPERATION Key Enhancements of the CS61304A Relative to the LXT304A 12.5% Lower Power Consumption transmitter short-circuit current RMS limiting for E1 (per OFTEL OTR-001), Optional AMI, B8ZS, HDB3 encoder/de- coder or external line coding support, Receiver AIS (unframed all ones) detection, Improved receiver Loss of Signal handling ...
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... AMI CS61304A AIS JITTER DETECT ATTENUATOR AIS HOST MODE CLKE CONTROL LINE DRIVER CS61304A DRIVER MONITOR JITTER LINE RECEIVER ATTENUATOR Figure 7. Overview of Operating Modes CS61304A LEN0/1/2 TTIP TRANSMIT TRING TRANSFORMER MRING MTIP DPM RTIP RECEIVE RRING TRANSFORMER LEN0/1/2 TTIP TRANSMIT TRING ...
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... OFTEL OTR-001 short-circuit current limiting require- ments for E1 applications. The CS61304A will detect a static TCLK, and will force TTIP and TRING low to prevent trans- mission when data is not present. When any transmit control pin (TAOS, LEN0-2 or LLOOP) is toggled, the transmitter outputs will require ap- proximately 22 bit periods to stabilize ...
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... The out abl transformer specified in Application Section. 2. 0.237 V Table 4. CCITT G.703 Specifications CS61304A For shielded twisted a nd pair, 120 load and transformer specified in Application Section 0.30 V 244 ns 0 ...
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... RCLK, the recovered clock. In the Extended Hardware Mode, data at RDATA should be sampled on the falling edge of RCLK. In the Host Mode, CLKE determines the clock polarity for which output data should be sampled as shown in Table 5. CS61304A RPOS Jitter RNEG Attenuator RCLK ...
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... The jitter attenuator ex- ceeds the jitter attenuation requirements of Publications 43802 and REC. G.742. A typical jitter attenuation curve is shown in Figure 12. The CS61304A fully meets AT&T 62411 jitter attenu- ation requirements ...
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... Notes Don’t Care. The identified All Ones Select input is ignored when the indicated loopback is in effect. 2. Logic 1 indicates that Loopback or All Ones option is selected. Table 7. Interaction of RLOOP with TAOS CS61304A Source of Clock for TTIP & TRING TCLK TCLK DS156PP2 ...
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... The reference clock for the re- ceiver is provided by the crystal oscillator, or ACLKI if the oscillator is disabled. The reference clock for the transmitter is provided by TCLK. The initial calibration should take less than 20 ms. CS61304A LEN 2/1/0 000 010-111 B8ZS Encoder AMI Encoder ...
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... The line interface responds to address 16 (0010000). The last bit is ignored. LSB, first bit MSB, last bit Figure 13. Input/Output Timing CS61304A 0 R/W Read/Write Select write read 1 ADD0 LSB of address, Must ADD1 Must ADD2 Must ADD3 Must be 0 ...
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... RLOOP in effect DPM changed state since last "clear DPM" occured LOS changed state since last "clear LOS" occured LOS and DPM have changed state since last "clear LOS" and "clear DPM". Table 12. Coding for Serial Output bits 5,6,7 CS61304A 17 ...
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... RV+/RGND supply. Wire-wrap bread- boarding of the line interface is not recommended because lead resistance and inductance serve to defeat the function of the decoupling capacitors. 18 CS61304A Schematic & Layout Review Service Confirm Optimum Schematic & Layout Before Building Your Board. For Our Free Review Service Call Applications Engineering ...
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... TGND 14 15 TCLK TPOS top 8 view DPM LOS TTIP CS61304A TAOS LLOOP RLOOP LEN2 LEN1 LEN0 RGND RV+ RRING RTIP MRING MTIP TRING TV+ TAOS LLOOP RLOOP LEN2 26 25 LEN1 24 LEN0 23 22 RGND 21 RV ...
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... TGND 14 15 TCLK BPV top 8 view AIS LOS TTIP CS61304A TAOS LLOOP RLOOP LEN2 LEN1 LEN0 RGND RV+ RRING RTIP PCS RCODE TRING TV+ TAOS LLOOP RLOOP LEN2 26 25 LEN1 24 LEN0 23 22 RGND 21 RV ...
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... TGND 14 15 TCLK TPOS top 8 view DPM LOS TTIP CS61304A CLKE SCLK CS SDO SDI INT RGND RV+ RRING RTIP MRING MTIP TRING TV+ CLKE SCLK CS SDO 26 25 SDI 24 INT 23 22 RGND 21 RV RRING ...
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... INT - Receive Alarm Interrupt, Pin 23. (Host Mode) Goes low when LOS or DPM change state to flag the host processor. INT is cleared by writing "clear LOS" or "clear DPM" to the register. INT is an open drain output and should be tied to the power supply through a resistor. 22 CS61304A DS156PP2 ...
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... Status and control information from the on-chip register. If CLKE is high SDO is valid on the rising edge of SCLK. If CLKE is low SDO is valid on the falling edge of SCLK. This pin goes to a high-impedance state when the serial port is being written to or after bit D7 is output. DS156PP2 CS61304A 23 ...
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... Inputs for clock and data to be transmitted. The signal is driven on to the line through TTIP and TRING. TPOS and TNEG are sampled on the falling edge of TCLK. A TPOS input causes a positive pulse to be transmitted, while a TNEG input causes a negative pulse to be transmitted. 24 CS61304A DS156PP2 ...
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... These pins are normally connected to TTIP and TRING and monitor the output of a line interface IC. If the INT pin in the Host mode is used, and the monitor is not used, writing the "clear DPM" bit will prevent an interrupt from the driver performance monitor. DS156PP2 CS61304A 25 ...
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... DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH. B D2/ pin E1 Plastic DIP 28-pin PLCC E E1 DIM MIN A 4.20 A1 2.29 B 0.33 D/E 12.32 D1/E1 11.43 D1 D2/E2 9. CS61304A MILLIMETERS DIM MIN NOM MAX MIN 3.94 4.32 5.08 0.155 A A1 0.51 0.76 1.02 0.020 B 0.36 0.46 0.56 0.014 B1 1.02 1.27 1.65 0.040 C 0.20 0.25 0.38 0.008 36.45 36.83 D 37.21 1.435 E1 13.72 13.97 14 ...
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... Cable R1 and R2 LEN2/1/0 100 200 0/1/1 - 1/1/1 120 240 0/0/0 0/0/0 0/0/1 0/0/1 75 150 0/0/0 0/0/0 0/0/1 0/0/1 Table A1. External Component Values the Host Mode. Figure A2 illustrates a 120 interface in the Hardware Mode. Figure A3 illus- trates a 75 Hardware Mode. CS61304A F +5V 100 Serial 24 Port RECEIVE LINE ...
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... IN LOS 11 EXTENDED AIS HARDWARE 5 MODE MODE 4 RRING TCODE 7 RDATA 8 RCLK 3 TDATA TRING 2 TCLK TTIP 9 XTALIN 10 XTALOUT RGND TGND Extended Hardware Mode Configuration CS61304A 23 Line 24 Length 25 Setting RECEIVE 6 LINE 2CT:1 PE-65351 TRANSMIT LINE 1:1.26 ...
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... Transformers Recommended transmitter and receiver trans- former specifications are shown in Table A2. The transformers in Table A3 are recommended for use with the CS61304A. Refer to the "Telecom Transformer Selection Guide" for detailed sche- matics which show how to connect the line interface IC with a particular transformer. ...
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... If the line interface is used in Hardware Mode, then the line interface RCLK output must be inverted be- fore being input to the CS62180B. If the CS61304A is used in Extended Hardware Mode, the RCLK output does not have to be inverted be- fore being input to the CS62180B. 30 ...
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... ORDERING INFORMATION: CDB61534, CDB6158, CDB61574A, CDB61575, CDB61304A, CDB61305A +5V 0V Reset Circuit CS61534, CS61535, CS61535A, CS6158, CS6158A, CS61574, CS61574A, CS61575, CS61577, CS61304A or CS61305A coax E1, or 120 twisted-pair E1 operation. CDB61535. CDB61535A, CDB6158A, CDB61574, CDB61577, TTIP TRING RTIP RRING XTL twisted-pair SEP ’95 DS40DB3 31 ...
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... Mode selection is accomplished with slide switch SW1 and jump- ers JP2, JP6, and JP7. The CS61535A, CS61574A, CS61575, CS61577, CS61304A, and CS61305A support the Hardware, Extended Hardware, and Host operating modes. The CS61534, CS61535, and CS61574 support the Hardware and Host operating modes ...
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... LOS applications with the CS61534, 12 CS61535, CS6158, CS61574, RV+ RV+ OR CS61577) LOS Q2 Q1 2N2222 2N2222 U1: CS61534, CS61535, LED LED CS61535A, CS6158 CS6158A, CS61574, CS61574A, CS61575 470 470 CS61577, CS61304A, OR CS61305A RV+ T2 RTIP 2:1 RRING TTIP JP5 (see Table 2) TRING 33 ...
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Performance Monitor alarm. The LED labeled LOS illuminates when the line interface receiver has detected a loss of signal. Extended Hardware Mode In the Extended Hardware operating mode, the line interface is configured using DIP switch S2. The digital control ...
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The evaluation board supports 100 T1, 75 coax E1, and 120 eration. The CDB61534, CDB61535, CDB6158, CDB61574, and CDB61577 are supplied from the factory with a 1:2 transmit transformer that may be used for all T1 and E1 applications. The ...
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A letter at the intersection of a row and column in Table 2 indicates that the selected transformer is supported for use with the device. The transformer is installed in the evaluation board with pin 1 positioned to match ...
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TRANSFORMER 1,2 (Turns Ratio) PE-65351 (1:2CT) Schott 12930 (1:2CT) PE-65388 (1:1.15) Schott 12931 (1:1.15) PE-65389 (1:1:1.26) Schott 12932 (1:1:1.26) PE-64951 (dual 1:2CT) Schott 11509 (dual 1:2CT) PE-65565 (dual 1:1.15 & 1:2CT) Schott 12531 (dual 1:1.15 & 1:2CT) PE-65566 (dual 1:1:1.26 ...
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LINE INTERFACE EVALUATION BOARD Figure 2. Silk Screen Layer (NOT TO SCALE) DS40DB3 ...
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Figure 3. Top Ground Plane Layer (NOT TO SCALE) DS40DB3 LINE INTERFACE EVALUATION BOARD 39 ...
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LINE INTERFACE EVALUATION BOARD Figure 4. Bottom Trace Layer (NOT TO SCALE) DS40DB3 ...
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Notes • ...
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Notes • ...
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Notes • ...
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TM Smart Analog is a Trademark of Crystal Semiconductor Corporation ...