PACS1284 California Micro Devices Corporation, PACS1284 Datasheet

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PACS1284

Manufacturer Part Number
PACS1284
Description
Manufacturer
California Micro Devices Corporation
Datasheet

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06/07/04
Features
Applications
© 2004 California Micro Devices Corp. All rights reserved.
Electrical Schematic
R1
C
Single chip IEEE 1284 parallel port termination
28-pin QSOP package, smallest physical
solution
17 terminating lines in a single package
In-system ESD protection to
In-system ESD protection to
IEC 61000-4-2
Protects downstream devices to 30V
Lead-free version available
ECP/EPP Parallel Port termination
PC Peripherals
Notebook and Desktop computers
Engineering Workstations and Servers
1
28
430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214
R3
C
R1
C
2
27
R1
C
26
R1
C
IEEE 1284 ECP/EPP Termination Network
R2
3
25
R1
C
±
±
8KV, HBM
4KV per
R2
4
24
R1
C
R2
5
23
R1
C
R2
22
6
21
PACS1284-02:
R1
C
R2
Product Description
California Micro Devices’ PACS1284 Parallel Port Ter-
mination Network provides a complete integrated solu-
tion for the entire IEEE 1284 interface in a single
QSOP package.
To support the bi-directional transfer data rates of
enhanced high-speed parallel ports, the IEEE 1284
Standard recommends a combined termination/pull-up
filter network between the driver/receiver and the cable
at both ends of the parallel port interface. In addition,
government EMC compatibility requirements impose
strict filtering requirements on the parallel port. The
California Micro Devices PACS1284 addresses all
these requirements by providing a seventeen-line IEEE
1284-compliant network in a thin film integrated circuit.
The device provides a complete parallel port termina-
tion solution for space critical applications by integrat-
ing a total of 60 discrete components. In addition, all
the I/O pins are ESD protected for contact discharges
up to
output pins having the highest probability of ESD pulse
exposure protected to
the necessary robustness for the port’s application
environment.
The PACS1284 is manufactured in a 28-pin QSOP
package and is available with optional lead-free finish-
ing.
7
20
R3
C
±
8
4KV per the Human Body Model (HBM), with the
19
R1 = 2.2kΩ
R2 = 33Ω
R3 = 2.2kΩ
C = 220pF
R1
▲ Fax: 408.263.7846
C
R2
9
R3
C
10
18
PACS1284-04:
R1
±
C
8KV (HBM), thereby providing
R2
11
R3
C
12
www.calmicro.com
R1 = 4.7kΩ
R2 = 33Ω
C = 180pF
R3 = 4.7kΩ
17
R1
C
PACS1284
R2
13
16
R1
C
R2
14
15
R3
C
1

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PACS1284 Summary of contents

Page 1

... I/O pins are ESD protected for contact discharges ± output pins having the highest probability of ESD pulse exposure protected to the necessary robustness for the port’s application environment. The PACS1284 is manufactured in a 28-pin QSOP package and is available with optional lead-free finish- ing. PACS1284-02 ...

Page 2

... CONNECTOR SIDE SERIES-TERMINATED GND CONNECTOR SIDE SERIES-TERMINATED V CC CONNECTOR SIDE SERIES-TERMINATED CONNECTOR SIDE SERIES-TERMINATED CONNECTOR SIDE SERIES-TERMINATED CONNECTOR SIDE SERIES-TERMINATED CAP-FILTERED; R3 PULL-UP R3 (Ω) 2.2k 4.7k Lead-free Finish Ordering Part 1 Number PACS1284-02QR PACS128402QR PACS1284-04QR PACS128404QR ▲ Fax: 408.263.7846 ▲ www.calmicro.com C (pF) 220 180 Part Marking 06/07/04 ...

Page 3

... Per IEC 61000-4-2 Level 2; C =150pF; R Discharge Discharge Notes 2,3 ESD applied to connector pin, mea- sured at corresponding input pin; +8kV discharge, Human Body Model Note 2 pin 20=5V; pin 22=GND ▲ Tel: 408.263.3214 PACS1284 RATING 6.0 -6.0 to 6.0 -65 to +150 100 1.00 RATING 5 +70 (SEE NOTE 1) MIN TYP =25° ...

Page 4

... Figure 1. Typical Filter Insertion Loss for PACS1284 (S © 2004 California Micro Devices Corp. All rights reserved. 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 ▲ Tel: 408.263.3214 4 The three plotted lines in measurements: • Line labeled "A" is measured between pin 14 (input) and pin 16 (output). • ...

Page 5

... Connector Host 14 1 PACS1284 SUPER 1284 1 Figure 2. Example Connections of IEEE 1284 Connectors with PACS1284 © 2004 California Micro Devices Corp. All rights reserved. 430 N. McCarthy Blvd., Milpitas, CA 95035-5112 06/07/04 Interfacing to IEEE 1284 Connectors IEEE 1284 defines three interface connectors: • 1284 25-pin DB series connector which is the de facto PC standard for the host connection. • ...

Page 6

... PACS1284 pin con- nections. When connecting a 1284-A host to a 1284-B periph- eral, the “Peripheral Logic High” signal is not used. Table 2: IEEE 1284 Connector Pinouts and PACS1284 Connection Guidelines PACS1284 PIN TYPE P-Port conn. side, series-terminated (16-19, 21, or 23-26) P-Port conn ...

Page 7

... Mechanical Details QSOP Mechanical Specifications: PACS1284 devices are packaged in 28-pin QSOP packages. Dimensions are presented below. For complete information on the QSOP-28 package, see the California Micro Devices QSOP Package Infor- mation document. PACKAGE DIMENSIONS Package QSOP (JEDEC name is SSOP) Pins Millimeters ...

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