LPC47M102S-MC Standard Microsystems, LPC47M102S-MC Datasheet
LPC47M102S-MC
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LPC47M102S-MC Summary of contents
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Pin Enhanced Super I/O Controller with LPC Interface for Consumer Applications • 3.3 Volt Operation (5 Volt Tolerant) • LPC Interface • ACPI 1.0 Compliant • Fan Control - Fan Speed Control Outputs - Fan Tachometer Inputs • Programmable ...
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... LPC47M102S-MC for AMI BIOS in 100 pin QFP package (leaded) LPC47M102S-MS for AMI BIOS in 100 pin QFP lead-free RoHS compliant package LPC47M107S-MC for Phoenix BIOS in 100 pin QFP package (leaded) LPC47M107S-MS for Phoenix BIOS in 100 pin QFP lead-free RoHS compliant package The LPC47M10x 3.3V (5V tolerant) PC98/PC99 compliant Super I/O controller. The LPC47M10x implements the LPC interface, a pin reduced ISA bus interface which provides the same or better performance as the ISA/X-bus with a substantial savings in pins used ...
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FEATURES..................................................................................................................................................................1 ORDERING INFORMATION ....................................................................................................................................2 GENERAL DESCRIPTION .......................................................................................................................................2 PIN CONFIGURATION.............................................................................................................................................5 DESCRIPTION OF PIN FUNCTIONS..................................................................................................................... UFFER YPE ESCRIPTIONS ................................................................................................................................. INS HAT EQUIRE XTERNAL BLOCK DIAGRAM...................................................................................................................................................12 REFERENCE DOCUMENTS..................................................................................................................................12 3 VOLT OPERATION / 5 VOLT TOLERANCE ...
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PARALLEL PORT....................................................................................................................................................72 IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES ..................................................................73 EXTENDED CAPABILITIES PARALLEL PORT.................................................................................................78 POWER MANAGEMENT........................................................................................................................................88 SERIAL IRQ..............................................................................................................................................................91 TIMING DIAGRAMS FOR SER_IRQ CYCLE ....................................................................................................91 8042 KEYBOARD CONTROLLER DESCRIPTION ........................................................................................... ATCHES N EYBOARD AND OUSE K M ...
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PIN CONFIGURATION GP40/DRVDEN0 1 GP41/DRVDEN1 2 nMTR0 3 nDSKCHG 4 nDS0 5 CLKI32 6 VSS 7 nDIR 8 nSTEP 9 nWDATA 10 nWGATE 11 nHDSEL 12 nINDEX 13 LPC47M10x nTRK0 14 nWRTPRT 15 nRDATA 16 100 PIN QFP GP42/nIO_PME 17 ...
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DESCRIPTION OF PIN FUNCTIONS PIN No./ QFP NAME TOTAL PROCESSOR/HOST LPC INTERFACE (10) 23:20 Multiplexed Command, Address, Data [3:0] 24 Frame 25 Encoded DMA Request 26 PCI Reset 27 Power Down 29 PCI Clock 30 Serial IRQ 6 32.768 Trickle ...
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DESCRIPTION OF PIN FUNCTIONS PIN No./ QFP NAME TOTAL 3 Motor Write Protected 14 Track 0 13 Index Pulse Input 1 General Purpose I/O/Drive Density Select 0 2 General Purpose I/O/Drive Density Select 1 SERIAL PORT 1 ...
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DESCRIPTION OF PIN FUNCTIONS PIN No./ QFP NAME TOTAL 73 Port Data 5 74 Port Data 6 75 Port Data 7 77 Printer Selected Status 78 Paper End 79 Busy 80 Acknowledge 81 Error 82 Autofeed Output 83 Strobe Output ...
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PIN No./ QFP NAME 47 General Purpose I/O /MIDI_OUT 50 General Purpose I/O /SMI Output 48 General Purpose I/O / LED 49 General Purpose I/O / LED 17 General Purpose I/O / Power Management Event 28 General Purpose I/O /Device ...
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Buffer Type Descriptions Note: The buffer type values are specified at VCC=3.3V IO12 Input/Output, 12mA sink, 6mA source. IS/O12 Input with Schmitt Trigger/Output, 12mA sink, 6mA source. O12 Output, 12mA sink, 6mA source. OD12 Open Drain Output, 12mA sink. O6 ...
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Pins That Require External Pullup Resistors The following pins require external pullup resistors: • KDAT • KCLK • MDAT • MCLK • GP36/KBDRST if KBDRST function is used • GP37/A20M if A20M function is used • GP20/P17 If P17 function ...
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SMI SER_IRQ SERIAL IRQ PCI_CLK LPC Bus LPC BUS Signals INTERFACE CLOCK GEN V Vcc Vss TR CLK32 CLOCKI 32KHz 14MHz FIGURE 1 – LPC47M10x BLOCK DIAGRAM REFERENCE DOCUMENTS 1. SMSC Consumer Infrared Communications Controller (CIrCC) V1.X 2. IEEE ...
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VOLT OPERATION / 5 VOLT TOLERANCE The LPC47M10x is a 3.3 Volt part intended solely for 3.3V applications. Non-LPC bus pins are 5V tolerant; that is, the input voltage is 5.5V max, and the I/O buffer output ...
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Indication of 32kHz Clock There is a bit to indicate whether or not the 32kHz clock input is connected to the LPC47M10x. This bit is located at bit 0 of the CLOCKI32 register at 0xF0 in Logical Device A. This ...
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All GPIOs listed above are for PME wakeup as a GPIO (or alternate function). Note that GP32 and GP33 cannot be used for wakeup under VTR power (VCC=0) since these are the fan control pins which come up as outputs ...
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The maximum VCC current given with all outputs open (not loaded) and all inputs in a fixed state (i.e 3.3V). The maximum VREF current given with all outputs open (not loaded) ...
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LPC INTERFACE The following sub-sections specify the implementation of the LPC bus. LPC Interface Signal Definition The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI 33MHz electrical signal characteristics. SIGNAL ...
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I/O Read and Write Cycles The LPC47M10x is the target for I/O cycles. I/O cycles are initiated by the host for register or FIFO accesses, and will generally have minimal Sync times. The minimum number of wait-states between bytes is ...
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POWER MANAGEMENT CLOCKRUN Protocol The nCLKRUN pin is not implemented in the LPC47M10x. See the Low Pin Count (LPC) Interface Specification Section. LPCPD Protocol See the Low Pin Count (LPC) Interface Specification Section. SYNC Protocol See the Low Pin Count ...
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I/O and DMA START Fields I/O and DMA cycles use a START field of 0000. Reset Policy The following rules govern the reset policy: 1) When nPCI_RESET goes inactive (high), the clock is assumed to have been running for 100usec ...
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LPC TRANSFER SEQUENCE EXAMPLES Wait State Requirements I/O Transfers The LPC47M10x inserts three wait states for an I/O read and two wait states for an I/O write cycle. A SYNC of 0110 is used for all I/O transfers. The exception ...
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INT PENDING RESET 0 COND. BIT 0 DIRECTION Active high status indicating the direction of head movement. A logic "1" indicates inward direction; a logic "0" indicates outward direction. BIT 1 nWRITE PROTECT Active low status of the WRITE ...
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BIT 6 DMA REQUEST Active high status of the DMA request pending. BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt. STATUS REGISTER B (SRB) Address 3F1 READ ONLY This register is read-only and ...
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PS/2 Model 30 Mode 7 nDRV2 RESET N/A COND. BIT 0 nDRIVE SELECT 2 The DS2 disk interface is not supported. BIT 1 nDRIVE SELECT 3 The DS3 disk interface is not supported. BIT 2 WRITE GATE Active high status ...
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BIT 3 DMAEN PC/AT and Model 30 Mode: Writing this bit to logic "1" will enable the DMA and interrupt functions. This bit being a logic "0" will disable the DMA and interrupt functions. This bit is a logic "0" ...
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Table 5 - Internal 2 Drive Decode - Drives 0 and 1 Swapped 7 S/W RESET RESET 0 COND. DIGITAL OUTPUT REGISTER Bit 7 Bit 6 Bit 5 Bit ...
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BIT 2 through 4 PRECOMPENSATION SELECT These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 7 shows the precompensation values for the combination of these bits settings. Track 0 is ...
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DT1 DT0 Table 10 - Default Precompensation Delays MAIN STATUS REGISTER Address 3F4 READ ONLY The Main Status Register is a read-only register and indicates the status of the disk controller. The ...
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DATA REGISTER (FIFO) Address 3F5 READ/WRITE All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register. Data transfers are governed by the RQM and DIO bits ...
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DIGITAL INPUT REGISTER (DIR) Address 3F7 READ ONLY This register is read-only in all modes. PC-AT Mode 7 DSK CHG RESET N/A COND. BIT UNDEFINED The data bus outputs are read as ‘0’. BIT ...
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BIT 2 NOPREC This bit reflects the value of NOPREC bit set in the CCR register. BIT 3 DMAEN This bit reflects the value of DMAEN bit set in the DOR register bit 3. BITS UNDEFINED Always ...
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STATUS REGISTER ENCODING During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed. BIT NO. SYMBOL 7 1,0 DS1,0 BIT ...
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BIT NO. SYMBOL BIT NO. SYMBOL 1,0 DS1,0 RESET There are three sources of system reset on the ...
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PC/AT mode The PC/AT register set is enabled, the DMA enable bit of the DOR becomes valid (controls the interrupt and DMA functions), and DENSEL is an active high signal. PS/2 mode This mode supports the PS/2 models 50/60/80 configuration ...
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RQM can be used for polled systems. The host must respond to the request by reading data from the FIFO. This process is repeated until the last byte is transferred out of the FIFO. The FDC will deactivate the interrupt ...
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COMMAND SET/DESCRIPTIONS Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, ...
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Table 16 - Description of Command Symbols SYMBOL NAME MT Multi-Track When set, this flag selects the multi-track operating mode. In this Selector mode, the FDC treats a complete cylinder under head 0 and single track. The ...
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Table 16 - Description of Command Symbols SYMBOL NAME WGATE Write Gate INSTRUCTION SET PHASE R Command W MT MFM ──────── C ──────── W ──────── H ──────── W ──────── R ──────── W ──────── N ...
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PHASE R Command W MT MFM ──────── C ──────── W ──────── H ──────── W ──────── R ──────── W ──────── N ──────── W ─────── EOT ─────── W ─────── GPL ─────── W ─────── DTL ─────── Execution ...
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PHASE R Command W MT MFM Execution Result PHASE R Command W 0 MFM ...
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PHASE R Command W MT MFM Execution Result PHASE R Command Result PHASE ...
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PHASE R Command Execution SENSE INTERRUPT STATUS PHASE R Command Result R ─────── ST0 ─────── R ─────── PCN ─────── PHASE R Command ...
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PHASE R Command W 1 DIR ─────── RCN ─────── PHASE R Command Execution Result ──── SRT ──── LOCK ...
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PHASE R Command PHASE R Command W ───── Invalid Codes ───── Result R PHASE R/W D7 Command W LOCK Result returned if the last command that was issued was ...
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DATA TRANSFER COMMANDS All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. An implied ...
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Status Register 1 to "1", sets the DD bit in Status Register 2 to "1" if CRC is incorrect in the ID field, and terminates the Read Data Command. Table 20 describes the effect of the SK bit on the ...
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This command is similar to the Read Data command except that the entire data field is read continuously from each of the sectors of a track. Immediately after encountering a pulse on the nINDEX pin, the FDC starts to read ...
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Verify The Verify command is used to verify the data stored on a disk. This command acts exactly like a Read Data command except that no data is transferred to the host. Data is read from the disk and CRC ...
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GAP4a SYNC IAM GAP1 80x 12x 50x SYSTEM 3740 (SINGLE DENSITY) FORMAT GAP4a SYNC IAM GAP1 40x 6x 26x GAP4a SYNC IAM GAP1 80x 12x 50x ...
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IC code in Status Register 0 to "01" (abnormal termination), sets the MA bit in Status Register 1 to "1", and terminates the command. The following commands ...
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End of Seek, Relative Seek, or Recalibrate command 3. FDC requires a data transfer during the execution phase in the non-DMA mode The Sense Interrupt Status command resets the interrupt signal and, via the IC code and SE bit ...
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Configure Default Values: EIS - No Implied Seeks EFIFO - FIFO Disabled POLL - Polling Enabled FIFOTHR - FIFO Threshold Set to 1 Byte PRETRK - Pre-Compensation Set to Track 0 EIS - Enable Implied Seek. When set to "1", ...
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Any command issued will use the current PCN value except for the Recalibrate command, which only looks for the TRACK0 signal. Recalibrate will return an error if the head is farther than 79 due to its limitation of issuing a ...
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The write pre-compensation given to a perpendicular mode drive will be 0ns. 3. For D0-D3 programmed to "0" for conventional mode drives any data written will be at the currently programmed write pre-compensation. Note: Bits D0-D3 can only be ...
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The LPC47M10x incorporates two full function UARTs. They are compatible with the NS16450, the 16450 ACE registers and the NS16C550A. The UARTS perform serial-to-parallel conversion on received characters and parallel-to- serial conversion on transmit characters. The data rates are independently ...
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Disabling the interrupt system inhibits the Interrupt Identification Register and disables any Serial Port interrupt out of the LPC47M10x. All other system functions operate in their normal ...
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Transmitter Holding Register Empty 4. MODEM Status (lowest priority) Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt Identification Register (refer to Interrupt Control Table). When the CPU accesses ...
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Table 29 - Interrupt Control FIFO INTERRUPT MODE IDENTIFICATION ONLY REGISTER PRIORITY BIT 3 BIT 2 BIT 1 BIT 0 LEVEL Highest Second Second ...
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LINE CONTROL REGISTER (LCR) Address Offset = 3H, DLAB = 0, READ/WRITE This register contains the format information of the serial line. The bit definitions are: Bits 0 and 1 These two bits specify the number of bits in each ...
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This 8 bit register controls the interface with the MODEM or data set (or device emulating a MODEM). The contents of the MODEM control register are described below. Bit 0 This bit controls the Data Terminal Ready (nDTR) output. When ...
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Bit 4 Break Interrupt (BI). Bit 4 is set to a logic "1" whenever the received data input is held in the Spacing state (logic "0") for longer than a full word transmission time (that is, the total time of ...
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SCRATCHPAD REGISTER (SCR) Address Offset =7H, DLAB =X, READ/WRITE This 8 bit read/write register has no effect on the operation of the Serial Port intended as a scratchpad register to be used by the programmer to hold data ...
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When the XMIT FIFO and transmitter interrupts are enabled (FCR bit 0 = "1", IER bit 1 = "1"), XMIT interrupts occur as follows: A. The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty ...
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Table 31 - Reset Function REGISTER/SIGNAL Interrupt Enable Register Interrupt Identification Reg. FIFO Control Line Control Reg. MODEM Control Reg. Line Status Reg. MODEM Status Reg. TXD1, TXD2 INTRPT (RCVR errs) INTRPT (RCVR Data Ready) INTRPT (THRE) OUT2B RTSB DTRB ...
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Bit 7 of the Line Control Register (ADDR = 3). Note 1: Bit 0 is the least significant bit the first bit serially transmitted or received. Note 2: When operating in the XT mode, this bit ...
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The UART starts the above operations typically with a Tx interrupt. The chip issues a Tx interrupt whenever the Tx FIFO is empty and the Tx interrupt is enabled, except in the following instance. Assume that the Tx FIFO is ...
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Following a VTR POR, the IRTX and IRTX2 pins will be output and low. They will remain low until one of the following conditions are met: IRTX2/GP35 Pin. This pin defaults to the IRTX2 function. 1. This pin will remain ...
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NOTE: This figure is for illustration purposes only and is not intended to suggest specific implementation details. Host Interface Overview The Host Interface includes two contiguous 8-bit run-time registers (the Status/Command Port and the Data Port), and an interrupt. For ...
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Bit 7 – MIDI Receive Buffer Empty Bit 7 MIDI Receive Buffer Empty indicates the read state of the MIDI Data port (Table 36). If the MRBE bit is ‘0’, MIDI Read/Command Acknowledge data is available to the host. Acknowledge ...
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MIDI_IN MIDI RX DATA BYTE N 4 MIDI RX CLOCK 1 DATA READY 3 IRQ 2 nREAD 1 NOTE DATA READY represents the Data Ready bit B0 in the UART Line Status Register. 2 NOTE nREAD represents host read operations ...
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NOTE: The command acknowledge byte will appear as the next available data byte in the receive buffer of the MIDI Data port. For example if the receive FIFO is not empty when an MPU-401 RESET command is received, the command ...
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The LPC47M10x incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the Configuration Registers for information ...
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HOST CONNECTOR PIN NUMBER 1 83 2-9 68- (1) = Compatible Mode (3) = High Speed Mode Note: For the cable interconnection required for ...
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BIT 3 nERR - nERROR The level on the nERROR input is read by the CPU as bit 3 of the Printer Status Register. A logic 0 means an error has been detected; a logic 1 means no error has ...
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EPP write cycle. During a READ operation, PD0 - PD7 ports are read. An LPC I/O read cycle causes an EPP ADDRESS READ cycle to be performed and ...
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If the EPP bus is not ready (nWAIT is active low) when nDATASTB or nADDRSTB goes active then the write can complete when nWAIT goes inactive high the EPP bus is ready (nWAIT is inactive high) then ...
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Software Constraints Before an EPP cycle is executed, the software must ensure that the control register bits D0, D1 and D3 are set to zero. Also, bit D5 (PCD logic "0" for an EPP write or a logic ...
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EPP SIGNAL EPP NAME nWRITE nWrite PD<0:7> Address/Data INTR Interrupt WAIT nWait DATASTB nData Strobe RESET nReset ADDRSTB nAddress Strobe PE Paper End SLCT Printer Selected Status nERR Error Note 1: SPP and EPP can use 1 common register. Note ...
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The bit map of the Extended Parallel Port registers is data PD7 PD6 ecpAFifo Addr/RLE dsr nBusy nAck dcr 0 0 cFifo ecpDFifo tFifo cnfgA 0 0 cnfgB compress intrValue ecr MODE Note 1: These registers are available ...
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NAME TYPE nStrobe O During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). PData 7:0 I/O Contains address or data or RLE data. nAck I Indicates valid data driven by the ...
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MODE 000 SPP mode 001 PS/2 Parallel Port mode 010 Parallel Port Data FIFO mode 011 ECP Parallel Port mode 100 EPP mode (If this option is enabled in the configuration registers) 101 Reserved 110 Test mode 111 Configuration mode ...
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BIT 3 SELECTIN This bit is inverted and output onto the nSLCTIN output. A logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. BIT 4 ackIntEn - INTERRUPT REQUEST ENABLE The interrupt ...
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This register is a read only register. When read, 10H is returned. This indicates to the system that this is an 8-bit implementation. (PWord = 1 byte) cnfgB (Configuration Register B) ADDRESS OFFSET = 401H Mode = 111 BIT 7 ...
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R/W 000: Standard Parallel Port Mode . In this mode the FIFO is reset and common collector drivers are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will not tri-state the output drivers in ...
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ECP Operation Prior to ECP operation the Host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol. This is a somewhat complex negotiation carried out under program control in mode 000. After negotiation, it ...
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Pin Definition The drivers for nStrobe, nAutoFd, nInit and nSelectIn are open-collector in mode 000 and are push-pull in all other modes. LPC Connections The interface can never stall causing the host to hang. The width of data transfers is ...
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DMA may be disabled in the middle of a transfer by first disabling the host DMA controller. Then setting serviceIntr to 1, followed by setting dmaEn to 0, and waiting for the FIFO to become empty or full. Restarting the ...
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Power management capabilities are provided for the following logical devices: floppy disk, UART 1, UART 2 and the parallel port. For each logical device, two types of power management are provided: direct powerdown and auto powerdown. FDC Power Management Direct ...
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The part will revert back to its low power mode when the access has been completed. Pin Behavior The LPC47M10x is specifically designed for systems in which power conservation is a primary concern. This ...
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System Interface Pins Table 49 gives the state of the interface pins in the powerdown state. Pins unaffected by the powerdown are labeled "Unchanged". Table 49 – State of System Pins in Auto Powerdown SYSTEM PINS LAD[3:0] nLDRQ nLPCPD nLFRAME ...
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Parallel Port Direct power management is controlled by CR22. Refer to CR22 for more information. Auto Power Management is enabled by CR23-B3. When set, this bit allows the ECP or EPP logical parallel port blocks to be placed into powerdown ...
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SER_IRQ Cycle Control There are two modes of operation for the SER_IRQ Start Frame. 1) Quiet (Active) Mode: Any device may initiate a Start Frame by driving the SER_IRQ low for one clock, while the SER_IRQ is Idle. After driving ...
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SER_IRQ PERIOD The SER_IRQ data frame will now support IRQ2 from a logical device, previously SER_IRQ Period 3 was reserved for use by the ...
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Reset and Initialization The SER_IRQ bus uses nPCI_RESET as its reset signal. The SER_IRQ pin is tri-stated by all agents while nPCI_RESET is active. With reset, SER_IRQ Slaves are put into the (continuous) IDLE mode. The Host Controller is responsible ...
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KEYBOARD INTERFACE The LPC47M10x LPC interface is functionally compatible with the 8042 style host interface. It consists of the D0-7 data signals; the read and write signals and the Status register, Input Data register, and Output Data register. Table 51 ...
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MIRQ is controlled by P25, Writing a zero to P25 forces MIRQ low, a high forces MIRQ high. (MIRQ is normally selected as IRQ12 for mouse support). Gate A20 A general purpose P21 is used as a software ...
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Host I/F Status Register The Status register is 8 bits wide. Table 53 shows the contents of the Status register Status Register This register is cleared on a reset. This register is read-only for ...
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Bit Function 7:6 Reserved. Returns 00 when read 5 Reserved. Returns a 1 when read 4 Reserved. Returns a 0 when read 3 Reserved. Returns a 0 when read 2 Reserved. Returns a 1 when read 1 ALT_A20 Signal control. ...
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P20 P92 Bit 0 Note: When Port 92 is disabled, writes are ignored and reads return undefined values. Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the CPU low for support of real ...
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Latches On Keyboard and Mouse IRQs The implementation of the latches on the keyboard and mouse interrupts is shown below. 8042 8042 KLATCH Bit VCC D Q KINT CLR RD 60 FIGURE 5 – KEYBOARD LATCH MLATCH Bit VCC D ...
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The KLATCH and MLATCH bits are located in the KRST_GA20 register, in Logical Device 7 at 0xF0. These bits are defined as follows: Bit[4]: MLATCH – Mouse Interrupt latch control bit. 0=MINT is the 8042 MINT ANDed with Latched MINT ...
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The LPC47M10x provides a set of flexible Input/Output control functions to the system designer through the 37 dedicated independently programmable General Purpose I/O pins (GPIO). The GPIO pins can perform basic I/O and many of them can be individually enabled ...
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PME block see Run Time Register section. configuration state register addresses are listed in Table 55. TABLE 55 - General Purpose I/O Port Assignments PIN NO. DEFAULT ALT. /QFP FUNCTION FUNC GPIO Joystick 1 Button ...
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PIN NO. DEFAULT ALT. /QFP FUNCTION FUNC GPIO Device Disable Reg. Control N/A Reserved 92 GPIO Ring Indicator 2 94 GPIO Data Carrier Detect 2 95 GPIO Receive Serial Data 2 96 GPIO Transmit Serial Data 2 97 ...
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GPIO Operation The operation of the GPIO ports is illustrated in Figure 4. Note: Figure 7 is for illustration purposes only and is not intended to suggest specific implementation details. D-TYPE SD-bit D Q GPx_nIOW Transparent Q D GPx_nIOR GPIO ...
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GPIO PME and SMI Functionality The following GPIOs are dedicated wakeup GPIOs with a status and enable bit in the PME status and enable registers: GP10-GP17 GP20-GP22, GP24-GP27 GP30-GP33 GP41, GP43 GP50-GP57 GP60, GP61 The following PME status and enable ...
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Note 2: GP36-GP37 and GP40 should not be connected to any VTR powered external circuitry. These pins are not used for wakeup. Note 3: GP60 and GP61 have LED functionality which must be active under VTR so its buffer is ...
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SYSTEM MANAGEMENT INTERRUPT (SMI) The LPC47M10x implements a “group” nIO_SMI output pin. The System Management Interrupt is a non-maskable interrupt with the highest priority level used for OS transparent power management. The nIO_SMI group interrupt output consists of the enabled ...
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The LPC47M10x offers support for power management events (PMEs). A power management event is requested by a function via the assertion of the nIO_PME signal. transitions on the ring indicator inputs nRI1 and nRI2, valid NEC infrared remote control frames, ...
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SMI output is active. Note: Bit 5 of the SMI_EN2 register must also be set. This bit is cleared on a write of ‘1’. There is a bit in the PME Enable Register 3 to enable the SMI ...
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The state machine will reset after 11 clocks and the process will restart. The process will continue until it is shut off by setting the SPEKEY_EN bit (see following sub-section). The state machine will reset if there is a period ...
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Note 2. This is Fan Control Register Bit Note 3. This is Fan Control Register Bit Note 4. This is FANx Register Bit 7 FANx Registers The FAN1 and FAN2 Registers are located at ...
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The fan tachometer input signal and clock source is shown below. Fan Tachometer Input Clock Source for Counter The counter is reset by the rising edge of each pulse (and by writing the preload register). The counter does not wrap; ...
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RPM for the generation of a PME or SMI. A representation of the logic for the fan tachometer implementation is shown ...
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The following register describes the functionality to support security in the LPC47M10x. GPIO Device Disable Register Control The GPIO pin GP43 is used for the Device Disable Register Control (DDRC) function. Setting bits[3:2] of the GP43 configuration register to ‘01’, ...
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The figure below illustrates the timing of the game port signals. The 556 timers will reset the outputs (OUTA,B) to zero and the RC constant (TIMA,B) pins to zero when the RC constant (TIMA,B) inputs reach 2/3 of VREF as ...
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Game Port Register Register Location: <GAME_PORT>+0h System I/O Space Default Value: 00h on VTR POR Attribute: Read-Only Size: 8-bits D7 D6 Button #2 Button #1 Button #2 Joystick 2 Joystick 2 Joystick 1 (J2B2) (J2B1) The game port register is ...
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REGISTER OFFSET HARD (hex) RESET TYPE (Note 4) 10 R ...
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REGISTER OFFSET HARD (hex) RESET TYPE 3B R/W 3C R/W 3D R/W Note 2 3E R/W 3F R/W 40 R/W 41 R/W 42 R/W 0x00 43 R/W 44 R/W 45 R/W 46 R/W 47 R ...
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The following registers are located at an offset from (PME_BLK) the address programmed into the base I/O address register for Logical Device A. REG OFFSET NAME PME_STS Default = 0x00 on VTR POR N/A PME_EN Default = 0x00 on VTR ...
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REG OFFSET NAME (hex) PME_STS2 05 Default = 0x00 (R/W) on VTR POR PME_STS3 06 Default = 0x00 (R/W) on VTR POR PME_STS4 07 Default = 0x00 (R/W) on VTR POR (Note 6) DESCRIPTION PME Wake Status Register 2 This ...
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REG OFFSET NAME (hex) PME_STS5 08 Default = 0x00 (R/W) on VTR POR (Note 6) N/A 09 (R) PME_EN1 0A Default = 0x00 (R/W) on VTR POR DESCRIPTION PME Wake Status Register 5 This register indicates the state of the ...
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REG OFFSET NAME (hex) PME_EN2 0B Default = 0x00 (R/W) on VTR POR PME_EN3 0C Default = 0x00 (R/W) on VTR POR DESCRIPTION PME Wake Enable Register 2 This register is used to enable individual LPC47M10x PME wake sources onto ...
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REG OFFSET NAME (hex) PME_EN4 0D Default = 0x00 (R/W) on VTR POR PME_EN5 0E Default = 0x00 (R/W) on VTR POR N/A 0F (R) SMI_STS1 10 Default = 0x02 (R/W) on VTR POR Bit 1 is set to ‘1’ ...
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REG OFFSET NAME (hex) SMI_STS2 11 Default = 0x00 (R/W) on VTR POR SMI_STS3 12 Default = 0x00 (R/W) on VTR POR SMI_STS4 13 Default = 0x00 (R/W) on VTR POR (Note 6) SMI_STS5 14 Default = 0x00 (R/W) on ...
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REG OFFSET NAME (hex) SMI_EN1 16 Default = 0x00 (R/W) on VTR POR SMI_EN2 17 Default = 0x00 (R/W) on VTR POR SMI_EN3 18 Default = 0x00 (R/W) on VTR POR SMI_EN4 19 Default = 0x00 (R/W) on VTR POR ...
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REG OFFSET NAME (hex) SMI_EN5 1A Default = 0x00 (R/W) on VTR POR N/A 1B (R) MSC_STS 1C Default = 0x00 (R/W) on VTR POR N/A 1D (R) Force Disk Change 1E Default = 0x01 on (R/W) VCC POR DESCRIPTION ...
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REG OFFSET NAME (hex) Floppy Data Rate 1F Select Shadow (R) UART1 FIFO 20 Control Shadow (R) UART2 FIFO Control 21 Shadow (R) DESCRIPTION Floppy Data Rate Select Shadow Bit[0] Data Rate Select 0 Bit[1] Data Rate Select 1 Bit[2] ...
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REG OFFSET NAME (hex) Device Disable 22 Register Read/Write when Default = 0x00 GP43 register VTR POR bits[3: AND GP43 pin = 0 OR GP43 register bits[3:2] ≠ 01 READ-ONLY When GP43 register bits[3:2] =01 AND GP43 pin ...
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REG OFFSET NAME (hex) GP12 25 Default = 0x01 (R/W) on VTR POR GP13 26 Default = 0x01 (R/W) on VTR POR GP14 27 Default = 0x01 (R/W) on VTR POR GP15 28 Default = 0x01 (R/W) on VTR POR ...
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REG OFFSET NAME (hex) GP17 2A Default = 0x01 (R/W) on VTR POR GP20 2B Default = 0x01 (R/W) on VTR POR GP21 2C Default =0x01 (R/W) on VTR POR GP22 2D Default =0x01 (R/W) on VTR POR N/A 2E ...
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REG OFFSET NAME (hex) GP25 30 (R/W) Default = 0x01 on VTR POR GP26 31 Default = 0x01 (R/W) on VTR POR GP27 32 Default = 0x01 (R/W) on VTR POR GP30 33 Default = 0x01 (R/W) on VTR POR ...
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REG OFFSET NAME (hex) GP32 35 Default = 0x01 (R/W) on VTR POR Default = 0x00 on VCC POR and Hard Reset (Note 3) GP33 36 Default = 0x01 (R/W) on VTR POR Default = 0x00 on VCC POR and ...
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REG OFFSET NAME (hex) GP37 3A Default = 0x01 (R/W) on VTR POR GP40 3B Default =0x01 (R/W) on VTR POR GP41 3C Default =0x01 (R/W) on VTR POR GP42 3D Default =0x01 (R/W) on VTR POR DESCRIPTION General Purpose ...
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REG OFFSET NAME (hex) GP43 3E Default = 0x01 (R/W) on VTR POR Bits[3:2] are reset (cleared) on VCC POR, VTR POR and Hard Reset GP50 3F Default = 0x01 (R/W) on VTR POR GP51 40 Default = 0x01 (R/W) ...
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REG OFFSET NAME (hex) GP52 41 Default = 0x01 (R/W) on VTR POR GP53 42 Default = 0x00 (R/W) on VTR POR, VCC POR and Hard Reset (Note 4) GP54 43 Default = 0x01 (R/W) on VTR POR GP55 44 ...
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REG OFFSET NAME (hex) GP56 45 Default = 0x01 (R/W) on VTR POR GP57 46 Default = 0x01 (R/W) on VTR POR GP60 47 Default = 0x01 (R/W) on VTR POR GP61 48 Default = 0x01 (R/W) on VTR POR ...
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REG OFFSET NAME (hex) GP1 4B Default = 0x00 (R/W) on VTR POR GP2 4C Default = 0x00 on VTR POR (R/W) GP3 4D Default = 0x00 (R/W) on VTR POR Bits 2 and 3 are reset on VCC POR, ...
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REG OFFSET NAME (hex) FAN1 56 Default = 0x00 (R/W) on VTR POR FAN2 57 Default = 0x00 (R/W) on VTR POR DESCRIPTION FAN Register 1 Bit[0] Fan Control 1=FAN1 pin is high 0=bits[6:1] control the duty cycle of the ...
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REG OFFSET NAME (hex) Fan Control 58 Default = 0x50 (R/W) on VTR POR Fan1 Tachometer 59 Register (R) Default = 0x00 on VTR POR Fan2 Tachometer 5A Register (R) Default = 0x00 on VTR POR Fan1 Preload 5B Register ...
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REG OFFSET NAME LED1 Default = 0x00 on VTR POR LED2 Default = 0x00 on VTR POR Keyboard Scan Code Default = 0x00 on VTR POR N/A User Note: When selecting an alternate function for a GPIO pin, all bits ...
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The following register is located at an offset of zero from (GAME_PORT) the address into the base I/O address register for Logical Device 9. REG OFFSET NAME Game Port Register Default = 0x00 on VTR POR CONFIGURATION The Configuration of ...
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Entering the Configuration State The device enters the Configuration State when the following Config Key is successfully written to the CONFIG PORT. Exiting the Configuration State The device exits the Configuration State when the following Config Key is successfully written ...
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Programming Example The following is an example of a configuration program in Intel 8086 assembly language. ;----------------------------. ; ENTER CONFIGURATION MODE ;----------------------------' MOV DX,02EH MOV AX,055H OUT DX,AL ;----------------------------. ; CONFIGURE REGISTER CRE0, ; LOGICAL DEVICE 8 ;----------------------------' MOV DX,02EH ...
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INDEX TYPE HARD RESET 0x2C R/W - 0x2D R/W - 0x2E R/W - 0x2F R/W - LOGICAL DEVICE 0 CONFIGURATION REGISTERS (FDD) 0x30 R/W 0x00 0x60, R/W 0x03, 0x61 0xF0 0x70 R/W 0x06 0x74 R/W 0x02 0xF0 R/W 0x0E 0xF1 ...
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INDEX TYPE HARD RESET 0x30 R/W 0x00 0x70 R/W 0x00 0x72 R/W 0x00 0xF0 R/W 0x00 LOGICAL DEVICE 8 CONFIGURATION REGISTERS (Reserved) LOGICAL DEVICE 9 CONFIGURATION REGISTERS (Game Port) 0x30 R/W 0x00 0x60, R/W 0x00, 0x61 0x00 LOGICAL DEVICE A ...
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Chip Level (Global) Control/Configuration Registers[0x00-0x2F] The chip-level (global) registers lie in the address range [0x00-0x2F]. The design MUST use all 8 bits of the ADDRESS Port for register selection. All unimplemented registers and bits ignore writes and return zero when ...
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REGISTER ADDRESS Power Mgmt 0x23 R/W Default = 0x00 on VCC POR, VTR POR and HARD RESET Table 63 – Chip Level Registers (cont’d) REGISTER ADDRESS OSC 0x24 R/W Default = 0x44 VCC POR, VTR POR and HARD ...
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REGISTER ADDRESS TEST 4 0x2B R/W Default = 0x00, on VCC POR and VTR POR TEST 5 0x2C R/W Default = 0x00, on VCC POR and VTR POR TEST 1 0x2D R/W Default = 0x00, on VCC POR and VTR ...
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LOGICAL DEVICE REGISTER Note1 Activate Default = 0x00 on VCC POR, VTR POR, HARD RESET and SOFT RESET Logical Device Control (0x31-0x37) Logical Device Control Memory Base Address (0x40-0x5F) Note 2 I/O Base Address (0x60-0x6F) (see Device Base I/O Address ...
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DEVICE ON (ACTIVE) = (Activate Bit SET or Pwr/Control Bit SET). The Logical device's Activate Bit and its Pwr/Control Bit are linked such that setting or clearing one sets or clears the other. Note 2: If the I/O Base Addr ...
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Table 65 - I/O Base Address Configuration Register Description LOGICAL DEVICE LOGICAL NUMBER DEVICE 0x0A Runtime Registers 0x0B MPU-401 Config. Config. Port Port Note 1: This chip uses address bits [A11:A0] to decode the base address of each of its ...
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For the KYBD by (refer to the KYBD controller section of this spec). Note: IRQs are disabled if not used/selected by any Logical Device. Refer to Note A. Note: nSMI must be disabled to use IRQ2. Note: All IRQ’s are ...
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SMSC Defined Logical Device Configuration Registers The SMSC Specific Logical Device Configuration Registers reset to their default values only on hard resets generated by Vcc or VTR POR (as shown) or the nPCI_RESET signal. These registers are not affected by ...
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Table 68 - Floppy Disk Controller, Logical Device 0 [Logical Device Number = 0x00] NAME REG INDEX FDD0 0xF4 R/W Default = 0x00 on VCC POR, VTR POR and HARD RESET FDD1 0xF5 R/W Table 69 - Parallel Port, Logical ...
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Table 70 - Serial Port 1, Logical Device 4 [Logical Device Number = 0x04] NAME REG INDEX Serial Port 1 0xF0 R/W Mode Register Default = 0x00 on VCC POR, VTR POR and HARD RESET Note 1: To properly share ...
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Table 71 - Serial Port 2, Logical Device 5 [Logical Device Number = 0x05] NAME REG INDEX IR Option Register 0xF1 R/W Default = 0x02 on VCC POR, VTR POR and HARD RESET IR Half Duplex 0xF2 Timeout Default = ...
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Table 72 - KYBD, Logical Device 7 [Logical Device Number = 0x07] NAME REG INDEX KRST_GA20 0xF0 KRESET and GateA20 Select R/W Bit[7] Polarity Select for P12 Default = 0x00 = 0 P12 active low (default) on VCC POR, = ...
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Table 74 – MPU-401 [Logical Device Number = 0x0B] NAME REG INDEX Base I/O Address Low Byte Default = 0x30 on HARD RESET, SOFT RESET, VCC POR and VTR POR OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS* Operating Temperature Range.....................................................................................................0 Storage Temperature ...
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PARAMETER SYMBOL IO6 Type Buffer Low Output Level High Output Level Output Leakage OD6 Type Buffer Low Output Level Output Leakage O6 Type Buffer Low Output Level High Output Level IO8 Type Buffer Low Output Level High Output Level Output ...
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PARAMETER OP14 Type Buffer Low Output Level High Output Level Output Leakage IOP14 Type Buffer Low Output Level High Output Level Output Leakage IOD16 Type Buffer Low Output Level Output Leakage Backdrive Protect/ChiProtect (All pins excluding LAD[3:0], nLDRQ, nLPCPD, nLFRAME) ...
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CIR ‘off’ is 250 μA. Note 5: Min I with V TRI CC CAPACITANCE T = 25° 1MHz PARAMETER SYMBOL Clock Input Capacitance Input Capacitance Output Capacitance C For the Timing Diagrams shown, ...
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NAME DESCRIPTION t1 Vcc Slew from 2. Vcc Slew from 0V to 2.7V t3 All Host Accesses After Powerup ...
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NAME t1 Period t2 High Time t3 Low Time t4 Rise Time t5 Fall Time nPCI_RESET NAME t4 nPCI_RESET width (Note 1) Note 1: The nPCI_RESET width is dependent upon the processor clock. The ...
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CLK Output Delay Tri-State Output FIGURE 10 – OUPUT TIMING MEASUREMENT CONDITIONS, LPC SIGNALS NAME DESCRIPTION t1 CLK to Signal Valid Delay – Bused Signals t2 Float to Active Delay t3 Active to Float Delay CLK Input FIGURE 11 – ...
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PCI_CLK nLFRAME nLAD[3: Note: L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000 PCI_CLK nLFRAME nLAD[3: Note: L1=Start; L2=CYCTYP+DIR; L3=Sync of 0000 PCI_CLK nLDRQ Start FIGURE 14 – DMA REQUEST ASSERTION THROUGH nLDRQ PCI_CLK nLFRAME Start C+D CHL Size nLAD[3:0] ...
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FIGURE 17 – FLOPPY DISK DRIVE TIMING (AT MODE ONLY) NAME DESCRIPTION t1 nDIR Set Up to STEP Low t2 nSTEP Active Time Low t3 nDIR Hold Time after nSTEP t4 nSTEP ...
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PD<7:0> nDATASTB nADDRSTB nWAIT FIGURE 18 – EPP 1.9 DATA OR ADDRESS WRITE CYCLE NAME DESCRIPTION t1 nWAIT Asserted to nWRITE Asserted (Note 1) t2 nWAIT Asserted to nWRITE Change (Note 1) t3 nWAIT Asserted to PDATA Invalid ...
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PD<7:0> DATASTB ADDRSTB nWAIT FIGURE 19 – EPP 1.9 DATA OR ADDRESS READ CYCLE NAME t1 nWAIT Asserted to nWRITE Deasserted t2 nWAIT Asserted to nWRITE Modified (Notes 1,2) t3 nWAIT Asserted to PDATA Hi-Z (Note 1) t4 Command ...
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PD<7:0> nDATASTB nADDRSTB nWAIT FIGURE 20 – EPP 1.7 DATA OR ADDRESS WRITE CYCLE NAME DESCRIPTION t1 Command Deasserted to nWRITE Change t2 Command Deasserted to PDATA Invalid t3 PDATA Valid to Command Asserted t4 nWRITE to Command t5 ...
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Parallel Port FIFO (Mode 101) The standard parallel port is run at or near the peak 500KBytes/sec allowed in the forward direction using DMA. The state machine does not examine nACK and begins the next transfer based on Busy. Refer ...
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Output Drivers To facilitate higher performance data transfer, the use of balanced CMOS active drivers for critical signals (Data, HostAck, HostClk, PeriphAck, PeriphClk) are used in ECP Mode. Because the use of active drivers can present compatibility problems in Compatible ...
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PD<7:0> nSTROBE t6 BUSY FIGURE 23 - ECP PARALLEL PORT FORWARD TIMING NAME DESCRIPTION t1 nALF Valid to nSTROBE Asserted t2 PDATA Valid to nSTROBE Asserted t3 BUSY Deasserted to nALF Changed (Notes 1,2) t4 BUSY Deasserted to PDATA ...
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PD<7:0> nACK t4 nALF FIGURE 24 - ECP PARALLEL PORT REVERSE TIMING NAME DESCRIPTION t1 PDATA Valid to nACK Asserted t2 nALF Asserted to PDATA Changed t3 nACK Asserted to nALF Deasserted (Notes 1,2) t4 nACK Deasserted to nALF Asserted ...
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DATA IRRX n IRRX Pa rame ter t1 Pulse Width at 1 15kba ud t1 Pul se Wid th at 57.6kba ud t1 Pul se Wid th at 38.4kba ud t1 Pul ...
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DAT IRT X n IRT X Parameter t1 Pulse Width at 115kbaud t1 Pulse Width at 57.6kbaud t1 Pulse Width at 38.4kbaud t1 Pulse Width at 19.2kbaud t1 Pulse Width at ...
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DAT IRRX n IRRX IRRX IRRX Pa ramet odu lated Out put Bit T ime t2 Off Bit T ime t3 M odu lated ...
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IRTX n IRT MIRTX MIRT X Pa ramet odu lated Out put Bit T ime t2 Off Bit T ime t3 M odu ...
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PCI_CLK SER_IRQ FIGURE 29 – SETUP AND HOLD TIME NAME DESCRIPTION t1 SER_IRQ Setup Time to PCI_CLK Rising t2 SER_IRQ Hold Time to PCI_CLK Rising Data Start TXD1, 2 NAME DESCRIPTION t1 Serial Port Data Bit Time Note 1: t ...
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J1X, J1Y, J2X, J2Y t1 FIGURE 31 – JOYSTICK POSITION SIGNAL NAME DESCRIPTION t1 Rise Time to 2/3 VREF J1B1, J1B2, J2B1, J2B2 t1 FIGURE 32 – JOYSTICK BUTTON SIGNAL NAME DESCRIPTION t1, t2 Button Fall/Rise Time MIN 20 90% ...
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CLK CLK KCLK MCLK Start Bit Bit 0 KDAT/ MDAT FIGURE 33 – KEYBOARD/MOUSE RECEIVE/SEND DATA TIMING NAME DESCRIPTION t1 Time from DATA transition to falling edge of CLOCK (Receive) t2 Time from ...
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Idle (No Data) Data Start Bit MIDI_Tx NAME t1 MIDI Data Bit Time Note: The MIDI bit clock is 31.25kHz +/- 1% FANx NAME DESCRIPTION t1 PWM Period (Note 1) t2 PWM High Time (Note 2) Note 1: The period ...
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FAN_TACHx FIGURE 36 – FAN TACHOMETER INPUT TIMING NAME DESCRIPTION t1 Pulse Time (1/2 Revolution Time=30/RPM) t2 Pulse High Time t3 Pulse Low Time Note the clock used for the tachometer counter 30.52 * DVSR, ...
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PACKAGE OUTLINE ...
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APPENDIX - TEST MODE Board Test Mode Board test mode can be entered as follows: On the rising (deasserting) edge of nPCI_RESET, drive nLFRAME low and drive LAD[0] low. Exit board test mode as follows: On the rising (deasserting) edge ...
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Introduction The LPC47M10x provides board test capability through the XNOR chain. When the chip is in the XNOR chain test mode, setting the state of any of the input pins to the opposite of its current state will cause the ...
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TRUTH TABLE 1 - Toggling Inputs In Descending Order PIN PIN 100 99 INITIAL CONFIG L L STEP STEP STEP STEP STEP … … … ...
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... Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders. ...