IC AMP AUDIO PWR 37W D 56TSSOP

TAS5122DCA

Manufacturer Part NumberTAS5122DCA
DescriptionIC AMP AUDIO PWR 37W D 56TSSOP
ManufacturerTexas Instruments
SeriesPurePath Digital™
TypeClass D
TAS5122DCA datasheet
 


Specifications of TAS5122DCA

Output Type2-Channel (Stereo)Max Output Power X Channels @ Load37W x 2 @ 6 Ohm
Voltage - Supply16 V ~ 25.5 VFeaturesDepop, Digital Inputs, Mute, Short-Circuit and Thermal Protection, Shutdown
Mounting TypeSurface MountPackage / Case56-TSSOP Exposed Pad, 56-eTSSOP, 56-HTSSOP
For Use WithTAS5508-5122C6EVM - EVAL MODULE FOR TAS5508B/TAS5122TAS5028-5122C6EVM - EVAL MODULE FOR TAS5028A/TAS5122TAS5010-5112F2EVM - EVAL MODULE FOR TAS5010/TAS5112TAS5001-5122C2EVM - EVAL MODULE FOR TAS5001/TAS5122Lead Free Status / RoHS StatusLead free / RoHS Compliant
Other names296-18835-5  
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TAS5122
SLES088E – AUGUST 2003 – REVISED DECEMBER 2004
THEORY OF OPERATION
POWER SUPPLIES
The power device only requires two supply voltages,
GVDD and PVDD_x.
GVDD is the gate drive supply for the device, regulated
internally down to approximately 12 V, and decoupled with
regards to board GND on the GREG pins through an
external capacitor. GREG powers both the low side and
high side via a bootstrap step-up conversion. The
bootstrap supply is charged after the first low-side turnon
pulse. Internal digital core voltage DREG is also derived
from GVDD and regulated down by internal low-dropout
regulators (LDRs) to 3.3 V.
The gate-driver LDR can be bypassed for reducing idle
loss in the device by shorting GREG to GVDD and directly
feeding in 12 V. This can be useful in an application where
thermal conduction of heat from the device is difficult.
Bypassing the LDR reduces power dissipation.
PVDD_x is the H-bridge power supply pin. Two power pins
exist for each half-bridge to handle the current density. It
is
important
that
the
circuitry
concerning the PVDD_x pins are followed carefully both
topology-
and
layout-wise.
recommendations, see the System Configuration Used for
Characterization
section.
Following
recommendations is important for parameters like EMI,
reliability, and performance.
SYSTEM POWER-UP/POWER-DOWN
SEQUENCE
Powering Up
> 1 ms
RESET
GVDD (1)
PVDD_x (1)
PWM_xP
(1) PVDD should not be powered up before GVDD.
During power up when RESET is asserted LOW, all
MOSFETs are turned off and the two internal half-bridges
are in the high-impedance state (Hi-Z). The bootstrap
capacitors supplying high-side gate drive are at this point
12
not charged. To comply with the click and pop scheme and
use of non-TI PWM processors, it is recommended to use
a 4-kΩ pulldown resistor on each PWM output node to
ground. This precharges the bootstrap supply capacitors
and discharges the output filter capacitor (see the System
Configuration Used for Characterization section).
After GVDD has been applied, it takes approximately 800
µs to fully charge the BST capacitor. Within this time,
RESET must be kept low. After approximately 1 ms, the
power stage bootstrap capacitor is charged.
RESET can now be released if the modulator is powered
up and streaming PWM signals to the power stage
PWM_xP.
A constant HIGH dc level on PWM_xP is not permitted,
because it would force the high-side MOSFET ON until it
eventually ran out of BST capacitor energy and might
damage the device.
An unknown state of the PWM output signals from the
processor is illegal and should be avoided, which in
practice means that the PWM processor must be powered
up and initialized before RESET is deasserted HIGH to the
power stage.
recommendations
Powering Down
For
topology
For powering down the power stage, an opposite
approach is necessary. RESET must be asserted LOW
these
before the valid PWM signal is removed.
When TI PWM processors are used with TI power stages,
the correct timing control of RESET and PWM_xP is
performed by the modulator.
Precaution
The TAS5122 must always start up in the high-impedance
(Hi-Z) state. In this state, the bootstrap (BST) capacitor is
precharged by a resistor on each PWM output node to
ground.
See
> 1 ms
Characterization. This ensures that the power stage is
ready for receiving PWM pulses, indicating either HIGH-
or LOW-side turnon after RESET is deasserted to the
power stage.
With the following pulldown and BST capacitor size, the
charge time is:
C = 33 nF, R = 4.7 kΩ
R × C × 5 = 775.5 µs
After GVDD has been applied, it takes approximately
800 µs to fully charge the BST capacitor. During this time,
RESET must be kept low. After approximately 1 ms, the
power stage BST is charged and ready. RESET can now
be released if the PWM modulator is ready and is
streaming valid PWM signals to the power stage. Valid
PWM signals are switching PWM signals with a frequency
between 350−400 kHz. A constant HIGH level on the
PWM_xP forces the high-side MOSFET ON until it
eventually runs out of BST capacitor energy. Putting the
device in this condition should be avoided.
www.ti.com
System
Configuration
Used
for