LC78622NE Sanyo Semiconductor Corporation, LC78622NE Datasheet

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LC78622NE

Manufacturer Part Number
LC78622NE
Description
Manufacturer
Sanyo Semiconductor Corporation
Datasheet

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LC78622NE
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SANYO/三洋
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LC78622NE
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LC78622NE-E
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LC78622NE-E
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Ordering number : EN6015
Overview
The LC78622NE is a CMOS IC that implements the
signal processing and servo control required by compact
disc players. At the same time as providing an EFM PLL
circuit, a 1-bit D/A converter, and an analog low-pass
filter the LC78622NE realizes an optimal cost-
performance tradeoff for low-end players by strictly
limiting functionality to basic signal-processing and servo
system functionality. The LC78622NE signal-processing
system provides demodulation of the EFM signal from the
pickup, de-interleaving, error detection and correction, and
digital filters that can prove useful in reducing the cost of
end products. The LC78622NE servo control system
processes servo commands sent from the control
microprocessor.
The LC78622NE is an improved version of the LC78622E
that adds 8 oversampling digital filters, three general-
purpose output ports (that also have specific shared
functions) and the PCCL pin (pin 34). However, some
handling of general-purpose ports differ from that of the
LC78622E, therefore care must be taken.(Refer to pages
16 and 21).
Functions
• Input signal processing: The LC78622NE takes an HF
• Precise reference clock and necessary internal timing
• Disk motor speed control using a frame phase difference
signal as input, digitizes (slices) that signal at a precise
level, converts that signal to an EFM signal, and
generates a PLL clock with an average frequency of
4.3218 MHz by comparing the phases of that signal and
an internal VCO.
generation using an external 16.9344 MHz crystal
oscillator
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
• Frame synchronization signal detection, protection and
• EFM signal demodulation and conversion to 8-bit
• Subcode data separation from the EFM demodulated
• Subcode Q signal output to a microprocessor over the
• Demodulated EFM signal buffering in internal RAM to
• Demodulated EFM signal reordering in the prescribed
• Error detection, correction, and flag processing (error
• Sets the C2 flags based on the C1 flags and a C2 check,
• Support for command input from a control
• Built-in digital output circuits.
• Arbitrary track counting to support high-speed data
• D/A converter outputs with data continuity improved by
• Built-in third-order
signal generated from the playback clock and the
reference clock
interpolation to assure stable data readout
symbol data
signal and output of that data to an external
microprocessor
serial I/O interface after performing a CRC error check
(LSB first)
handle up to ±4 frames of disk rotational jitter
order for data unscrambling and de-interleaving
correction scheme: dual C1 plus dual C2 correction)
and then performs signal interpolation or muting
depending on the C2 flags. The interpolation circuit uses
a dual-interpolation scheme. The previous value is held
if the C2 flags indicate errors two or more times
consecutively.
microprocessor: commands include track jump, focus
start, disk motor start/stop, muting on/off and track
count (8 bit serial input)
access
8 oversampling digital filters.
pass filter is built in.)
Compact Disc Player DSP
D/A converters (An analog low-
LC78622NE
11999RM (OT) No. 6015-1/31
CMOS IC

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LC78622NE Summary of contents

Page 1

... The LC78622NE servo control system processes servo commands sent from the control microprocessor. The LC78622NE is an improved version of the LC78622E that adds 8 oversampling digital filters, three general- purpose output ports (that also have specific shared functions) and the PCCL pin (pin 34). However, some handling of general-purpose ports differ from that of the LC78622E, therefore care must be taken ...

Page 2

... Built-in digital de-emphasis • Zero cross muting • Supports the implementation of a double-speed dubbing function. • Support for bilingual applications. • General-purpose I/O ports: 5 pins Features • single-voltage power supply Equivalent Circuit Block Diagram LC78622NE Package Dimensions unit: mm 3159-QFP64E [LC78622NE] 17.2 14.0 1.0 0.8 0. 15.6 1.6 1.0 ...

Page 3

... Pin Assignment Specifications Absolute Maximum Ratings 25°C, V Parameter Maximum supply voltage Input voltage Output voltage Allowable power dissipation Operating temperature Storage temperature LC78622NE = Symbol Conditions V max OUT Pd max Topr Tstg Ratings Unit V – – 0 ...

Page 4

... TST11, 16M, 4.2M, CONT1 to CONT5 (3) DOUT PDO, CLV I (1) OFF V Output off leakage current PDO, CLV I (2) OFF V I PDO: R PDOH Charge pump output current I PDO: R PDOL LC78622NE = Conditions , Capacitor-coupled input ...

Page 5

... A filter (AD725D built in) LCHO, RCHO; 1 kHz data input, Crosstalk CT using the 20 kHz low-pass filter (AD725D built in) Note: Measured with the normal-speed playback mode in the Sanyo one-bit D/A converter block reference digital attenuator circuit set to EE (hexadecimal). LC78622NE = ...

Page 6

... LC78622NE Figure 2 Subcode Q Output Figure 3 Subcode Output Figure 4 General-Purpose Port Input Timing Figure 5 General-Purpose Port Output Timing No. 6015-6/31 ...

Page 7

... Subcode and W output 50 SFSY O Subcode frame synchronization signal output. This signal falls when the subcodes are in the standby state. LC78622NE Function Test input. A pull-down resistor is built in. Must be connected Internal VCO control phase comparator output Internal VCO ground. Must be connected ...

Page 8

... We recommend laying a ground or V shield line between these two lines. Since the LC78622NE includes a VCO circuit, a PLL circuit can be formed by connecting an external RC circuit. ISET is the charge pump reference current, PDO is the VCO circuit loop filter, and resistor that determines the VCO frequency range ...

Page 9

... Focus start Track jump Muting control One-byte commands Disk motor control Miscellaneous control Track check Two-byte command (RWC set twice) Digital attenuator Two-byte commands (RWC set once) General-purpose I/O, E/D • One-byte commands • Two-byte commands (RWC set twice: For track checking) LC78622NE No. 6015-9/31 ...

Page 10

... Note: CLV servo control commands can set the TOFF pin low only in CLV mode. That pin will be at the high level at all other times. Control of the TOFF pin by microprocessor command is only valid in CLV mode. LC78622NE Command COMMAND INPUT NOISE REDUCTION MODE ...

Page 11

... CLV mode In CLV mode the LC78622NE detects the disk speed from the HF signal and provides proper linear speed using several different control schemes by switching the DSP internal modes. The PWM reference period corresponds to a frequency of 7.35 kHz. The V/P pin outputs a high level during rough servo and a low level during phase control. ...

Page 12

... Issuing the internal brake-on (C5H) command sets the LC78622NE to internal brake mode. In this mode, the disk deceleration state can be monitored from the WRQ pin when a brake command (06H) is executed. — In this mode the disk deceleration state is determined by counting the EFM signal density in a single frame, and when the EFM signal count falls under four, the CLV which functions as a brake completion monitor, goes high ...

Page 13

... Track Jump Circuit; Pin 15: HFL, pin 16: TES, pin 17: TOFF, pin 18: TGL, pin 19: JP • The LC78622NE supports the two track count modes listed below. MSB LSB The earlier track count function uses the TES signal directly as the internal track counter clock ...

Page 14

... The passage of the braking period (period c) completes the specified jump. During the braking period, the LC78622NE detects the beam slip direction from the TES and HFL inputs. TOFF is used to cut the components in the TES signal that aggravate slip. The jump destination track is captured by increasing the servo gain with TGL ...

Page 15

... While there was no braking period (the C period) in the LC78620E/21E for the new track jump command “2 TRACK JUMP IN (OUT)”, this has been changed in this LSI, which has a C period of 60 ms. The THLD signal is generated by the LA9230M, LA9231M, or LA9240M, and the tracking signal is held during the JP pulse period. LC78622NE 233 µ ...

Page 16

... The LC78622NE will count the specified number of tracks plus one when the microprocessor sends an arbitrary binary value in the range 8 to 254 after issuing either a track check track check out command. Note: Data for the desired track count must not be set to the general-purpose command $D9 to $DF. ...

Page 17

... W). Subcode data P is output on the fall of this signal. SBSY is a signal output for each subcode block. This signal goes high for the S0 and S1 synchronization signals. The fall of this signal indicates the end of the subcode synchronization signals and the start of the data in the subcode block. (EIAJ format) LC78622NE No. 6015-17/31 ...

Page 18

... Note: 1. Normally, the WRQ pin indicates the subcode Q standby state. However used for a different monitoring purpose in track check mode and during internal braking. (See the items on track counting and internal braking for details.) 2. The LC78622NE becomes active when the CS pin is low, and subcode Q data is output from the SQOUT pin. When the CS pin is high, the SQOUT pin goes to the high-impedance state. ...

Page 19

... When an Rch set (2AH) command is issued, the left and right channels both output the right channel data. 12. De-Emphasis; Pin 29: EMPH/CONT6 The preemphasis on/off bit in the subcode Q control information is output from the EMPH pin. When this pin is high, the LC78622NE internal de-emphasis circuit operates and the digital filters and the D/A converter output de- emphasized data. 13. Digital Attenuator Digital attenuation can be applied to the audio data by setting the RWC pin high and inputting the corresponding two-byte command to the COIN pin in synchronization with the CQCK clock ...

Page 20

... The IC defines zero cross to be the ranges where the upper 7 bits of the data are all zeros or all ones. Note that the MUTE -12 dB instruction supported by the LC78620E has been removed from this product. LC78622NE [dB] 100H ...

Page 21

... General-Purpose I/O Ports; Pin 24: CONT1, Pin 25: CONT2, Pin 26: CONT3, Pin 27: CONT4, Pin 28: CONT5, Pin 29: EMPH/CONT6, Pin 34: PCCL, Pin 35: MUTEL/CONT7, Pin 42: MUTER/CONT8 The LC78622NE provides five I/O ports CONT1 to CONT5 and three output ports CONT6 to CONT8. After a reset, these five I/O ports are set to function as input pins and the three output ports are set to function as EMPH, MUTEL, and MUTER pins, respectively ...

Page 22

... Both in normal- and double-speed playback modes, the 16M pin buffer outputs the 16.9344 MHz external crystal oscillator 16.9344 MHz signal. The 4.2M pin supplies the LA9240M or LA9241M system clock, normally outputting a 4.2336 MHz signal. When the oscillator is turned off both these pins will be fixed at either high or low. LC78622NE LSB Command ...

Page 23

... OSC Playback speed Digital filter normal speed Setting the RES pin low sets the LC78622NE to the settings enclosed in boxes in the table. 23. Other Pins; Pin 2:TAI, pin 64: TEST1, pin 11: TEST2, pin 32: TEST3, pin 33: TEST4, pin 62: TEST5, pin 59: TST11 These pins are used for testing the LSI’s internal circuits. Even though pull-down resistors are built into the TAI and TEST2 to TEST5 input pin circuits, these pins must be connected during normal operation ...

Page 24

... PCK side of the CLV servo circuit. If the ±4 frame buffer capacity is exceeded, the LC78622NE forcibly sets the write address to the ±0 position. However, since the errors that occur due to this operation cannot be handled with error flag processing, the IC applies muting to the output for a 128 frame period ...

Page 25

... OUT LC78622NE UBIT ON TJ mode UBIT OFF TJ mode DOUT ON ...

Page 26

... Note: VCO 2 SET command should be issued in case of low voltage power supply application. LC78622NE Double-speed playback FOCUS START # Normal-speed ...

Page 27

... Sample Application Circuit LC78622NE No. 6015-27/31 ...

Page 28

... 1.2 K 18K 16K – – 2fs (4) 5 (max 16MDRAM) 3.6 to 5.5 V 3.0 to 5.5 V QFP80E QFP64E DD LC78626E LC78622E LC78622NE (LC78626KE) Built-in VCO Built-in VCO 1.2 K 16K 16K 16K – – – 4fs 4fs 8fs (8fs) ( (3) ...

Page 29

... If a current output type pickup is used, locate the optical sensor connector and the ASP RF input as close together as possible voltage output type pickup is used, locate the I/V conversion resistor as close to the ASP RF input side as possible. LC78622NE DD and output V /V values ...

Page 30

... Since this IC is specifically designed for use in CD players, its specifications differ from those of standard logic and other general-purpose IC products. We recommend adopting failsafe design techniques in the applications, and we also recommend debugging applications in the application equipment itself. LC78622NE or ground DD No. 6015-30/31 ...

Page 31

... SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of January, 1999. Specifications and information herein are subject to change without notice. LC78622NE PS No. 6015-31/31 ...

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