P87C51RD2BA

Manufacturer Part NumberP87C51RD2BA
Description357-036-542-201 CARDEDGE 36POS DL .156 BLK LOPRO
ManufacturerNXP Semiconductors
P87C51RD2BA datasheets

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Philips Semiconductors
80C51 8-bit microcontroller family
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high
speed (30/33 MHz)
CMOD Address = D9H
CIDL
WDTE
Bit:
7
6
Symbol
Function
CIDL
Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs
it to be gated off during idle.
WDTE
Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it.
–
Not implemented, reserved for future use.*
CPS1
PCA Count Pulse Select bit 1.
CPS0
PCA Count Pulse Select bit 0.
CPS1
CPS0
Selected PCA Input**
0
0
0
0
1
1
1
0
2
1
1
3
ECF
PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables
that function of CF.
NOTE:
* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive
value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
** f
= oscillator frequency
OSC
CCON Address = D8H
Bit Addressable
CF
CR
Bit:
7
6
Symbol
Function
CF
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is
set. CF may be set by either hardware or software but can only be cleared by software.
CR
PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA
counter off.
–
Not implemented, reserved for future use*.
CCF4
PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF3
PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF2
PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF1
PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
CCF0
PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.
NOTE:
* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive
value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
2003 Jan 24
8KB/16KB/32KB/64KB OTP
–
–
–
CPS1
5
4
3
2
Internal clock, f
/6 in 6-clock mode (f
OSC
OSC
Internal clock, f
/2 in 6-clock mode (f
OSC
OSC
Timer 0 overflow
External clock at ECI/P1.2 pin
(max. rate = f
/4 in 6-clock mode, f
OSC
OCS
Figure 22. CMOD: PCA Counter Mode Register
–
CCF4
CCF3
CCF2
5
4
3
2
Figure 23. CCON: PCA Counter Control Register
35
Product data
P87C51RA2/RB2/RC2/RD2
Reset Value = 00XX X000B
CPS0
ECF
1
0
/12 in 12-clock mode)
/4 in 12-clock mode)
/8 in 12-clock mode)
SU01318
Reset Value = 00X0 0000B
CCF1
CCF0
1
0
SU01319

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