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P87C51RD2BA
P87C51RD2BA | |
|---|---|
| Manufacturer Part Number | P87C51RD2BA |
| Description | 357-036-542-201 CARDEDGE 36POS DL .156 BLK LOPRO |
| Manufacturer | NXP Semiconductors |
| P87C51RD2BA datasheets |
|
Availability: In stock
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Warranty: 60 days
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PrevNext
Philips Semiconductors
80C51 8-bit microcontroller family
with 512B/1KB RAM, low voltage (2.7 to 5.5 V), low power, high
speed (30/33 MHz)
AC ELECTRICAL CHARACTERISTICS (12-CLOCK MODE, 5 V 10% OPERATION)
T
= 0 C to +70 C or –40 C to +85 C ; V
amb
Symbol
Figure
Parameter
1/t
38
Oscillator frequency
CLCL
t
34
ALE pulse width
LHLL
t
34
Address valid to ALE low
AVLL
t
34
Address hold after ALE low
LLAX
t
34
ALE low to valid instruction in
LLIV
t
34
ALE low to PSEN low
LLPL
t
34
PSEN pulse width
PLPH
t
34
PSEN low to valid instruction in
PLIV
t
34
Input instruction hold after PSEN
PXIX
t
34
Input instruction float after PSEN
PXIZ
t
34
Address to valid instruction in
AVIV
t
34
PSEN low to address float
PLAZ
Data Memory
t
35
RD pulse width
RLRH
t
36
WR pulse width
WLWH
t
35
RD low to valid data in
RLDV
t
35
Data hold after RD
RHDX
t
35
Data float after RD
RHDZ
t
35
ALE low to valid data in
LLDV
t
35
Address to valid data in
AVDV
t
35, 36
ALE low to RD or WR low
LLWL
t
35, 36
Address valid to WR low or RD low
AVWL
t
36
Data valid to WR transition
QVWX
t
36
Data hold after WR
WHQX
t
36
Data valid to WR high
QVWH
t
35
RD low to address float
RLAZ
t
35, 36
RD or WR high to ALE high
WHLH
External Clock
t
38
High time
CHCX
t
38
Low time
CLCX
t
38
Rise time
CLCH
t
38
Fall time
CHCL
Shift register
t
37
Serial port clock cycle time
XLXL
t
37
Output data setup to clock rising edge
QVXH
t
37
Output data hold after clock rising edge
XHQX
t
37
Input data hold after clock rising edge
XHDX
t
37
Clock rising edge to input data valid
XHDV
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all outputs = 80 pF
3. Interfacing the microcontroller to devices with float time up to 45 ns is permitted. This limited bus contention will not cause damage to port 0
drivers.
4. Parts are guaranteed by design to operate down to 0 Hz.
5. Below 16 MHz this parameter is 8 t
– 133.
CLCL
2003 Jan 24
8KB/16KB/32KB/64KB OTP
1,2,3,4
= 5 V 10%, V
= 0 V
CC
SS
Limits
MIN
0
2 t
–8
CLCL
t
–13
CLCL
t
–20
CLCL
t
–10
CLCL
3 t
–10
CLCL
0
6 t
–20
CLCL
6 t
–20
CLCL
0
3 t
–15
CLCL
4 t
–15
CLCL
t
–25
CLCL
t
–15
CLCL
7 t
–5
CLCL
t
–10
CLCL
0.32 t
CLCL
0.32 t
CLCL
12 t
CLCL
10 t
–25
CLCL
2 t
–15
CLCL
0
5
46
Product data
P87C51RA2/RB2/RC2/RD2
Unit
16 MHz Clock
MAX
MIN
MAX
33
MHz
117
ns
49.5
ns
42.5
ns
4 t
–35
215
ns
CLCL
52.5
ns
177.5
ns
3 t
–35
152.5
ns
CLCL
0
ns
t
–10
52.5
ns
CLCL
5 t
–35
277.5
ns
CLCL
10
10
ns
355
ns
355
ns
5 t
–35
277.5
ns
CLCL
0
ns
2 t
–10
115
ns
CLCL
8 t
–35
465
ns
CLCL
9 t
–35
527.5
ns
CLCL
3 t
+15
172.5
202.5
ns
CLCL
235
ns
37.5
ns
47.5
ns
432.5
ns
0
0
ns
t
+10
52.5
72.5
ns
CLCL
t
– t
ns
CLCL
CLCX
t
– t
ns
CLCL
CHCX
5
ns
5
ns
750
ns
600
ns
110
ns
0
ns
10 t
–133
492
ns
CLCL
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