ALC262 REALTEK, ALC262 Datasheet
ALC262
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ALC262 Summary of contents
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... ALC262-GR ALC262-VB Series (ALC262-VB0-GR, ALC262SRS-GR, ALC262H-GR) ALC262-VC Series (ALC262-VC1-GR, ALC262-VC2-GR) ALC262-VD Series (ALC262-VD2-GR, ALC262W-VD2-GR) 4-CHANNEL DAC AND 6-CHANNEL ADC HIGH DEFINITION AUDIO CODEC DATASHEET Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211. Fax: +886-3-577-6047 www ...
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... USING THIS DOCUMENT This document is intended for the hardware and software engineer’s general information on the Realtek ALC262 Series Audio Codecs. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process ...
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... Meets Intel low power ECR compliant and power status control for all analog converter and pin widgets. See section 7.5 Power Management, page 28. 1.9 2008/04/15 Added information for all ALC262 series (version A/B/C/D). Added part number ALC262W-VD2-GR in section 12 Ordering Information, page 78. 4-Ch DAC and 6-Ch ADC High Definition Audio Code nd SPDIF output: iii ...
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... Codec Reset ..........................................................................................................................................................25 7.3.3. Codec Initialization Sequence ..............................................................................................................................26 7. ERB AND ESPONSE 7.4.1. Command Verb Format........................................................................................................................................27 7.4.2. Response Format..................................................................................................................................................27 7. ...............................................................................................................................................28 OWER ANAGEMENT 7.5.1. ALC262 A/B/C Versions .......................................................................................................................................28 7.5.2. ALC262 D Version ...............................................................................................................................................29 4-Ch DAC and 6-Ch ADC High Definition Audio Code Table of Contents ................................................................................................................................................3 ................................................................................................................................................6 U .....................................................................................................................................9 NIT ..............................................................................................................................................10 I ......................................................................................................10 ERSION DENTIFICATION I ......................................................................................................11 ERSION DENTIFICATION I ...
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... Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h) ........................36 8.1.12. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh) .......................................................37 8.1.13. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) (ALC262 A/B/C Version) ........37 8.1.14. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) (ALC262 D Version) ...............38 8.1.15. ...
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... ID=F0F IDGET H ERB ID=F20 /723 ~720 ERB H H ............................................................................................................................................ .........................................................................................73 XTERNAL ARIABLE ESISTOR GPIO0/GPIO1.....................................................................................................................74 .................................................................................................................74 MPLEMENTATION N ............................................................................................................................77 OTES vi ALC262 Series 2 (V ID=F0D , F0E )...........................................64 ERB ID=70D , 70E )............................................65 ERB H H /70F ) .................................................................... [31:0])..................................................... Track ID: JATR-1076-21 Datasheet Rev. 1.9 ...
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... ID=09 ).............................................33 H ARAMETER ID=0A ) ...........................................34 H ARAMETER ID=0B )...........................................35 H ARAMETER H ID=0C ) ............................................................... ID=0D NPUT MPLIFIER ARAMETER A P ID=12 UTPUT MPLIFIER ARAMETER ID=0E ) ...................................................... ID=0F ) (ALC262 A/B/C V ARAMETER ID=0F ) (ALC262 D V ARAMETER H ID=10 )..................................................38 ARAMETER H ID=11 ) ............................................................ ID=13 ) .............................................39 H ARAMETER H ) ................................................................................ ................................................................51 ERSION )........................................................................52 ERSION Track ID: JATR-1076-21 Datasheet ~1F ................ )....................... ....................36 H ).....37 ERSION ) ...
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... ID=F0F IDGET H ERB ID=F20 / 723 ~720 ERB H H ................................................................................................................................67 ATINGS ...........................................................................................................................68 C ................................................................................................................68 HARACTERISTICS T ..................................................................................................................69 IMING C ...............................................................................................................70 ODEC T ..........................................................................................................................71 IMING ............................................................................................................................................72 ..........................................................................................................................................78 viii ALC262 Series ) ................................................................................ ........................................................................... ............................................................................56 H ID=71C /71D /71E /71F FOR (V ID=F19 ) .........................................................62 ERB H (V ID=719 )..........................................................63 ERB ID=F0D , F0E )...........................................64 ERB ...
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... ALC262 C V IGURE LOCK IAGRAM – ALC262 D V IGURE LOCK IAGRAM IGURE NALOG NPUT UTPUT F 5. ALC262 A/B V IGURE ERSION F 6. ALC262 IGURE ERSION ALC262 IGURE ERSION HDA L P ...............................................................................................................................................15 IGURE INK ROTOCOL ................................................................................................................................................................16 IGURE IT ...
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... All analog IO are input and output capable and can be re-tasked according to user’s definitions. Headphone amplifiers are also integrated at analog output ports and F. The ALC262 series supports 16/20/24 S/PDIF input and output to offer easy connection of PCs to high quality consumer electronic products such as digital decoders and speakers ...
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... PCB layout and radio frequency devices • The ALC262 C supports scalable I/O voltage (1.5V to 3.3V HDA link, which will be a requirement in future chipsets designed for low voltage operation. The ALC262 D supports a secondary S/PDIF output converter and a dedicated output pin (S/PDIF-OUT2 HDMI transmitter, and all ADCs support up to192K sample rate and 24-bit PCM format. The ALC262 D version conforms to Intel’ ...
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... Front-Out-Left and Front-Out-Right channels Three stereo ADCs support 16/20-bit PCM for multiple input streaming (ALC262A/B/C versions) Three stereo ADCs support 16/20/24-bit PCM for multiple input streaming (ALC262D version) All DACs supports 44.1/48/96/192kHz sample rate All ADCs support 44 ...
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... Supports low voltage (1.5V~3.3V) IO for HDA link (ALC262 C/D version) Supports stereo digital microphone input (ALC262 C/D version) Supports 2nd S/PDIF output. (ALC262 D version) Intel low power ECR compliant and power status control for all widgets (ALC262 D version) 2.2. Software Features Meets Microsoft Windows Logo Program requirements EAX™ ...
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... TrueSurround HD (optional software feature) ® Fortemedia SAM™ technology for voice processing (Beam Forming and Acoustic Echo Cancellation) (optional software feature) MaxxAudio technologies from Waves (optional software feature, ALC262-VD2 only) 3. System Applications Multimedia desktop and laptop PCs Information appliances (IA) 4-Ch DAC and 6-Ch ADC High Definition Audio Code ...
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... Block Diagram 4.1. ALC262 A/B Version Figure 1. 4-Ch DAC and 6-Ch ADC High Definition Audio Code Block Diagram – ALC262 A/B Version 6 ALC262 Series Datasheet Track ID: JATR-1076-21 Rev. 1.9 ...
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... ALC262 C Version Note: The ALC262 C Version supports digital MIC (DMIC-CLK, DMIC-DATA). 4-Ch DAC and 6-Ch ADC High Definition Audio Code Figure 2. Block Diagram – ALC262 C Version 7 ALC262 Series Datasheet Track ID: JATR-1076-21 Rev. 1.9 ...
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... ALC262 D Version Note: The ALC262 D Version supports digital MIC (DMIC-CLK, DMIC-DATA) and S/DPIF-OUT2. 4-Ch DAC and 6-Ch ADC High Definition Audio Code Figure 3. Block Diagram – ALC262 D Version 8 ALC262 Series Datasheet Track ID: JATR-1076-21 Rev. 1.9 ...
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... Analog Input/Output Unit Pin Complex widgets NID=14h~16h, 18h~1Bh are re-tasking IO. Output_Signal_Left Output_Signal_Right Input_Signal_Left Input_Signal_Right 4-Ch DAC and 6-Ch ADC High Definition Audio Code A R EN_OBUF EN_AMP R EN_OBUF EN_IBUF Figure 4. Analog Input/Output Unit 9 ALC262 Series Datasheet Left Right Track ID: JATR-1076-21 Rev. 1.9 ...
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... Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 5. The version number is shown in the location marked ‘VV’. For example, ‘VV=B0’ indicates silicon version ‘B’ and stepping version ‘0’, which is the first stepping of the ALC262 version B. 4-Ch DAC and 6-Ch ADC High Definition Audio Code ...
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... Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 6. The version number is shown in the location marked ‘VV’. For example, ‘VV=C0’ indicates silicon version ‘C’ and stepping version ‘0’, which is the first stepping of the ALC262-VC. 4-Ch DAC and 6-Ch ADC High Definition Audio Code Figure 6 ...
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... Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 7. The version number is shown in the location marked ‘VV’. For example, ‘VV=D0’ indicates silicon version ‘D’ and stepping version ‘0’, which is the first stepping of the ALC262-VD. 4-Ch DAC and 6-Ch ADC High Definition Audio Code Figure 7 ...
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... Stereo Microphone Input Left Channel nd 2 Stereo Microphone Input Right Channel CD Input Left Channel CD Input Reference Ground CD Input Right Channel st 1 Stereo Microphone Input Left Channel 13 ALC262 Series Characteristic Definition V =0.5*DVDD t Schmitt trigger input, V =1.0V Schmitt trigger input, V =1.0V ...
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... Analog GND Digital VDD (3.3V) Digital GND Digital VDD (3.3V) Digital VDD (1.5V~3.3V) Digital GND 14 ALC262 Series Characteristic Definition Analog input/output, default is input (PORT-B) Analog input/output, default is input (PORT-C) Analog input/output, default is input (PORT-C) Analog input, 1.6Vrms of full scale input Analog output (PORT-D) Analog output (PORT-D) ...
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... HDA controller. The input and output streams, including command and PCM data, are isochronous with a 48kHz frame rate. Figure 8 shows the basic concept of the HDA link protocol. 4-Ch DAC and 6-Ch ADC High Definition Audio Code Figure 8. HDA Link Protocol 15 ALC262 Series Datasheet Track ID: JATR-1076-21 Rev. 1.9 ...
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... Start of Frame 999 998 997 996 995 994 993 992 991 990 499 498 Codec samples SDO at both rising and falling edge of BCLK Figure 9. Bit Timing 16 ALC262 Series Datasheet 497 496 495 494 Track ID: JATR-1076-21 Rev. 1.9 ...
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... The multiple SDOs and multiple SDIs are used to expand the transmission rate between controller and codecs. Section 7.2 Frame Composition, page 18, describes the detailed outbound and inbound stream compositions for single and multiple SDOs/SDIs. The connections shown in Figure 10 can be implemented concurrently in an HDA system. The ALC262 is designed to receive a single SDO stream. SDI14 ...
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... Stream Tag msb lsb Preamble Stream=10 (4-Bit) (4-Bit Previous Stream 18 ALC262 Series Next Frame Stream 'X' Tag (Here ' Stream 'X' Data Padded at the Null Field end of Frame time of samples, Block2 th time of samples th Data of Stream 10 Track ID: JATR-1076-21 Datasheet ...
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... SDO1 is for transmitting a striped stream. The codec does not support multiple SDOs connected to SDO0. To guarantee all codecs can determine their corresponding stream, the command stream is not striped always transmitted on SDO0, and copied on SDO1. 4-Ch DAC and 6-Ch ADC High Definition Audio Code Figure 13. Striped Stream on Multiple SDOs 19 ALC262 Series Datasheet Track ID: JATR-1076-21 Rev. 1.9 ...
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... Data Length in Bytes n-1 A Complete Stream Figure 15. SDI Stream Tag and Data 20 ALC262 Series Next Frame Stream 'X' 0s Null Field Padded at the end of Frame (N+1) th Null Pad n-2 0 (Data Length in Bytes *8)-Bit Track ID: JATR-1076-21 ...
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... The appropriate ratio between 44.1kHz and 48kHz is 147/160. Meaning 147 sample blocks are transmitted every 160 frames. 4-Ch DAC and 6-Ch ADC High Definition Audio Code Stream 'A' Tag A Data A Stream 'X' Stream 'B' Tag B Data B Stream and Y are independent and have separate IDs 21 ALC262 Series Stream ' Track ID: JATR-1076-21 Datasheet Rev. 1.9 ...
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... One sample block is transmitted in every 4 frames One sample block is transmitted in every 3 frames One sample block is transmitted in every 6 frames One sample block is transmitted in every 6 frames Two sample blocks are transmitted in each frame Four sample blocks are transmitted in each frame 22 ALC262 Series Datasheet Track ID: JATR-1076-21 Rev. 1.9 ...
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... DAC and 6-Ch ADC High Definition Audio Code 44.1kHz Variable Rate of Delivery Timing -11 -12 -11 -11 -12 -11 -11 -11 - (repeat -11 -12 -11 -11 -12 -11 -11 -11 - (repeat) 23 ALC262 Series Datasheet Track ID: JATR-1076-21 Rev. 1.9 ...
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... The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low The controller asserts the RST# signal to low, and enters the ‘Link Reset’ state All link signals driven by controller and codecs should be tri-state by internal pull low resistors 4-Ch DAC and 6-Ch ADC High Definition Audio Code 24 Track ID: JATR-1076-21 ALC262 Series Datasheet Rev. 1.9 ...
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... After the target codec completes its reset operation, an initialization sequence is requested. In ALC262 D version, the extend power state of conforming to Intel low power ECR the function reset could not initialize the register setting. Host SW needs to send ‘two’ function reset consecutively to reset all settings ...
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... The codec will stop driving the SDI during this turnaround period. The controller drives SDI to assign a CAD to the codec. The controller releases the SDI after the CAD has been assigned. Normal operation state 4-Ch DAC and 6-Ch ADC High Definition Audio Code Figure 18. Codec Initialization Sequence 26 ALC262 Series Datasheet Track ID: JATR-1076-21 Rev. 1.9 ...
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... DAC and 6-Ch ADC High Definition Audio Code Bit [27:20] Node ID Bit [27:20] Node ID Table 12. Solicited Response Format Bit [34] Bit [33:32] Unsol=0 Reserved Table 13. Unsolicited Response Format Bit [33:32] Reserved 27 ALC262 Series Datasheet Bit [19:16] Bit [15:0] Verb ID Payload Bit [19:8] Bit [7:0] Verb ID Payload Bit [31:0] Response Bit [31:28] Bit [27:0] Tag ...
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... ALC262 A/B/C Versions The ALC262 does not support Wake-Up events when in low power mode. All power management state changes in widgets are driven by software. Table 14 shows the System Power State Definitions. In the ALC262, all the widgets include output/input converters support power control. Software may have various power states depending on system configuration ...
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... The ALC262-VD minimizes D3 state idle mode power consumption and increases overall battery life in mobile systems mode, only a power on reset or a ‘double function reset’ resets all ALC262-VD settings, cutting software configuration time spent entering/leaving D3 state, and reducing latency time for transitions ...
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... All power management state changes in widgets are driven by software. Table 17 indicates the definitions of power states. In the ALC262-VD, the Audio Function (NID=01h), input converter, output converter, and each pin widget supports power control. Software may have various power states dependent on system configuration. Table 17 indicates those Nodes that support power management. To simplify power control, software can configure whole codec power states using only the Audio Function (NID=01h) ...
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... Mixers powered down Reference power down 8. Supported Verbs and Parameters This section describes the Verbs and Parameters supported by various widgets in the ALC262 verb is not supported by the addressed widget, it will respond with 32 bits of ‘0’. 8.1. Verb – Get Parameters (Verb ID=F00h) The ‘ ...
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... Codec Response Format Bit Description 31:24 Reserved. Read as 0’s. 23:20 MajRev. The major version number (in decimal) of the HDA Spec to which the ALC262 is fully compliant. 19:16 MinRev. The minor version number (in decimal) of the HDA Spec to which the ALC262 is fully compliant. 15:8 Revision ID. The vendor’s revision number. ...
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... OutAmpPre, Out AMP Present. 1 InAmpPre, In AMP Present. 0 Stereo. 0: Mono Widget 4-Ch DAC and 6-Ch ADC High Definition Audio Code 1h: Audio Input 2h: Mixer 4h: Pin Complex 5h: Power Widget 7h~Eh: Reserved Fh: Vendor defined audio widget 1: Unsolicited response is supported 1: Processing control is supported 1: Stereo Widget 33 ALC262 Series Datasheet Track ID: JATR-1076-21 Rev. 1.9 ...
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... Not supported 0 R1: Indicates whether 8kHz (=1/6*48kHz) rate is supported. 0: Not supported 4-Ch DAC and 6-Ch ADC High Definition Audio Code 1: Supported 1: Supported 1: Supported 1: Supported 1: Supported 1: Supported 1: Supported 1: Supported 1: Supported 1: Supported 1: Supported 1: Supported 1: Supported 1: Supported 1: Supported 1: Supported 1: Supported 34 ALC262 Series Datasheet Track ID: JATR-1076-21 Rev. 1.9 ...
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... Note: Only Pin Complex widgets support this parameter. 4-Ch DAC and 6-Ch ADC High Definition Audio Code 1: Supported 1: Supported 1: Supported 100% 80% Reserved 35 ALC262 Series Datasheet Ground 50% Hi-Z Track ID: JATR-1076-21 Rev. 1.9 ...
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... Reserved. Read as 0. 14:8 Number of Steps. Indicates the number of steps in the gain range. ‘0’ means the gain is fixed. 7 Reserved. Read as 0. 6:0 Offset. Indicates which step is 0dB. 4-Ch DAC and 6-Ch ADC High Definition Audio Code 36 Track ID: JATR-1076-21 ALC262 Series Datasheet Rev. 1.9 ...
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... Indicates the number of inputs connected to a widget. If the Connect List Length is 1, there is only one input, and there is no Connection Select Control (Not a MUX widget). 8.1.13. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) (ALC262 A/B/C Version) Table 32. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) (ALC262 A/B/C Version) Bit Description 31:4 Reserved. Read as 0’s. ...
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... Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) (ALC262 D Version) The ALC262 version D is designed to meet Intel’s low-power-state white paper and is ECR HDA-015B compliant. Table 33. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) (ALC262 D Version) Codec Response Format ...
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... Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h) Table 35. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h) Codec Response Format Bit Description 31 GPIWake=0. The ALC262 does not support GPIO wake up function. 30 GPIUnsol=1. The ALC262 supports GPIO unsolicited response. 29:24 Reserved. Read as 0’s. 23:16 NumGPIs=00h. ...
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... Codec Response for Digital Pin S/PDIF-OUT Bit Description 31:8 0’s. 7:0 Connection Index Currently Set (Default value is 00h). 00h: Digital Converter (S/PDIF-OUT) Codec Response for Digital Pin S/PDIF-OUT2 (ALC262 D version only) Bit Description 31:8 0’s. 7:0 Connection Index Currently Set (Default value is 00h). 00h: Digital Converter (S/PDIF-OUT) ...
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... Returns 1Fh (S/PDIF-IN Pin Widget) for N=0~3. 4-Ch DAC and 6-Ch ADC High Definition Audio Code Bit [19:8] Payload Bit [7:0] Select Index [7:0] Bit [19:8] Payload Bit [7:0] Offset Index - N[7:0] 41 ALC262 Series Codec Response Format Response [31:0] 0’s for all nodes Codec Response Format Response [31:0] 32-bit Response Returns 00h for N>3. Returns 00h for N>3. ...
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... DAC and 6-Ch ADC High Definition Audio Code Returns 00h for N>3. Returns 00h for N>3. Returns 00h for N>7. Returns 00h for N>7. Returns 00h for N>3. Returns 00h for N>3. Returns 00h for N>3. Returns 00h for N>3. Returns 00h for N>3. Returns 00h for N>3. 42 Track ID: JATR-1076-21 ALC262 Series Datasheet Rev. 1.9 ...
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... Returns 0000h. 15:8 Connection List Entry (N+1). Returns 00h for N>3. 7:0 Connection List Entry (N). Returns 06h (S/PDIF-OUT converter) for N=0~3. Returns 00h for N>3. Codec Response for NID=11h (Pin Widget: S/PDIF-OUT2 for ALC262 D Version) Bit Description 31:16 Connection List Entry (N+3) and (N+2). Returns 0000h. 15:8 Connection List Entry (N+1). ...
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... DAC and 6-Ch ADC High Definition Audio Code Bit [19:8] Payload Bit [7:0] 0’s Bit [19:8] Payload Bit [7:0] Processing State [7:0] 44 ALC262 Series Returns 00h for N>7. Returns 00h for N>7. Returns 00h for N>7. Returns 1Ch (Pin Complex - CD) for N=4~7. Returns 00h for N>11. Codec Response Format Response [31:0] 32-bit response ...
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... Payload Bit [15:0] Verb ID=Dh 0’s Bit [19:16] Payload Bit [15:0] Verb ID=5h Coefficient Index [15:0] Bit [19:16] Payload Bit [15:0] Verb ID=Ch 0’s 45 ALC262 Series Datasheet Codec Response Format Response [31:0] Bit [15:0] are Coefficient Index Codec Response Format Response [31:0] 0’s for all nodes Codec Response Format Response [31:0] Processing Coefficient [15:0] Track ID: JATR-1076-21 ...
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... DAC and 6-Ch ADC High Definition Audio Code Bit [19:16] Payload Bit [15:0] Verb ID=4h Coefficient [15:0] Bit [19:16] Payload Bit [15:0] Verb ID=Bh ‘Get’ payload [15:0] 46 ALC262 Series Codec Response Format Response [31:0] 0’s for all nodes Codec Response Format Response [31:0] Bit[7:0] are responsible for ‘Get’ 1: Left amplifier gain is requested Track ID: JATR-1076-21 Datasheet ...
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... Bit- ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Gain). Bit- ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain). Codec Response to Other NID Bit Description 31:0 Not Supported (returns 00000000h). 4-Ch DAC and 6-Ch ADC High Definition Audio Code 1: Mute 1:Mute (Default=1) 1: Mute 47 ALC262 Series Datasheet Track ID: JATR-1076-21 Rev. 1.9 ...
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... Mute. 0: Unmute 1: Mute (-∞gain) 6:0 Gain[6:0]. A 7-bit step value specifying the amplifier gain. 4-Ch DAC and 6-Ch ADC High Definition Audio Code Bit [19:8] Payload Bit [7:0] Verb ID=3h ‘Set’ payload [7:0] 48 ALC262 Series Datasheet Codec Response Format Response [31:0] 0’s for all nodes Track ID: JATR-1076-21 Rev. 1.9 ...
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... Sample Base Rate (BASE). 0: 48kHz 13:11 Sample Base Rate Multiple (MULT). 000b: *1 10:8 Sample Base Rate Divisor (DIV). 000b: /1 100b: /5 The ALC262 does not support Divisor. Always read as 000b. 7 Reserved. Read as 0. 6:4 Bits per Sample (BITS). 000b: 8 bits 100b: 32 bits 3:0 Number of Channels channel ...
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... Reserved 1: 2 channels 2: 3 channels 50 ALC262 Series Datasheet Codec Response Format Response [31:0] 0’s for all nodes 011b: *4 100b~111b: Reserved. 011b: /4 111b: /8 011b: 24 bits ……… 15: 16 channels Track ID: JATR-1076-21 ...
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... Verb – Get Power State (Verb ID=F05h) (ALC262 A/B/C Version) Table 50. Verb – Get Power State (Verb ID=F05h) (ALC262 A/B/C Version) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Codec Response for NID=01h (Audio Function Group) Bit Description 31:6 Reserved. Read as 0’s. 5:4 PS-Act. Actual Power State [1:0]. ...
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... Verb – Get Power State (Verb ID=F05h) (ALC262 D Version) Table 51. Verb – Get Power State (Verb ID=F05h) (ALC262 D Version) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Codec Response for NID=01h (Audio Function Group) Codec Response for NID=02h, 03h, 07h, 08h, 09h (Analog Input/Output Converter) ...
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... Payload Bit [7:0] Power State [7:0] 01: Power state is D1 11: Power state is D3 01: Power state is D1 11: Power state is D3 Bit [19:8] Payload Bit [7:0] 0’s 53 ALC262 Series Datasheet Codec Response Format Response [31:0] 0’s for all nodes Codec Response Format Response [31:0] Stream & Channel [7:0] Track ID: JATR-1076-21 Rev. 1.9 ...
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... Payload Bit [7:0] Stream & Channel [7:0] Bit [19:8] Payload Bit [7:0] 0’s 1: Enabled 1: Enabled 1: Enabled 001b: 50% of AVDD 100b: 80% of AVDD 54 ALC262 Series Datasheet Codec Response Format Response [31:0] 0’s for all nodes Codec Response Format Response [31:0] Pin Control [7:0] 010b: Ground 0V 101b: 100% of AVDD Track ID: JATR-1076-21 ...
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... Pin Control [7:0] 1: Enabled 1: Enabled 1: Enabled 001b: 50% of AVDD 100b: 80% of AVDD Bit [19:8] Payload Bit [7:0] 0’s 1: Enabled 55 ALC262 Series Datasheet Codec Response Format Response [31:0] 0’s for all nodes 010b: Ground 0V 101b: 100% of AVDD Codec Response Format Response [31:0] 32-bit Response Track ID: JATR-1076-21 Rev. 1.9 ...
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... DAC and 6-Ch ADC High Definition Audio Code Bit [19:8] Payload Bit [7:0] EnableUnsol [7:0] Table 58. Verb – Get Pin Sense (Verb ID=F09h) Bit [19:8] Payload Bit [7:0] 0’s 56 ALC262 Series Datasheet Codec Response Format Response [31:0] 0’s for all nodes Codec Response Format Response [31:0] 32-bit Response Track ID: JATR-1076-21 ...
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... Note: The 32-bit registers for each Pin Widget are sticky and will not be reset by a LINK Reset or Codec Reset (Function Reset Verb). 4-Ch DAC and 6-Ch ADC High Definition Audio Code Bit [19:8] Payload Bit [7:0] Right Channel[0] Bit [19:8] Payload Bit [7:0] 0’s 57 ALC262 Series Datasheet Codec Response Format Response [31:0] 0’s for all nodes Codec Response Format Response [31:0] 32-bit Response Track ID: JATR-1076-21 Rev. 1.9 ...
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... Bit Description 31:0 0’s. 4-Ch DAC and 6-Ch ADC High Definition Audio Code Bit [19:8] Payload Bit [7:0] Verb ID=71Ch, Label [7:0] Bit [19:8] Payload Bit [7:0] Verb ID=F1Bh 0’s 58 ALC262 Series Datasheet Codec Response Format Response [31:0] 0’s for all nodes Codec Response Format Response [31:0] Divider [7:0] Track ID: JATR-1076-21 Rev. 1.9 ...
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... DAC and 6-Ch ADC High Definition Audio Code Bit [19:8] Payload Bit [7:0] Divider [7:0] Table 64. Verb – Get GPIO Data (Verb ID=F15h) Bit [19:8] Payload Bit [7:0] 0’s 59 ALC262 Series Datasheet Codec Response Format Response [31:0] 0’s for all nodes Codec Response Format Response [31:0] 32-bit Response Track ID: JATR-1076-21 ...
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... DAC and 6-Ch ADC High Definition Audio Code Table 65. Verb – Set GPIO Data (Verb ID=715h) Bit [19:8] Payload Bit [7:0] Data [7:0] Bit [19:8] Payload Bit [7:0] 0’s 60 ALC262 Series Datasheet Codec Response Format Response [31:0] 0’s for all nodes Codec Response Format Response [31:0] EnableMask [7:0] Track ID: JATR-1076-21 ...
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... Codec Response for Other NID Bit Description 31:0 0’s. 4-Ch DAC and 6-Ch ADC High Definition Audio Code Bit [19:8] Payload Bit [7:0] Enable Mask [7:0] Bit [19:8] Payload Bit [7:0] 0’s 61 ALC262 Series Datasheet Codec Response Format Response [31:0] 0’s for all nodes Codec Response Format Response [31:0] Direction [7:0] Track ID: JATR-1076-21 Rev. 1.9 ...
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... Codec Response for Other NID Bit Description 31:0 0’s. 4-Ch DAC and 6-Ch ADC High Definition Audio Code Bit [19:8] Payload Bit [7:0] Direction [7:0] Bit [19:8] Payload Bit [7:0] 0’s 62 ALC262 Series Datasheet Codec Response Format Response [31:0] 0’s for all nodes Codec Response Format Response [31:0] UnsolEnable [7:0] Track ID: JATR-1076-21 Rev. 1.9 ...
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... Node ID=01h Verb ID=7FFh Codec Response Bit Description 31:0 Reserved. Read as 0’s. Note: The Function Reset command causes all widgets in the ALC262 to return to their power on default state. 4-Ch DAC and 6-Ch ADC High Definition Audio Code Bit [19:8] Payload Bit [7:0] UnsolEnable [7:0] Bit [19:8] Payload Bit [7:0] 0’ ...
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... Professional format 1: AC3 or other digital non-audio data 1: Not asserted 1: Filter pre-emphasis is 50/15 microseconds Professional format 1: AC3 or other digital non-audio data 1: Not asserted 1: Filter pre-emphasis is 50/15 microseconds 64 ALC262 Series Datasheet Codec Response Format Response [31:0] Bit[31:16]=0’s, Bit[15:0] are SIC bit Track ID: JATR-1076-21 Rev. 1.9 ...
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... DAC and 6-Ch ADC High Definition Audio Code Bit [19:8] Payload Bit [7:0] SIC [7:0] Bit [19:8] Payload Bit [7:0] SIC [15:8] 1: Professional format 1: AC3 or other digital non-audio data 1: Not asserted 1: Filter pre-emphasis is 50/15 microseconds ALC262 Series Datasheet Codec Response Format Response [31:0] 0’s Codec Response Format Response [31:0] 0’s Track ID: JATR-1076-21 Rev. 1.9 ...
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... DAC and 6-Ch ADC High Definition Audio Code Bit [19:8] Payload Bit [7:0] 0’s Bit [19:8] Payload Bit [7:0] Bit[7] is ‘Direct’ control Bit [19:8] Payload Bit [7:0] 0’s 66 ALC262 Series Datasheet Codec Response Format Response [31:0] Bit[31:8]=0’s, Bit[7:0] is volume Codec Response Format Response [31:0] 0’s Codec Response Format Response [31:0] 32 bits response Track ID: JATR-1076-21 Rev ...
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... Ts - ESD (Electrostatic Discharge) =25°C, with 50pF external load. Table 78. Threshold Voltage Symbol Minimum V -0. 0.65*DVDD- 0.56*DVDD IH (1.85) V 0.9*DVDD- - ALC262 Series Typical Maximum 3.3 3.6 3.3 3.6 3.3 5.5 - +70 - +125 Susceptibility Voltage 3000V 4000V Typical Maximum - DVDD +0.30 - 0.30*DVDD- 0.44*DVDD (1.45 0.1*DVDD- ...
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... DAC and 6-Ch ADC High Definition Audio Code Table 79. Digital Filter Characteristics Minimum 0 0.6* 0.6* Table 80. S/PDIF Input/Output Characteristics Symbol Minimum ALC262 Series Datasheet Typical Maximum - 19.2 (-3dB) 0.458*Fs (-1dB -76.0 - ±0. ±0.05 - 19.2 (-3dB) - 0.435*Fs (-1dB -78.5 - ±0. ±0.03 Typical Maximum 3 ...
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... DAC and 6-Ch ADC High Definition Audio Code Table 81. Link Reset and Initialization Timing Symbol Minimum T 1.0 RST T 20 PLL T - FRAME 4 BCLK T RST Figure 20. Link Reset and Initialization Timing 69 ALC262 Series Datasheet Typical Maximum Units - - - - - 1 Frame Time Initialization >= 4 BCLK Sequence Normal Frame SYNC Initialization ...
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... DAC and 6-Ch ADC High Definition Audio Code Symbol Minimum - - T_ - cycle T_ - jitter T_ 17.5 high T_ 17.5 low T_ 2.1 setup T_ 2.1 hold T_ - tco T_ - tco T_ - flight T_cycle T_high T_low T_hold T_tco T_flight Figure 21. Link Signals Timing 70 ALC262 Series Datasheet Typical Maximum Units 24.0 - MHz 41. 2.0 - 24.16 - 24. 7.5 - 10.0 - 2.0 - Track ID: JATR-1076- Rev. 1.9 ...
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... Bit parameters for 48kHz sample rate of S/PDIF-OUT *2: Bit parameters for 48kHz sample rate of S/PDIF- 9.2.4. Test Mode The ALC262 series does not support codec test mode or Automatic Test Equipment (ATE) mode. 4-Ch DAC and 6-Ch ADC High Definition Audio Code Table 83. S/PDIF Output and Input Timing Symbol Minimum - - T - ...
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... Sampling frequency=48kHz; 0dB=1Vrms • 10KΩ/50pF load; Test bench Characterization BW:10Hz~22kHz, 0dB attenuation Table 84. Analog Performance Min - - - - - - - - - 2. ALC262 Series Datasheet Typ Max Units 1.5 - Vrms 1.1 - Vrms 1.4 - Vrms 1.2 - Vrms FSA 100 - dB FSA - - -75 - ...
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... Volume knob. DC level changes will be reflected to software to control the master volume. AVDD=5V Variable Resistor Figure 23. Volume Control by External Variable Resistor 4-Ch DAC and 6-Ch ADC High Definition Audio Code ALC262 DCVOL (Pin 33) ADC +5V: DCVOL=31 0V: DCVOL=0 73 ALC262 Series Datasheet 5-bit Volume Code [4:0] Track ID: JATR-1076-21 Rev. 1.9 ...
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... This section describes the ALC262 digital microphone implementation. There is one Clock output pin and 1 Data input pin in the ALC262. The ALC262 provides the clock signal to the digital microphone. When the digital microphone receives the external sound input, it converts the analog signals to digital in a 1-bit format ...
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... One pin is clock output to the digital microphone, and the other is a serial pin. The default clock output is 2.048MHz. In Type 1 (Figure 26), the ALC262 uses one data pin to support mono input from digital microphones with an LMV1024 (L), SPD0205ND (L), or AKU2000 (L). ...
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... Mechanical Dimensions See the Mechanical Dimensions notes on the next page. 4-Ch DAC and 6-Ch ADC High Definition Audio Code Track ID: JATR-1076-21 ALC262 Series Datasheet Rev. 1.9 ...
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... BSC 0.217 0.27 0.007 0.008 0.011 0.0196 BSC 3.5 7 0.75 0.018 0.0236 0.030 - - 0.0393 - 77 ALC262 Series TITLE: LQFP-48 (7.0x7.0x1.6mm) PACKAGE OUTLINE DRAWING, FOOTPRINT 2.0mm LEADFRAME MATERIAL APPROVE DOC. NO. VERSION CHECK DWG NO. DATE REALTEK SEMICONDUCTOR CORP. Track ID: JATR-1076-21 Datasheet 02 PKGC-065 Rev. 1.9 ...
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... Package ALC262-GR Version A2 silicon, LQFP-48 &‘Green’ package ALC262-VB0-GR Version B0 silicon, LQFP-48 &‘Green’ package ALC262SRS-GR ALC262-VB0-GR + SRS TruSurround XT (software feature) ALC262H-GR ALC262-VB0-GR + Dolby ALC262-VC1-GR Version C1 silicon, LQFP-48 &‘Green’ package ALC262-VC2-GR Version C2 silicon, LQFP-48 &‘Green’ package ALC262-VD2-GR Version D2 silicon, LQFP-48 & ...