RTL8326 REALTEK, RTL8326 Datasheet
RTL8326
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RTL8326 Summary of contents
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... RTL8326 24-PORT 10/100M + 2-PORT 10/100/1000M ETHERNET SWITCH CONTROLLER WITH EMBEDDED MEMORY DATASHEET Rev. 2.1 27 November 2003 Track ID: JATR-1076-21 ...
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... Realtek representative for additional information that may help in the development process. REVISION HISTORY Revision Release Date 1.8 2003/05/15 1.9 2003/08/08 2.0 2003/9/17 2.1 2003/11/27 24-Port + 2-Port 10/100/1000 Ethernet Switch Controller Summary First external release. Add AC/DC characteristics and mechanical information. Add thermal data Add digital timing characteristics diagram ii RTL8326 Datasheet Track ID: JATR-1076-21 Rev.2.1 ...
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... ACKET AP 24-Port + 2-Port 10/100/1000 Ethernet Switch Controller Table of Contents (208-P PQFP).................................................................................................................. #23).....................................................................................................................19 ORT (P # #G1) .................................................................................................20 ORT ORT (SMI) ..................................................................................................................24 NTERFACE ....................................................................................................................................25 ..........................................................................................................................................33 ) ..................................................................................................................33 NTERFACE (GMII/TBI/MII) .............................................................................................................33 M ..............................................................................................................................34 APPING L ........................................................................................................35 EARCH AND EARNING ..................................................................................................................................35 ........................................................................................................................................ DDRESSES ILTERING ONTROL iii ....................................................................................35 Track ID: JATR-1076-21 Rev.2.1 RTL8326 Datasheet ...
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... NTERFACE 7.28.1. Serial-CPU Access Format ..................................................................................................................................49 7.29. PHY S M ERIAL ANAGEMENT 24-Port + 2-Port 10/100/1000 Ethernet Switch Controller ..............................................................................................................................................35 C .................................................................................................................36 ONTROL P ...................................................................................................................36 REVENTION R S .....................................................................................................37 ECOVERY UPPORT .........................................................................................................................................38 C ...........................................................................................................42 ANDWIDTH ONTROL S ...............................................................................................................................42 UPPORT C P ......................................................................................................42 ONTROL ROTOCOL F D .....................................................................................................46 AULT ETECTION ........................................................................................................................................47 .........................................................................................................................................47 ...........................................................................................................................47 ............................................................................................................................................48 I ....................................................................................................................50 NTERFACE iv RTL8326 Datasheet Track ID: JATR-1076-21 Rev.2.1 ...
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... Loop Detect Status Register (32-Bit Register) .....................................................................................69 24-Port + 2-Port 10/100/1000 Ethernet Switch Controller ............................................................................................................................51 NTERFACE ........................................................................................................................................51 ............................................................................................................................................ NTERNAL EGISTER APPING R ........................................................................................................................55 EGISTERS .......................................................................................................................................56 R ..............................................................................................................56 EGISTERS (ALT ...............................................................................................56 ONTROL EGISTER .....................................................................................................................................59 R .............................................................................................................................59 EGISTER ........................................................................................................................................60 ......................................................................................................................................... .............................................................................................................63 ESERVED R ..........................................................................................................................64 EGISTER C ................................................................................................................68 ONFIGURATION ......................................................................................................................................... .....................................................................54 ABLE Track ID: JATR-1076-21 Rev.2.1 RTL8326 Datasheet ...
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... Port Priority Configuration Registers 0 ............................................................................................82 24-Port + 2-Port 10/100/1000 Ethernet Switch Controller R ...............................................................................................................71 EGISTER ..............................................................................................................72 EGISTER ..............................................................................................................73 EGISTER ONFIGURATION C R ............................................................................................73 ONTROL EGISTER (ALT ...............................................................................................75 ONTROL EGISTER C R ABLE ONFIGURATION EGISTERS ................................................................................................................................81 EGISTER vi .......................................................................73 EGISTER ..............................................................................80 Track ID: JATR-1076-21 Rev.2.1 RTL8326 Datasheet ...
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... HERMAL ATA 13. MECHANICAL INFORMATION................................................................................................................................98 13. ECHANICAL IMENSIONS 24-Port + 2-Port 10/100/1000 Ethernet Switch Controller R .............................................................................................................................82 EGISTER ..........................................................................................................................................83 MIB ORT OUNTER BJECT ELECTION MIB (RX C OUNTER EGISTER .................................................................................................................................91 ATINGS ...........................................................................................................................92 N ............................................................................................................................99 OTES vii 12...................................................88 EGISTER ) (32 ) ......................................................89 OUNTER BITS Track ID: JATR-1076-21 Rev.2.1 RTL8326 Datasheet ...
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... ACKET ORMAT .............................................................................................................................................. NTERNAL EGISTER APPING R ..........................................................................................................................55 EGISTERS ........................................................................................................................................56 R ...............................................................................................................56 EGISTERS (ALT ................................................................................................56 ONTROL EGISTER ......................................................................................................................................59 ..............................................................................................................................59 EGISTER .........................................................................................................................................60 ..........................................................................................................................................60 ( (32- ) .......................................................................................61 EGISTER OUNTER BITS ( (32- ) .......................................................................................62 EGISTER OUNTER BITS ( (32- EGISTER IAGNOSTIC OUNTER viii ....................................................................................44 T ......................................................................54 ABLE ).........................................................................63 BITS Track ID: JATR-1076-21 Rev.2.1 RTL8326 Datasheet ...
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... ONTROL EGISTER OUTER ORT ISCOVERY EGISTER R .......................................................................................................................78 EGISTER VLAN SSIGNMENT NDEX EGISTER UTPUT ORT RIORITY AGGING ix ............................................................................67 ).................................................................................69 0 ...............................................................................71 1 ...............................................................................71 ........................................................................73 EGISTER .......................................................................74 EGISTER (32 )..................................................................78 BITS 0~12................................................................. ...................................80 ONTROL EGISTER Track ID: JATR-1076-21 Rev.2.1 RTL8326 Datasheet ...
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... R (TX C OUNTER EGISTER OUNTER OUNTER EGISTER IAGNOSTIC /R ...................................................................................................................91 ATINGS .............................................................................................................................92 IMING .............................................................................................................................93 IMING .............................................................................................................................................94 .....................................................................................................................................97 ANGE ..............................................................................................................................................97 x 031DH+3 )) ............................................................. 031DH+3 +1)) ......................................................... 031DH+3 +2)) ......................................................... 12.................................................................... ....................................................88 EGISTER ) (32 ) ........................................................90 OUNTER BITS ) (32 ).............................................................90 BITS C ) (32 ) .............................................90 OUNTER BITS Track ID: JATR-1076-21 Rev.2.1 RTL8326 Datasheet ...
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... IGURE ROSS SECTION OF 24-Port + 2-Port 10/100/1000 Ethernet Switch Controller List of Figures ..................................................................................................................................15 F ..........................................................................................................................41 ORMAT P ....................................................................................................................43 ROTOCOL P F .........................................................................................................44 EPLY ACKET ORMAT F ................................................................................................................................45 ORMAT .................................................................................................................................46 ORMAT F ............................................................................................................................47 RAME .............................................................................................................................................48 .....................................................................................................................................49 (ACK) ................................................................................................................................ ...............................................................................................................50 RITE ORMAT /W F ...............................................................................................................50 RITE ORMAT ......................................................................................................................................92 ........................................................................................................................................92 .......................................................................................................................................92 .............................................................................................................................................93 ............................................................................................................................................94 xi RTL8326 Datasheet Track ID: JATR-1076-21 Rev.2.1 ...
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... The RMT gives network administrators the ability to remotely configure and monitor dumb layer 2 switches as though they were intelligent switches. With QoS, Trunking, VLAN, bandwidth control, remote control, and an 0.18µm process, the RTL8326 is a cost effective switch controller for a 24+2G dumb or smart switch application. ...
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... Supports per-port bandwidth control Supports loop detection and indication function Provides serial LED and parallel LED interface for port properties and diagnostic display Needs only one low cost 25MHz crystal or OSC input 0.18µm, 208-pin PQFP, 3.3V single power, 5V I/O tolerance 13 Track ID: JATR-1076-21 Rev. 2.1 RTL8326 Datasheet ...
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... Block Diagram RTL8326 system architecture RTL8326 system architecture Dumb/Smart Out band 8051 control EEPROM Octal-PHY (RTL8208) TXR x 4 RJ45 band control Copyright © 2002 Realtek Sem iconductor Corp. 24-Port + 2-Port 10/100/1000 Ethernet Switch Controller 25MHz Crystal Realtek RTL8326 SMII Octal-PHY ...
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... Ports PHY Management I/F GMII/ TBI/ MII 10/100/1000 MAC DMA Engine RX TX FIFO FIFO TX Start Addr. Queue Switching Engine Flow Control Address Lookup Engine Figure 2. Functional Block Diagram 15 RTL8326 Datasheet EEPROM LED I/F I/F Buffer Management Packet Buffer 8K-Entry Address Table Track ID: JATR-1076-21 Rev. 2.1 ...
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... DVDD 202 DGND 203 TEST_IOD[3] 204 TEST_IOD[2] 205 TEST_IOD[1] 206 TEST_IOD[0] 207 SCK 208 SDA 24-Port + 2-Port 10/100/1000 Ethernet Switch Controller RTL8326 Figure 3. Pin Assignments 16 RTL8326 Datasheet 104 G0RXD[0] 103 G0RX_DV/G0RXDS[8] 102 G0RX_CLK/G0RSCK0 101 G0RXDS[9] 100 G0COL 99 G0CRS 98 G0RSCK1/G0TXC 97 G0TXDS[9] 96 G0TX_CLK ...
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... O 94 DVDD I 95 DGND P 96 G0TX_CLK G 97 G0TXDS[9]/(EnSPDUP G0RSCK1/G0TXC I 99 G0CRS G 100 G0COL P 101 G0RXDS[9] P 102 G0RX_CLK/G0RSCK0 O 103 G0RX_DV/G0RXDS[8] I 104 G0RXD[0] 17 RTL8326 Datasheet Type ...
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... I 198 TEST_IOD[6] I 199 TEST_IOD[5] P 200 TEST_IOD[4] G 201 DVDD I 202 DGND I 203 TEST_IOD[3] I 204 TEST_IOD[2] I 205 TEST_IOD[1] I 206 TEST_IOD[0] I 207 SCK P 208 SDA 18 RTL8326 Datasheet Type ...
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... SMII transmit data is input on these pins, where: 29 Ports 0~7 transmit data is sent synchronously to SYNC_0_7 31 and REFCLK_0_7. 35 Ports 8~15 transmit data is sent synchronously to SYNC_8_15 37 and REFCLK_8_15. 40 Ports 16~23 transmit data is sent synchronously to SYNC_16_23 and 42 REFCLK_16_23 RTL8326 Datasheet Track ID: JATR-1076-21 Rev. 2.1 ...
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... Ports 8~15 data is sent or received synchronously to SYNC_8_15. Ports 16~23 data is sent or received synchronously to SYNC_16_23. Pin No. Description 96 Gigabit port Transmit Clock Output (TBI mode). 125Mhz transmit 8B/10B encoded code-group clock. Transmit Clock Output (GMII mode). 125MHz transmit clock used for G0_TXD synchronization. 20 RTL8326 Datasheet Track ID: JATR-1076-21 Rev. 2.1 ...
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... Receive Clock 1 Input (TBI mode). 62.5MHz receive clock. Used to latch even numbered code-group data in the received PHY bit stream. Transmit Clock Input (MII modes). 2.5/25 MHz (10Mbps/100Mbps) receive clock. The transmit data is sent synchronously on the rising edge of G0_TXC. 21 RTL8326 Datasheet Track ID: JATR-1076-21 Rev. 2.1 ...
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... G0COL is only valid in MII half duplex mode asserted high when a collision is detected on the media. 141 Gigabit port Transmit Clock Output (TBI mode). 125Mhz transmit 8B/10B encoded code-group clock. Transmit Clock Output (GMII mode). 125MHz transmit clock used for G1_TXD synchronization. 22 RTL8326 Datasheet Track ID: JATR-1076-21 Rev. 2.1 ...
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... Receive Clock 1 Input (TBI mode). 62.5MHz receive clock. Used to latch even numbered code-group data in the received PHY bit stream. Transmit Clock Input (MII modes). 2.5/25 MHz (10Mbps/100Mbps) receive clock. The transmit data is sent synchronously at the rising edge of G1_TXC. 23 RTL8326 Datasheet Track ID: JATR-1076-21 Rev. 2.1 ...
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... Table 5. Serial Management Interface (SMI) Pin No Description 79 Serial Management Data Clock (MDC). MDC operates at 1MHz. MDC is in tri-state when RST# is active low. 80 Serial Management Data Input/Output. MDIO is in tri-state when RST# is active low. 24 RTL8326 Datasheet Track ID: JATR-1076-21 Rev. 2.1 ...
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... SCLK acts as an output pin after hardware reset for EEPROM read access. When the configuration download from EEPROM is finished the EEPROM does not exist, then the SCLK will act as an input pin driven by an external CPU to access the RTL8326 internal registers. SCLK Frequency: Output: Operates at 100KHz ...
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... When network control frames are received with the destination MAC address as the group MAC address: (01-80-C2-00-00-03 ~ 01-80-C2-00-00-0F), the switch will drop the frames if the EnCtrlFilter=1. If EnCtrlFilter=0 the frames will be flooded. 0: Disable Filtering 1: Enable Filtering (Default) 46 Enable IGMP Snooping. 0: Disable (Default) 1: Enable 26 RTL8326 Datasheet Track ID: JATR-1076-21 Rev. 2.1 ...
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... Disable back pressure flow control ability 20 Disable Back Pressure 48 Pass One Algorithm. When the 48 Pass One algorithm is enabled, the switch will pass one incoming packet for every 48 collisions. 0: Enable 48 Pass One algorithm (Default) 1: Disable 48 Pass One algorithm 27 RTL8326 Datasheet Track ID: JATR-1076-21 Rev. 2.1 ...
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... Delay 0 ns (Default) 1: Delay 2 ns (Recommend) If EEPROM exists, the EEPROM configuration will override the delay configuration set here. 87 Force TBI G0 Link Up. 0: Normal (Default) 1: Force Link Up 84 Force TBI G1 Link Up. 0: Normal (Default) 1: Force Link Up 28 RTL8326 Datasheet Track ID: JATR-1076-21 Rev. 2.1 ...
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... SLED_DATA shift into external shift register. O 176 Serial LED Data Output/Trunk Port 1 Enabled LED output. In Serial LED mode, when Serial LED mode is enabled, serial LED data is shifted out when SLED_CLK is active. See 7.31 LED Interfaces, page 51 for detailed information. 29 RTL8326 Datasheet Track ID: JATR-1076-21 Rev. 2.1 ...
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... This LED show the state information of the Gigabit Port when it is linked at 1000Mbps. The definition of this LED is different in serial mode and parallel mode: In Serial Mode it is 1000M speed In Parallel Mode it is 1000M Link/ Activity 0: Link Up 1: Link Down Blinking: TX/RX Activity (Blinking then 40 ms OFF) 30 RTL8326 Datasheet Track ID: JATR-1076-21 Rev. 2.1 ...
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... Note: DO NOT supply 1.8V power to these pins. P 138, 157 1.8V for Core power. Generated by internal regulator. Only an external 10uF CAP and by pass CAP are required. Note: DO NOT supply 1.8V power to these pins 25, GND for Core power. 48, 65, 92, 107, 139, 158, 180, 31 RTL8326 Datasheet Track ID: JATR-1076-21 Rev. 2.1 ...
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... Normally kept floating Test pin. (Pd) Normally kept floating. I 186 Test pin. (Pd) Normally kept floating. IO 187, 188, Test Pins. 189, 190, Normally kept floating. 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 203, 204, 205, 206 32 RTL8326 Datasheet Track ID: JATR-1076-21 Rev. 2.1 ...
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... Functional Description 7.1. Reset 7.1.1. Hardware Reset In a power-on reset, an internal power on reset pulse (44ms) will be generated and the RTL8326 will start the reset initialization procedures. These are: 1. Determine various default settings via the hardware strap pins at the end of the RST# signal 2. Auto load the configuration from EEPROM if EEPROM is detected (approx. 10ms) 3 ...
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... GRXD7 GRX_DV - - - In TBI interface mode, the RTL8326 implements a built-in PCS (Physical Coding Sublayer) for SERDES transceiver applications. The PCS function implemented by the RTL8326 comprises: • PCS Transmit process • PCS Receive process • 8-bit to 10-bit Encoding and 10-bit to 8-bit Decoding • Synchronization process • ...
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... The RTL8326 MAC address lookup table consists of an 8K-entry hash table and 64-entry CAM. The RTL8326 uses the last 13 bits of the MAC address to index the 8K-entry lookup table for address searching and learning. If the mapped location in the 8K entries is occupied, then the RTL8326 will compare the destination MAC address with the contents of the CAM for address searching and store the source MAC address to the CAM for address learning ...
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... MDIO external connected PHY good PAUSE frame is received from any PAUSE flow control enabled port with DA=0180C2000001, the corresponding port of the RTL8326 will stop its packet transmission until a PAUSE timer timeout or another PAUSE frame with zero PAUSE time is received. ...
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... LED. The LED will be active low when the trunking function is enabled. The RTL8326 trunking port always sends packets over the same link path in the trunk with a given source and destination MAC address to prevent frames from getting out of order, but the reverse path may follow a different link ...
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... IGMP report packet. 7.18. VLAN Function The RTL8326 supports a VLAN function to segregate the switch into 32 VLANs. Each VLAN is a broadcast domain and each VLAN may be flexibly configured from port members. Both port- based and tag-based VLAN functions are supported. The PVID, Tagging Control, and Ingress/Egress rules are manually configured on the VLAN Table at registers 0x030B~0x037C ...
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... VLAN tagging is ignored. All other VLAN table configurations are the same as tag-based VLAN functions. The VLAN classification of an incoming packet on a port-based VLAN is defined by the port PVID. The RTL8326 uses the Port VLAN Identifier (PVID) to search the VLAN table for the VLAN member. ...
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... Note: This function may be enabled whether the VLAN function is enabled or not. 7.19. QoS Function The RTL8326 can recognize QoS priority information in an incoming packet and send the packet to different priority queues for different service priority. The RTL8326 identifies the packet’s priority based on three types of QoS priority information: 1 ...
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... The DS field byte for IPv4 is the Type-of-Service (TOS) octet, and for IPv6 the Traffic-Class octet. Recommended DiffServ Codepoints are defined in RFC2597 for classifying traffic into different service classes. The RTL8326 extracts the codepoint value of the DS field from IPv4 and IPv6 packets and identifies the priority of the incoming IP packet following the definitions listed below: High Priority. DS-field = 101110 (EF, Expected Forwarding) 001010 ...
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... Flow Control Auto Turn Off The RTL8326 can automatically turn off 802.3x flow control and back pressure flow control for 1~2 seconds whenever the port receives a high priority packet. Flow control is re-enabled when no priority packet are received for 1~2 seconds. This auto-turn off function is enabled via hardware pin EnFCAutoOff or Register 0x0400 ...
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... A B Realtek RRCP Protocol commands ( Get, Set, Hello ) user 用戶端 Figure 7. Realtek Remote Control Protocol (1) register Get (2) register Set (3) Hello (1) register Get Reply (2) Hello Reply 43 RTL8326 Datasheet Track ID: JATR-1076-21 Rev. 2.1 ...
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... Operation Code (7bit). Code definition. 00: Hello packet 01: Get configuration 02: Set configuration Reply flag. On receiving a control packet reply from the switch to the management station, this flag will be set to 1. Otherwise, this bit should RTL8326 Datasheet ( Code (7bit) Value -- -- 0x8899 ...
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... Each Realtek switch controller that is aware of the RRCP has a unique Chip ID (see 10.4.7 0x0206H: Chip Model ID, page 72). 45 Value Default: 0x2379 ( Code (7bit) Uplink Port (1) Chip ID (2) Default=00h Updated by the Uplink_MAC switch Default: 0 EEPROM Track ID: JATR-1076-21 Rev. 2.1 RTL8326 Datasheet -- -- Value -- ...
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... Vender ID 4B 7.23. Network Loop Connection Fault Detection The RTL8326 periodically transmits a Realtek-EtherType (=0x8899) protocol frame to detect network loop faults. • Normal transmission time interval is five minutes • port detects a loop, the loop event flag will be set (register 0x0101) and the transmission time interval will change to one second to speed up the new topology change detection. • ...
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... The Realtek Echo Protocol (REP) supports the Layer 2 Echo test easy for a host to do network connection diagnostics through a simple test packet, with or without other hosts on the network assignment is required. When the RTL8326 receives a REP packet, it replies by sending the original REP frame to the source MAC address with the DA and SA exchanged. Realtek Echo Protocol Frame ...
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... Serial CPU Interface The RTL8326 supports a serial CPU interface (Slave mode) that shares the same hardware pin (SCK, SDA) as the EEPROM interface (Master mode). The EEPROM and Serial interface can coexist by assigning a different device ID. Define EEPROM device ID=1010-000, RTL8326 device ID=1010-100. ...
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... Serial-CPU Access Format In Serial CPU mode, 16-bit and 32-bit data access are both supported by the RTL8326. The Serial Read Write access format is as follows. • 16-bit Address (MSB first) • 16/32-bit data Burst Read (Low byte (Byte0) first; MSB first) • 16/32-bit data Burst Write (Low byte (Byte0) first; MSB first) Note: Each burst is one byte. Start and Stop Definition (START ...
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... Note ACK by RTL8326 ACK by CPU 7.29. PHY Serial Management Interface The RTL8326 supports PHY management through the serial MDIO and MDC signal (SMI) to start the auto-negotiation process. After a power-on reset, the RTL8326 writes its abilities to the advertisement registers 0, 4, and 9 of the connected PHY and commands the PHY to restart the auto negotiation process. ...
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... Write 7.29.2. PHY Register Indirect Access The RTL8326 supports the ability to randomly access PHY registers through a set of control registers at 0x0500~0x0502. Users need to define the PHY address ID, PHY Register ID, Data content of the write command, and operating command type (Read or Write) on the above registers. Then the RTL8326 will auto process the PHY Read/Write access through the MDC/MDIO interface ...
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... ON: Network loop connection fault detect ON: Broadcast Storm Alarm port Reserved for TX Utilization testing mode Reserved for RX Utilization testing mode DiagItem_2 ……. DiagItem_7 52 011 100 101 110 Link/Act Duplex Act Link /100Spd Loop to DiagItem_0 Track ID: JATR-1076-21 Rev. 2.1 RTL8326 Datasheet 111 Col ...
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... StateLED2] [Reserved_(DiagS1)] [Reserved_(DiagS2)] [Reserved_(DiagS5)] [Reserved_(DiagS6)] 53 NULL (Reserved NULL (Reserved) Broadcast Storm 6 Port 5 Loop Detect Port 4 High Priority Port 3 TrunkPort /Fault 2 FC/FC Active 1 0 DisPort /RxErr Diagnostics Indication LEDs …. last bit). [P25 DiagLED0] [Reserved_(DiagS3)] [Reserved_(DiagS7)] Track ID: JATR-1076-21 Rev. 2.1 RTL8326 Datasheet ...
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... QoS Control Port Priority Configuration 0 Port Priority Configuration 1 Reserved Reserved Global Port Control Register Port Property Configuration 0 Port Property Configuration 1 Port Property Configuration 2 Port Property Configuration 3 54 RTL8326 Datasheet Corresponding Internal Internal Register Default Address Mapping Value 0x0002 0A80 0x0003 0140 ...
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... Port Property Configuration 8 Port Property Configuration 9 Port Property Configuration 10 Port Property Configuration 11 Port Property Configuration 12 Reserved Reserved Reserved Diagnostic Configuration purposes (must be configured as 0000) Table 23. System Configuration Registers 55 RTL8326 Datasheet Corresponding Internal Internal Register Default Address Mapping Value 0x060E AFAF 0x060F AFAF ...
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... Address Learning Control Register 0. 2 Address Learning Control Register 1. 3 Unknown SA Capture Register 0. 4 Unknown SA Capture Register 1. 5 Unknown SA Capture Register 2. 24-Port + 2-Port 10/100/1000 Ethernet Switch Controller Table 24. System Status Registers Table 25. Management Configuration Registers 56 RTL8326 Datasheet RW Default Pin ...
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... Track ID: JATR-1076-21 Rev. 2.1 RTL8326 Datasheet Default Pin 0100 0302 0504 0706 0908 0B0A 0D0C 0F0E 1110 1312 1514 1716 1918 FFFF FFFF ...
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... Track ID: JATR-1076-21 Rev. 2.1 RTL8326 Datasheet Default Pin EE 0300 0000 0100 0300 0000 0200 0300 0000 0400 0300 0000 0800 0300 0000 1000 0300 0000 2000 0300 0000 4000 0300 ...
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... Description Address 0x0500 0 PHY Access Control Register. 1 PHY Access Write Data Register. 2 PHY Access Read Data Register. 24-Port + 2-Port 10/100/1000 Ethernet Switch Controller Table 27. Queue Control Registers Table 28. PHY Access Control Register 59 RTL8326 Datasheet RW Default Pin EE RW FFFF RW 03FF RW 0000 RW FFFF ...
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... Port MIB Counter Object Selection Register 5 (Port 10, 11). 6 Port MIB Counter Object Selection Register 6 (Port 12, 13). 7 Port MIB Counter Object Selection Register 7 (Port 14, 15). 24-Port + 2-Port 10/100/1000 Ethernet Switch Controller Table 29. Port Control Registers Table 30. MIB Counter Registers 60 RTL8326 Datasheet RW Default Pin ...
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... Track ID: JATR-1076-21 Rev. 2.1 RTL8326 Datasheet Default Pin EE 0555 0555 0555 0555 0555 Default Pin ...
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... Port 25 MIB Counter 2 Register (TX Counter) (32-bits). 24-Port + 2-Port 10/100/1000 Ethernet Switch Controller Track ID: JATR-1076-21 Rev. 2.1 RTL8326 Datasheet Default Pin ...
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... Ethernet Switch Controller Track ID: JATR-1076-21 Rev. 2.1 RTL8326 Datasheet Default Pin Default ...
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... Clears all the MAC, VLAN tables. 4. Resets all registers to default values. 5. Restarts auto-negotiation. 0: Normal 1: Hardware reset 15:2 Reserved 24-Port + 2-Port 10/100/1000 Ethernet Switch Controller LL: Latch Low until cleared LH: Latch High until cleared SC: Self Clearing RC: Read to Clear 64 RTL8326 Datasheet RW Default W/SC 0 W/SC 0 Track ID: JATR-1076-21 Rev. 2.1 ...
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... Enable Advanced Back Pressure Back Off scheme. 0: Normal mode 1: Advanced mode; k: min (n, 3) 12:11 PortDscThr[1:0] Reserved for Port Descriptor Threshold Tuning Control Testing. Keep the value at 00. 24-Port + 2-Port 10/100/1000 Ethernet Switch Controller Table 36. 0x0001H: Switch Parameter Register 65 RTL8326 Datasheet RW Default RW HW pin MaxPktLen[1: pin TXIPG_Comp RW ...
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... Gigabit Port G0 GMII RX I/O PAD input delay Configuration. 00: Delay 0 ns (Default) 01: Delay 1 ns 10: Delay 2 ns 11: Delay 3 ns Gigabit Port G1 GMII RX I/O PAD input delay Configuration. 00: Delay 0 ns (Default) 01: Delay 1 ns 10: Delay 2 ns 11: Delay RTL8326 Datasheet RW Default pin EnSPDUP RW Default ...
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... Delay 0 ns (Default) 1: Delay 2 ns Fast Ethernet Port 16~23 SMII REFCLK I/O PAD output delay Configuration. 00: Delay 0 ns (Default) 01: Delay 1 ns Description User Defined I/O Data. These bits reflect the real time value of the hardware pin USR_IO[3:0]. 67 RTL8326 Datasheet RW Default R 01 (W: EEPROM (W: EEPROM) R ...
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... StatLED2, StatLED1, StatLED0. 0: Disable 1: Enable If an LED is disabled, the corresponding serial clock will be masked. Serial/Parallel LED Display Mode Configuration. Two LED output display modes are supported; parallel mode and serial mode. 0: Parallel LED mode 1: Serial LED mode 68 RTL8326 Datasheet RW Default RW 000 RW 001 RW 010 RW ...
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... In fast mode the interval time is about 1 second in order to accelerate detection and diagnostic. The loop event will be reported in this Loop Detect Status Register Loop detected on this port 1: Loop detected on this port 69 RTL8326 Datasheet RW Default pin ...
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... FaultTkGroup[3] indicator for Trunk 3: (port 8, 9, 10, 11) FaultTkGroup[4] indicator for Trunk 4: (port 12, 13, 14, 15) FaultTkGroup[5] indicator for Trunk 5: (port 16, 17, 18, 19) FaultTkGroup[6] indicator for Trunk 6: (port 20, 21, 22, 23) FaultTkGroup[7] indicator for Trunk 7: (port G0, G1) 0: Trunk OK 1: Trunk Fault detected 70 RTL8326 Datasheet RW Default R 000 R 0 ...
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... RRCP Access enabled port 1: RRCP Access disabled port Note: Ports 0~23 RRCP security mask will be set if the hardware strap pin EnHomeVlan is pulled high during power on reset. This can be over written by EEPROM or register access. 71 RTL8326 Datasheet RW Default RW HW pin: DisRRCP RW HW pin ...
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... Identifies the chip version for programmer version control. Table 51. 0x0207H: System Vender ID Register 0 Description System Vender Identity Stream [15:0]. Used for the system vender to fill a code or name stream for switch device model number or vender name identification. 72 RTL8326 Datasheet RW Default R 0 (W: EEPROM) RW Default ...
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... Configures the maximum output bandwidth of the port. Bit reserved bit. Bit[2:0] controls the maximum RX rate of the port. 000: Disables rate control 001: 128Kbps 010: 256Kbps 011: 512Kbps 100: 1Mbps 101: 2Mbps 110: 4Mbps 111: 8Mbps 73 RTL8326 Datasheet RW Default R 0 (W: EEPROM) RW Default RW 0x2379 RW ...
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... Disables rate control 001: 128Kbps 010: 256Kbps 011: 512Kbps 100: 1Mbps 101: 2Mbps 110: 4Mbps 111: 8Mbps Description Port 2n RX Bandwidth Control. Port 2n TX Bandwidth Control. Port 2n+1 RX Bandwidth Control. Port 2n+1 TX Bandwidth Control. 74 RTL8326 Datasheet RW Default RW 0000 RW 0000 RW 0000 RW Default RW 0000 ...
Page 75
... DisMacLearn[15:0] control port[15:0]. The Layer 2 MAC address learning function can be per-port disabled for security management purposes. Generally this register is used with the ALT Configuration Register (0x0300) bits ‘DisMacAging’ & ‘EnDropUknDA’. 0: Enable learning (Default) 1: Disable learning 75 RTL8326 Datasheet RW Default pin. ...
Page 76
... Register addresses 0x0303 ~ 0x0305. The incoming port ID of the unknown Source MAC address and valid bit is reported in register address 0x0306. Description Unknown Source MAC Address Capture (Byte 2, 3). Description Unknown Source MAC Address Capture (Byte RTL8326 Datasheet RW Default Default ...
Page 77
... EnTrunk[6] control for Trunk 6: (port 20, 21, 22, 23). EnTrunk[7] control for Trunk 7: (port G0, G1). 0: Disable Trunking 1: Enable Trunking Test bit. Keep as 0. The bit value of EEPROM should be set Reg 0x0304 Reg Track ID: JATR-1076-21 Rev. 2.1 RTL8326 Datasheet Default 0000 0 Default 0x00 0 ...
Page 78
... Enable VLAN Unicast Packet Inter-VLAN Leaky Control Enables inter-VLAN communication for unicast forwarding packets. Normally, inter-VLAN packet switching is not valid. The RTL8326 supports a control bit to enable inter-VLAN communication in the switch without an external router. 0: Disable 1: Enable ARP broadcast Packet Inter-VLAN Leaky Control. ...
Page 79
... Port VLAN ID Bit[7:5]: Reserved, currently not used Port(2n+1) VID assignment Index. Bit[4:0]: Port VID assignment index. Use the index value as the offset to map to the VLAN configuration table to get a 12-bit Port VLAN ID Bit[7:5]: Reserved, current not used 79 RTL8326 Datasheet RW Default ...
Page 80
... VLAN (entry m) Port Member, 26-bit map (bit 0~15). Bit value 0: Port is not a member of the VLAN Bit value 1: Port is a member of the VLAN Description VLAN(m) Port Member 26-bit map (bit 16~25). Bit value 0: Port is not a member of the VLAN Bit value 1: Port is a member of the VLAN 80 RTL8326 Datasheet RW Default ...
Page 81
... Disabled (Default) 1: Enabled Weighted round robin ratio setting of priority queue. The frame service rate of High-pri queue: Low-pri queue is. 00: 4:1 01: 8:1 10: 16:1 (Default) 11: High priority queue first always 81 RTL8326 Datasheet RW Default Default RW HW pin. ...
Page 82
... Description PHY Register address setting for the PHY Access command. PHY ID (PHY address) setting for the PHY Access command. RTL8326 connected PHY ID is fixed as: Fast Ethernet Port0 ~ 23. PHY ID …, 30, 31. Gigabit Port G1 and G2. PHY ID: 2 and 3. PHY Access Command. 0: PHY Access Read command 1: PHY Access Write command PHY Access Command Execution Status ...
Page 83
... Strict flood mode will drop IP Multicast packets if any one destination port member is congested. Loose flood mode allows IP multicast packets to be flooded to all non-congested ports. 0: Disable IP Multicast Packet Strict Flood (Loose flood mode) 1: Enable IP Multicast Packet Strict Flood (Strict flood mode) 83 RTL8326 Datasheet RW Default RW 0 ...
Page 84
... Port Enable/Disable Control for port 16 ~ 25. Bit value 0: Port enable Bit value 1: Port disable When disabled, the port will disable packet transmission and reception except for Realtek Remote Control Packets. Note: Ports 16~25 map to bits RTL8326 Datasheet RW Default RW HW pin: DisBRDCTRL ...
Page 85
... Bit [4:0]: Media Capability[4:0]= {1000F, 100F, 100H, 10F, 10H}. Bit [5]: Pause ability (1: Enable). Bit [6]: AsyPause ability ( Asynchronous Pause) (1: Enable). Bit [7]: Enable Auto Negotiation (1: Enable). Note: A software reset is required to complete the port properties update. 85 RTL8326 Datasheet RW Default RW 100M. 0xAF 1000M: 0xBF RW 100M. 0xAF 1000M: 0xBF Track ID: JATR-1076-21 Rev ...
Page 86
... For ports 0~23 (Fast Ethernet ports) Don’t Care. For ports 24~25 (Gigabit ports). Defined as RX Pause ability. In half duplex mode. Don’t Care. 0: Flow control disabled 1: Flow control enabled Bit [7]: Enable Auto Negotiation (AN): 0: Disable AN 1: Enable AN 86 RTL8326 Datasheet RW Default R 0 Track ID: JATR-1076-21 Rev. 2.1 ...
Page 87
... For ports 0~23 (Fast Ethernet ports) Don’t Care. For ports 24~25 (Gigabit ports). Defined as RX Pause ability. In half duplex mode. Don’t Care. 0: Flow control disabled 1: Flow control enabled Bit [7]: Enable Auto Negotiation (AN): 0: Disable AN 1: Enable AN 87 RTL8326 Datasheet RW Default R 0 Track ID: JATR-1076-21 Rev. 2.1 ...
Page 88
... MIB object: Collision packet count TX byte count. This counter is incremented once for every data byte of a transmitted packet (includes both good and bad packets). TX packet count. This counter is incremented once for every transmitted packet (includes both good and bad packets). 88 RTL8326 Datasheet RW Default ...
Page 89
... Collision packet counter. This counter is incremented once for every collision event detected. Table 84. MIB Counter Timeout MIB Object Type MIB Counter Timeout (Sec.) Packet count Byte count Packet count Byte count Packet count Byte count 89 RTL8326 Datasheet RW Default ...
Page 90
... For Port(n) MIB Counter 3 Register (32-bit … 25 (Addr: 0x0741H+n). Table 87. 0x0741~075AH: Port MIB Counter 3 Register (Diagnostic Counter) (32 bits) Bits Name 31:0 Port(n)_MIB_CNT_3[31:0] 24-Port + 2-Port 10/100/1000 Ethernet Switch Controller Description Port(n) MIB Counter_1[31:0] Description Port(n) MIB Counter_2[31:0] Description Port(n) MIB Counter_3[31:0] 90 RTL8326 Datasheet RW Default Default Default R 0 ...
Page 91
... RTL8326 Datasheet Max Units °C +150 +5.0 V VDD V VDD V Max Units °C +70 3 ...
Page 92
... Table 90. PHY Management (SMI) Timing Minimum MDC t4 Data Figure 18. MDC/MDIO Write Timing MDC Figure 19. MDC/MDIO Read Timing High High Figure 20. MDC/MDIO Reset Timing 92 Typical Maximum - 1360 - - 680 - - 680 - 680 - 680 - - - Data t7 Track ID: JATR-1076-21 Rev. 2.1 RTL8326 Datasheet Units ...
Page 93
... Table 91. PHY Management (SMI) Timing Minimum T_opd_txd_smii REFCLK TXD SYNC Figure 21. SMII Transmit Timing Table 92. SMII Receive Timing Minimum T_ipsu_rxd_smii REFCLK RXD Valid Data Figure 22. SMII Receive Timing 93 Typical Maximum Typical Maximum 2 1.5 T_iphd_rxd_smii Track ID: JATR-1076-21 Rev. 2.1 RTL8326 Datasheet Units ns Units ns ns ...
Page 94
... Ethernet Switch Controller Table 93. GMII Transmit Timing Minimum T_opd_txd_gmii GxTX_CLK TXD Figure 23. GMII Transmit Timing Table 94. GMII Receive Timing Minimum T_su_rxd_gmii GxRX_CLK RXD Valid Data Figure 24. GMII Receive Timing 94 Typical Maximum 1.2 2.5 4 Typical Maximum 2.5 0.5 T_hd_rxd_gmii Track ID: JATR-1076-21 Rev. 2.1 RTL8326 Datasheet Units ns Units ns ns ...
Page 95
... Table 95. MII Transmit Timing Minimum T_opd_txd_mii GxTXC TXD Figure 25. MII Transmit Timing Table 96. MII Receive Timing Minimum T_su_rxd_mii GxRXC RXD Valid Data Figure 26. MII Receive Timing 95 Typical Maximum 4 7.4 10 Typical Maximum 2 1 T_hd_rxd_mii Track ID: JATR-1076-21 Rev. 2.1 RTL8326 Datasheet Units ns Units ns ns ...
Page 96
... Ethernet Switch Controller Table 97. TBI Transmit Timing Minimum T_opd_txd_TBI GxTX_CLK TXD Figure 27. TBI Transmit Timing Table 98. TBI Receive Timing Minimum T_su_rxd_TBI GxRCK0/1 RXD Valid Data Figure 28. TBI Receive Timing 96 Typical Maximum 1.5 2.5 4 Typical Maximum 3 0.5 T_hd_rxd_TBI Track ID: JATR-1076-21 Rev. 2.1 RTL8326 Datasheet Units ns Units ns ns ...
Page 97
... PCB conditions (JEDEC JESD51-7). Dimensions: 300 x 140 mm. Thickness: 1.6mm 24-Port + 2-Port 10/100/1000 Ethernet Switch Controller Tc Figure 29. Cross-section of 208 PQFP Table 99. Thermal Operating Range Condition Table 100. Thermal Resistance Condition 2 layer PCB, 0 ft/s airflow. 2 layer PCB, 0 ft/s airflow. 97 RTL8326 Datasheet Min Typical Max Units ° 125 °C 0 ...
Page 98
... Mechanical Information See the Mechanical Dimensions notes on the next page. 24-Port + 2-Port 10/100/1000 Ethernet Switch Controller 98 Track ID: JATR-1076-21 Rev. 2.1 RTL8326 Datasheet ...
Page 99
... Millimeter 0.20 0.30 4.General appearance spec. should be based 0.15 0.26 on final visual inspection spec. TITLE. 208 PQFP ( 28x28 mm) FOOTPRINT 2.6mm 0.50 0.80 APPROVE 0.50 0.75 1.30 1.55 CHECK - 0.10 0° - 12° PACKAGE OUTLINE DRAWING LEADFRAME MATERIAL: DOC. NO. 530-ASS-P004 VERSION 1 PAGE DWG NO. Q208 - 1 DATE REALTEK SEMICONDUCTOR CORP. Track ID: JATR-1076-21 Rev. 2.1 RTL8326 Datasheet ...