HDMP-1646 Avago Technologies, HDMP-1646 Datasheet

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HDMP-1646

Manufacturer Part Number
HDMP-1646
Description
Manufacturer
Avago Technologies
Datasheet

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Gigabit Ethernet Transceiver Chip
Preliminary Technical Data
Features
• IEEE 802.3z Gbit Ethernet
• Based on X3T11 “10 Bit
• Low Power Consumption
• Transmitter and Receiver
• Two Package Sizes
• 10-Bit Wide Parallel TTL
• Single +3.3 V Power Supply
• 5-Volt Tolerant I/Os
• 2 KV ESD Protection
Applications
• 1250 MBd Gigabit Ethernet
• High Speed Proprietary
• Backplane Serialization
• Bus Extender
Description
The HDMP-1636/46 transceiver is
a single silicon bipolar integrated
circuit packaged in a plastic QFP
package. It provides a low-cost,
low-power physical layer solution
for 1250 MBd Gigabit Ethernet or
proprietary link interfaces. It
Compatible, Supports 1250
MBd Gigabit Ethernet
Specification”
Functions Incorporated onto
a Single IC
Available:
– 10 mm PQFP (HDMP-1636)
– 14 mm PQFP (HDMP-1646)
Compatible I/Os
Interface
Interface
provides complete Serialize/
Deserialize for copper transmis-
sion, incorporating both the
Gigabit Ethernet transmit and
receive functions into a single
device.
This chip is used to build a high
speed interface (as shown in
Figure 1) while minimizing board
space, power and cost. It is
compatible with the IEEE 802.3z
specification.
The transmitter section accepts
10-bit wide parallel TTL data and
multiplexes this data into a high
speed serial data stream. The
parallel data is expected to be
8B/10B encoded data, or equiv-
alent. This parallel data is latched
into the input register of the
transmitter section on the rising
edge of the 125 MHz reference
clock (used as the transmit byte
clock).
The transmitter section’s PLL
locks to this user supplied 125
MHz byte clock. This clock is
then multiplied by 10, to gener-
ate the 1250 MHz serial signal
clock used to generate the high
speed output. The high speed
outputs are capable of interfacing
directly to copper cables for
electrical transmission or to a
separate fiber optic module for
optical transmission.
HDMP-1636 Transceiver
HDMP-1646 Transceiver
The receiver section accepts a
serial electrical data stream at
1250 MBd and recovers the
original 10-bit wide parallel data.
The receiver PLL locks onto the
incoming serial signal and
recovers the high speed serial
clock and data. The serial data is
converted back into 10-bit
parallel data, recognizing the
8B/10B comma character to
establish byte alignment.
The recovered parallel data is
presented to the user at TTL
compatible outputs. The receiver
section also recovers two 62.5
MHz receiver byte clocks which
are 180 degrees out of phase
with each other. The parallel data
is properly aligned with the rising
edge of alternating clocks.
For test purposes, the transceiver
provides for on-chip local loop-
back functionality, controlled
through an external input pin.
Additionally, the byte
711

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HDMP-1646 Summary of contents

Page 1

... Low Power Consumption • Transmitter and Receiver Functions Incorporated onto a Single IC • Two Package Sizes Available: – PQFP (HDMP-1636) – PQFP (HDMP-1646) • 10-Bit Wide Parallel TTL Compatible I/Os • Single +3.3 V Power Supply • 5-Volt Tolerant I/Os • ESD Protection Applications • ...

Page 2

... PROTOCOL DEVICE BYTSYNC REFCLK ENBYTSYNC Figure 1. Typical Application Using the HDMP-16x6. DATA BYTE FRAME TX[0-9] TX TXCAP0 PLL/CLOCK TXCAP1 GENERATOR REFCLK RXCAP0 RXCAP1 RBC0 RBC1 FRAME DATA BYTE DEMUX RX[0-9] BYTE SYNC BYTSYNC Figure 2. HDMP-16x6 Transceiver Block Diagram. 712 HDMP-16x6 TRANSMITTER SECTION PLL PLL ...

Page 3

... Gigabit Ethernet specifi- cation, which uses an 8B/10B encoding scheme with special reserve characters for link management purposes. In order to accomplish this task, the HDMP-1636/46 incorporates the following: • TTL Parallel I/O’s • High Speed Phase Lock Loops • Clock Generation/Recovery Circuitry • ...

Page 4

... In order to accom- plish this, it uses the high speed serial clock recovered from the RX PLL/CLOCK RECOVERY block. This serial bit stream is sent to the FRAME DEMUX and BYTE SYNC block. HDMP-1636/46 (Transmitter Section) Timing Characteristics + 3. 3. ...

Page 5

REFCLK TX[0]-TX[9] DATA t SETUP Figure 3. Transmitter Section Timing.    ± DOUT TX[0]-TX[9] REFCLK Figure 4. Transmitter Latency ...

Page 6

... HDMP-1636/46 (Receiver Section) Timing Characteristics + 3. 3. Symbol [1,2] b_sync Bit Sync Time t Time Data Valid Before Rising Edge of RBC valid_before t Time Data Valid After Rising Edge of RBC valid_after t RBC Duty Cycle duty t Rising Edge Time Difference A-B [3] t_rxlat ...

Page 7

... Symbol f Nominal Frequency (for Gigabit Ethernet Compliance) F Frequency Tolerance tol Symm Symmetry (Duty Cycle) HDMP-1636/46 (TRx) DC Electrical Specifications + 3. 3. Symbol V TTL Input High Voltage Level, Guaranteed High Signal IH,TTL for All Inputs ...

Page 8

... Output Peak-to-Peak Differential Voltage specified as DOUT+ minus DOUT-. a. Differential HS_OUT Output (Dout+ Minus Dout-). b. Single-Ended HS_OUT Output (Dout+). Eye Diagrams of the High-Speed Serial Outputs from the HDMP-1636/46 as Captured on the HP 83480A Digital Communications Analyzer. Tested with PRBS = 2 Figure 7. Transmitter DOUT Eye Diagrams. ...

Page 9

... OUTPUT) VARIABLE DELAY TTL b. Block Diagram of DJ Measurement Method. Parameter HDMP-1636 HDMP-1646 by the max I and subtracting the power dissipated outside the chip at the high speed 3.45 volts. CC resistors and receiver TTL outputs driving 10 pF loads. for these devices is 48 C/Watt for the HDMP-1636 and 44 C/Watt for the ...

Page 10

... Input TTL, Floats High When Left Open O-TTL Output TTL HS_OUT High Speed Output, ECL Compatible HS_IN High Speed Input C External Circuit Node S Power Supply or Ground HDMP-1636/46 (TRx) Pin Input Capacitance Symbol C Input Capacitance on TTL Input Pins INPUT O_TTL V _TTL ...

Page 11

... Rzz.zz = DIE REVISION S = SUPPLIER CODE YYWW = DATE CODE (YY = YEAR WORK WEEK) COUNTRY = COUNTRY OF MANUFACTURE (MARKED ON BACK OF DEVICE) Figure 11. HDMP-1636/46 (TRx) Package Layout and Marking, Top View. *Note: Pins 26 and 27 are designated as “no connect” pins and must be left unconnected ...

Page 12

TRx I/O Definition Name Pin Type BYTSYNC 47 O-TTL -DIN 52 HS_IN +DIN 54 -DOUT 61 HS_OUT Serial Data Outputs: High-speed outputs. These lines are active when +DOUT 62 ENBYTSYNC 24 I-TTL GND GND_RXA 51 S ...

Page 13

TRx I/O Definition (cont’d.) Name Pin Type RX[0] 45 O-TTL RX[1] 44 RX[2] 43 RX[3] 41 RX[4] 40 RX[5] 39 RX[6] 38 RX[7] 36 RX[8] 35 RX[9] 34 RXCAP0 48 C RXCAP1 49 TX[0] 2 I-TTL TX[1] 3 TX[2] 4 ...

Page 14

... The PLL capacitors are placed physically close to the appropriate pins on the HDMP- 1636/46. Keeping the lines short will prevent them from picking up stray noise from surrounding lines or components. ...

Page 15

... ALL DIMENSIONS ARE IN MILLIMETERS. PART NUMBER A1 HDMP-1636 10.00 HDMP-1646 14.00 TOLERANCE ± 0.10 ± 0.25 ± 0.05 BASIC + 0.15/ Figure 13. Mechanical Dimensions of HDMP-1636/46. Details Plastic 85% Tin, 15% Lead 300-800 m HDMP-1636 0.08 mm max HDMP-1646 0.10 mm max ...

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