PM4341A-RI PMC-Sierra Inc, PM4341A-RI Datasheet
PM4341A-RI
Specifications of PM4341A-RI
Available stocks
Related parts for PM4341A-RI
PM4341A-RI Summary of contents
Page 1
... DATA SHEET PMC-900602 SINGLE DSX-1 TRANSCEIVER DEVICE PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC DATA SHEET ISSUE 8: OCTOBER 2005 PM4341A T1XC T1 FRAMER/TRANSCEIVER ...
Page 2
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Details of Change Updated ordering information including ROHS compliant device. Data Sheet Reformatted — No Change in Technical Content. Generated R7 datasheet from PMC- 891007, R11 Release of Issue 10 of T1XC Eng Doc Release of Issue 9 of T1XC Eng Doc PM4341A T1XC T1 FRAMER/TRANSCEIVER ...
Page 3
... PULSE DENSITY VIOLATION DETECTOR (PDVD) ...................42 8.8 PERFORMANCE MONITOR COUNTERS (PMON) ....................42 8.9 BIT ORIENTED CODE DETECTOR (RBOC) ..............................42 8.10 HDLC RECEIVER (RFDL) ...........................................................43 8.11 ALARM INTEGRATOR (ALMI) .....................................................43 8.12 ELASTIC STORE (ELST).............................................................44 8.13 SIGNALLING EXTRACTOR (SIGX).............................................45 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER i ...
Page 4
... ANALOG DSX-1 PULSE GENERATOR (XPLS) ..........................53 8.27 BACKPLANE TRANSMIT INTERFACE (BTIF) ............................56 8.28 MICROPROCESSOR INTERFACE (MPIF) .................................57 9 REGISTER DESCRIPTION ....................................................................58 9.1 NORMAL MODE REGISTER MEMORY MAP .............................58 10 NORMAL MODE REGISTER DESCRIPTION ........................................62 10.1 INTERNAL REGISTERS..............................................................62 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER ii ...
Page 5
... USING THE LOOPBACK MODES.............................................222 13.4.1 PAYLOAD LOOPBACK ...................................................222 13.4.2 LINE LOOPBACK............................................................223 13.4.3 DIAGNOSTIC DIGITAL LOOPBACK ...............................224 13.4.4 DIAGNOSTIC METALLIC LOOPBACK ...........................225 13.5 USING THE PER-CHANNEL SERIAL CONTROLLERS............226 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 164 PM4341A T1XC T1 FRAMER/TRANSCEIVER iii ...
Page 6
... ABSOLUTE MAXIMUM RATINGS........................................................243 16 CAPACITANCE.....................................................................................244 17 D.C. CHARACTERISTICS...................................................................245 18 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS......247 19 T1XC I/O CHARACTERISTICS ............................................................252 20 ANALOG CHARACTERISTICS ...........................................................262 21 ORDERING AND THERMAL INFORMATION.......................................264 22 MECHANICAL INFORMATION.............................................................265 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER iv ...
Page 7
... REGISTER 11H: CDRC INTERRUPT ENABLE ................................................97 REGISTER 12H: CDRC INTERRUPT STATUS ................................................98 REGISTER 14H: XPLS LINE LENGTH CONFIGURATION ..............................99 REGISTER 15H: XPLS CONTROL/STATUS...................................................101 REGISTER 16H: XPLS CODE INDIRECT ADDRESS ....................................102 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER v ...
Page 8
... REGISTER 33H: TPSC CHANNEL INDIRECT DATA BUFFER ......................129 TPSC INTERNAL REGISTERS 01-18H: PCM DATA CONTROL BYTE..........131 TPSC INTERNAL REGISTERS 19-30H: IDLE CODE BYTE...........................133 REGISTER 34H: XFDL CONFIGURATION .....................................................135 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER vi ...
Page 9
... REGISTER 47H: XIBC LOOPBACK CODE ....................................................163 REGISTER 49H: PMON INTERRUPT STATUS ..............................................164 REGISTER 4AH: PMON LCV COUNT (LSB)..................................................166 REGISTER 4BH: PMON LCV COUNT (MSB).................................................167 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER vii ...
Page 10
... REGISTER 55H: PDVD INTERRUPT ENABLE/STATUS................................181 REGISTER 57H: XBOC CODE .......................................................................183 REGISTER 59H: XPDE INTERRUPT ENABLE/STATUS ................................184 REGISTER 5DH: RSLC INTERRUPT ENABLE/STATUS................................186 REGISTER 0BH: T1XC MASTER TEST .........................................................191 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER viii ...
Page 11
... FIGURE 19 - ESF 4KBIT/S RECEIVE DATALINK INTERFACE.......................197 FIGURE 20 - ESF 2KBIT/S RECEIVE DATALINK INTERFACE.......................198 FIGURE 21 - D-CHANNEL RECEIVE DATALINK INTERFACE .......................198 FIGURE 22 - D-CHANNEL TRANSMIT DATALINK INTERFACE.....................199 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER ix ...
Page 12
... FIGURE 37 - XFDL NORMAL DATA SEQUENCE............................................220 FIGURE 38 - XFDL UNDERRUN SEQUENCE ................................................221 FIGURE 39 - PAYLOAD LOOPBACK ..............................................................223 FIGURE 40 - LINE LOOPBACK.......................................................................224 FIGURE 41 - DIAGNOSTIC DIGITAL LOOPBACK ..........................................225 FIGURE 42 - DIAGNOSTIC METALLIC LOOPBACK ......................................226 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER x ...
Page 13
... FIGURE 61 - TRANSMIT DATA LINK INPUT TIMING DIAGRAM ....................256 FIGURE 62 - BACKPLANE RECEIVE INPUT TIMING DIAGRAM...................256 FIGURE 63 - RECEIVE DATA LINK OUTPUT TIMING DIAGRAM ..................257 FIGURE 64 - BACKPLANE RECEIVE OUTPUT TIMING DIAGRAM...............258 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER xi ...
Page 14
... FIGURE 69 - ANALOG RECEIVE DATA INPUT TIMING DIAGRAM................262 FIGURE PIN PLASTIC LEADED CHIP CARRIER (Q SUFFIX) ...........265 FIGURE PIN COPPER LEADFRAME PLASTIC QUAD FLAT PACK (R SUFFIX) 266 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER xii ...
Page 15
... TABLE 18 - XBAS ZERO CODE SUPPRESSION OPTIONS ........................158 TABLE 19 - XBAS FRAME FORMAT OPTIONS............................................159 TABLE 20 - XIBC CODE LENGTH OPTIONS ...............................................162 TABLE 21 - RPSC INDIRECT REGISTER MAP............................................176 TABLE 22 - RPSC INVERSION OPTIONS....................................................177 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER xiii ...
Page 16
... TABLE 43 - TRANSMIT DATA LINK INPUT TIMING (FIGURE 61)................256 TABLE 44 - BACKPLANE RECEIVE INPUT TIMING (FIGURE 62) ..............256 TABLE 45 - RECEIVE DATA LINK OUTPUT TIMING (FIGURE 63) ..............257 TABLE 46 - BACKPLANE RECEIVE OUTPUT TIMING (FIGURE 64)...........258 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER xiv ...
Page 17
... TABLE SLICING THRESHOLD VOLTAGE........................................262 TABLE 52 - ANALOG RECEIVE DATA INPUT TIMING (FIGURE 69) ...........262 TABLE 53 - TAP/TAN OUTPUT RESISTANCE ..............................................263 TABLE 54 - PACKAGING OPTIONS .............................................................264 TABLE 55 - THERMAL PROPERTIES...........................................................264 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER xv ...
Page 18
... Framing bit errors to 31 per second; • Line code violations to 4095 per second; and • Loss of frame or change of frame alignment events to 7 per second. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER 1 ...
Page 19
... Detects violations of the ANSI T1.403 12.5% pulse density rule over a moving 192 bit window or optionally stuffs ones to maintain minimum ones density. • Allows insertion of framed or unframed in-band loopback code sequences. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER 2 ...
Page 20
... Digital Access and Cross-Connect Systems (DACS) and Electronic DSX Cross-Connect Systems (EDSX) • T1 Frame Relay Interfaces • T1 ATM Interfaces • ISDN Primary Rate Interfaces (PRI) • SONET Add/Drop Multiplexers (ADM) • Test Equipment PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER 3 ...
Page 21
... Bell Communications Research - Functional Criteria for the DS1 Interface Connector, TR-TSY-000312, Issue 1, March, 1988. 13. Bell Communications Research - Transport Systems Generic Requirements (TSGR): Common Requirement, TR-TSY-000499, Issue 3, December, 1989. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER 4 ...
Page 22
... AT&T - Requirements For Interfacing Digital Terminal Equipment To Services Employing The Extended Superframe Format, PUB54016, October 1984. 17. AT&T, TR 62411 - Accunet T1.5 - "Service Description and Interface Specification" December, 1990. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER 5 ...
Page 23
... Saturn User Network Interface for PDH (S/UNI-PDH ™ implement ATM wide area user network interfaces (UNI) and network node interfaces (NNI). In this example, the T1 LIU and framing functions are provided by the PM4341A T1XC. The combination of the T1XC or E1XC devices with the S/UNI-PDH ™ ...
Page 24
... DATA SHEET PMC-900602 Figure 2 - Example 2. DSX-1/0 Cross-connect MT8980 DX PM4341A T1XC + PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC + PM4341A T1XC T1 FRAMER/TRANSCEIVER 7 ...
Page 25
... ISSUE 8 BTPCM BTPCM BTS IG BTS IG BTFP BTFP BTCLK BTCLK BRFP I BRFP I BRCLK BRCLK BRPCM BRPCM BRS IG BRS IG BRFPO BRFPO RCLKO RCLKO #1 #2 PM4341A T1XC T1 FRAMER/TRANSCEIVER TAP DSX-1 C Tran TAN s AVD RAS DSX-1 r Receive REF RRC XCLK AVS AVS ...
Page 26
... T1XC #1 would be programmed to use its RCLKO for the transmitter clock instead of the input BTCLK. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER 9 ...
Page 27
... DATA ALARM EXTRACT FRAM FRAMER/ ALMI SLIP BUFFER ALARM RAM INTE- GRATOR RBOC RFDL BIT- HDLC ORIENTED RECEIVER CODE DETECTOR PM4341A T1XC T1 FRAMER/TRANSCEIVER TRANSMITTER XPLS TAP ANALOG DSX-1 PULSE TAN GENERATOR TC DTIF TCLKO DIGITAL DS-1 TDP/TDD TRANSMIT TDN/TFLG INTERFACE TDLCLK/ TDLUDR TDLSIG/ ...
Page 28
... DATA SHEET PMC-900602 5 DESCRIPTION The PM4341A Single T1 Framer/Transceiver (T1XC feature-rich device suitable for use in many T1 systems with a minimum of external circuitry. The T1XC is software configurable, allowing feature selection without changes to external wiring. On the receive side, the T1XC recovers clock and data and can be configured to frame to any of the common DS-1 signal formats: SF, ESF, T1DM (DDS), or SLC® ...
Page 29
... T1XC device, and serial PCM interfaces that allow 1.544 Mbit/s or 2.048 Mbit/s backplanes to be directly supported. Tolerance of gapped clocks allows other backplane rates to be supported with a minimum of external logic. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER 12 ...
Page 30
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE PM4341A (TOP VIEW) PM4341A T1XC T1 FRAMER/TRANSCEIVER 60 VSSO[ TAP 57 RAVD 56 ...
Page 31
... VSSI[0] 10 VDDI[0] 11 VDDO[1] 12 D[4] 13 D[5] 14 D[6] 15 D[7] 16 RDB 17 WRB PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM43 41A (TOP VIEW) PM4341A T1XC T1 FRAMER/TRANSCEIVER VSSO[ TAP 55 RAVD 54 RAVS 53 RAS 52 RRC 51 REF 50 VSSI[1] 49 VDDI[1] 48 ...
Page 32
... The RDN input can be enabled for either RZ or NRZ waveforms When enabled for NRZ, this input may be enabled to be sampled on the rising falling edge of RCLKI. When ena RZ, clock is recovered from the RDN inputs. PM4341A T1XC T1 FRAMER/TRANSCEIVER eceive dual-rail ising or for P and d ive up ...
Page 33
... Receive Reference (REF bidirectional pin provides DC bias to an external isolation transformer connected to the negative lead of the transformer secondary and to a decoupling capacitor to RAVS. PM4341A T1XC T1 FRAMER/TRANSCEIVER or an output when the receive d for single-rail. ). This analog 16 ...
Page 34
... MHz clock, synchronized to the XCLK signal. The RCLKO signal is recovered from the received analog inputs (if the interface is powered up), from the RDP and RDN inputs (if the input format is dual-rail RZ), or from the RCLKI input (if the input format is NRZ). PM4341A T1XC T1 FRAMER/TRANSCEIVER ). al ith ise 17 ...
Page 35
... Recovered PCM (RPCM). This output available when the T1XC is configured for raw data output. This NRZ output signal is the recovered data s without optional B8ZS decodin It is updated on the falling edge of RCLKO. PM4341A T1XC T1 FRAMER/TRANSCEIVER is This d used be available at the RDD is tream g applied ...
Page 36
... RPCM/RDPCM data stream. This alternate superframe indication is useful for performing format conversion from SF to ESF while maintaining the same superframe alignment. RFP is updated on the falling edge of RCLKO. PM4341A T1XC T1 FRAMER/TRANSCEIVER for ...
Page 37
... DS-1 frame. RDLSIG is updated on the falling ed Receive Data Link Interrupt (RDLINT). The RDLINT signal is available on this output when RFDL is enabled. RDLINT goes high when an event occurs which changes the status of the HDLC receiver. PM4341A T1XC T1 FRAMER/TRANSCEIVER 1DM red RDLCLK. ...
Page 38
... ELST is not by-passed, the BRPCM stream is aligned to the backplane tim and is updated on the falling edge of BRCLK. When the ELST is by-passed BRPCM is aligned to the receive line timing and is updated on the falling edge of RCLKO. PM4341A T1XC T1 FRAMER/TRANSCEIVER hen sed to receive SF formatted data, ing 21 ...
Page 39
... The BRDN NRZ output re receive digital negative pulse signal extracted from the input bipolar signa BRDN is updated on the falling edge RCLKO. PM4341A T1XC T1 FRAMER/TRANSCEIVER Pulse . e falling edge of s the the entire the ...
Page 40
... The T1XC may be configured to ignore the BRCLK input and use the RCLKO signal in its place when the ELST is bypassed. PM4341A T1XC T1 FRAMER/TRANSCEIVER red format ...
Page 41
... In dual-rail input mode, the BTDP input by-passes the transmitter and is fed directly into the DJAT. BTDP is sampled on the rising edge of BTCLK. PM4341A T1XC T1 FRAMER/TRANSCEIVER . If lse . ed, e ing edge of BRCLK. ...
Page 42
... If frame alignment only is required, a pulse at least 1 BTCLK cycle wide must be provided on BTFP every 193 bit times. If superframe alignment is required, transmit superframe alignment must enabled, and a pulse at least 1 BTCLK cycle wide must be provided on BTFP every frame times. PM4341A T1XC T1 FRAMER/TRANSCEIVER put ...
Page 43
... HDLC transmitter (XFDL) is disabled from use. The rising edge of TDLCLK is used to sample the data stream contained on the TDLSIG input. When the T1XC is configured to transmit SF formatted data, the TDLCLK output is held low. PM4341A T1XC T1 FRAMER/TRANSCEIVER CLK input and he n the e ing he ...
Page 44
... TCLKO Transmit Digital DS-1 Signal (TDD). This signal is available on the output when configured to transmit single-rail dat The TDD signal may be enabled to be updated on the rising or falling edge of TCLKO. PM4341A T1XC T1 FRAMER/TRANSCEIVER R). he ing a 1.544 permit O may . ulse e a ...
Page 45
... This analog output drives an AC signal through an external matching transformer connected to the negative lead of the transformer primary. An analog Transmit Monitor Negative point is internally bonded to this output and is used to monitor the negative pulses on the transmit line. PM4341A T1XC T1 FRAMER/TRANSCEIVER lse to r NRZ updated on the l t ...
Page 46
... TAVS must be connected to a common ground together with the VSSO[2:0] and VSSI[1:0] pins. Care mu avoid coupling noise induced on the VSSO and VSSI pins into the TAVS pin. PM4341A T1XC T1 FRAMER/TRANSCEIVER taken to 29 ...
Page 47
... XCLK must be driven with a 37.056 MHz clock. Implementation of Line Loopback is also simplified when a 37.056 MHz clock is used. Vector Clock (VCLK). The VCLK signal is used during T1XC production test to verify internal functionality PM4341A T1XC T1 FRAMER/TRANSCEIVER when on of CLK is nominally a 37.056 . ...
Page 48
... Active low read enable (RDB). This signal is pulsed low to enable a T1XC register read access. The T1XC drives the D[7:0] bus with the contents of the addressed register while RDB and CSB are both low. PM4341A T1XC T1 FRAMER/TRANSCEIVER l asked interrupt sources are r test , then it should (D[7:0]) ...
Page 49
... Pad ring power pins (VDDO[3:0]). These pins must be connected to a common well decoupled +5 VDC supply together 42 44 with the VDDI[1:0] pins. Care must be taken to avoid coupling noise induced the VDDO pins into the VDDI pins. PM4341A T1XC T1 FRAMER/TRANSCEIVER l llowing the T1XC ...
Page 50
... These power supply connections must all be utilized and must all connect to a common + ground rail, as There is no low impedance connection within the PM4341A between the co pad ring, and transmit analog supply rails. Failure to properly make these connections may result in improper operation or damage to the device ...
Page 51
... RFDL FIFO buffer due to the transition from receiving all ones to flags is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 es specified in the RFDL Interrupt ly on detection of RFDL FIFO buffer overrun, n detection of an abort condition, or, PM4341A T1XC T1 FRAMER/TRANSCEIVER g 34 ...
Page 52
... TDLCLK frequency of 8 kHz (T1DM R-bit insertion), the time- out is 500µs. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 n the processor is unable to service the a specific time-out period. This period is PM4341A T1XC T1 FRAMER/TRANSCEIVER kHz rate), 35 ...
Page 53
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 al receive pins RDP/RDD/SDP and ck provides the f irs PM4341A T1XC T1 FRAMER/TRANSCEIVER t stage of sign al conditionin g C block, 36 ...
Page 54
... Bridging 2 Tight tolerances are required on the resistors and turns ratio to meet th loss specification. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 R1 (Ω ± 1%) 309 0 PM4341A T1XC T1 FRAMER/TRANSCEIVER Squelch R2 (Ω ± 1%) Level at Primary (mV ± 20%) 93 227 ...
Page 55
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 R1 1:N R2 0.1 µF ± 10% 316 k Ω ±1% C (pF L (µH w/w L max.) max.) 35 0.80 PM4341A T1XC T1 FRAMER/TRANSCEIVER V DD RAVD RAS REF RRC RAVS 47 nF ±10% DCR pri. DCR s ec. (Ω max.) (Ω max.) 0.80 1.2 ...
Page 56
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 the RSLC functional block with the 20 -1 with 14 zero restriction). The CDRC PM4341A T1XC T1 FRAMER/TRANSCEIVER 39 ...
Page 57
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 IN SPEC. REGION CDRC MAX. TOLERANCE (ALGSEL=0) 0.70 SINEWAVE JITTER FREQUENCY, kHz - LOG SCALE ATA RECOVERY (DREC) block to PM4341A T1XC T1 FRAMER/TRANSCEIVER CDRC MAX. TOLERANCE (ALGSEL=1) AT&T SPEC. BELLCORE SPEC. 100 10 ...
Page 58
... ISSUE 8 99 times out of 100. , and extracts the Y-bit from the T1DM MR also extracts the SLC®96 data 2 frames of PCM data during normal operation (i.e. when uishes control of FRAM to ELST which buffers the PM4341A T1XC T1 FRAMER/TRANSCEIVER om the incoming PCM data AM ...
Page 59
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 ion Detection function is provided by the PDVD block. ensity violations of the requirement that there be N ones d to signal a 16 consecutive zero event, and/or a change or (RBOC) PM4341A T1XC T1 FRAMER/TRANSCEIVER r bit ...
Page 60
... YELLOW alarm is removed PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 ed into a 4-level FIFO buffer. The Status Register contains PM4341A T1XC T1 FRAMER/TRANSCEIVER FCS status and the red ...
Page 61
... The following frame of PCM data will be deleted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 or absence of the YELLOW, RED, and AIS 40 ms, 40ms, and 60 ms intervals, respectively, PM4341A T1XC T1 FRAMER/TRANSCEIVER larm is declared -3 bit gh ...
Page 62
... The Receive Per-channel Serial Controller (RPSC) function is provided by a second PCSC block. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 of frame synchronization. This code is set to all ones density out-of-frame condition, PM4341A T1XC T1 FRAMER/TRANSCEIVER ncy channel- ng his ...
Page 63
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 ng nibble data located in the least significant nibble one byte of "filler" (can be during the first bit of the "filler" byte, PM4341A T1XC T1 FRAMER/TRANSCEIVER for TPSC. ntegrity e BRFPO pin indicates the first ...
Page 64
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 ning) by use of the Master Trunk gister. inally, the transmitter can be by-passed completely to TSB and provides serial streams for PM4341A T1XC T1 FRAMER/TRANSCEIVER l conditioning state (idle r all to - ...
Page 65
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 itted on the Facility Data Link channel as a 16-bit ated as long as the code is not 111111. The interrupt-driven basis by writing byte, an interrupt is generated to signal the controller to PM4341A T1XC T1 FRAMER/TRANSCEIVER nto fic and code pattern. The . This ...
Page 66
... TCLKI, BTCLK, or RCLKO. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 byte has been depleted. In this transmitter is disabled, the serial data to be transmitted PM4341A T1XC T1 FRAMER/TRANSCEIVER trol e XFDL o . The ...
Page 67
... II customer interface given in ANSI T1.403 to be met. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 frequencies below 6.6 Hz are rovide a smooth flow of data out of DJAT, PM4341A T1XC T1 FRAMER/TRANSCEIVER ith ase 50 ...
Page 68
... MHz, the minimum jitter tolerance for various differences between the frequency of PLL reference clock and XCLK/24 are shown in Figure 9. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 10 100 0.3k 1k Jitter Frequency, Hz PM4341A T1XC T1 FRAMER/TRANSCEIVER DJAT minimum tolerance acceptable unacceptable 10k 100k ...
Page 69
... Jitter Gain (dB) -30 -40 -50 1 6.6 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 200 250 0 32 62411 max DJAT response 10 100 Jitter Frequency, Hz PM4341A T1XC T1 FRAMER/TRANSCEIVER 300 354 Hz 100 ± ppm 43802 max 1k 10k 52 : ...
Page 70
... TDN output from DJAT causes a negative pulse to be transmitted. If both TDP and TDN are logical "0" or "1," no output pulse is transmitted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER for ...
Page 71
... The XPLS block provides Alarm Indication Signalling (AIS) generation capability by generating alternating mark signals on the link when the TAIS bit programmed high. This is useful when the internal loopback modes PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER LS can is are used. ...
Page 72
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 470nF ± 10% 0.68µF ± 10%, 50V T 22 Ω ±10% 1nF ±10% R 1:1.36 optional "snubbing " network C (pF L (µH w/w L max.) max.) 35 0.80 PM4341A T1XC T1 FRAMER/TRANSCEIVER 0 to 655 foot cable DSX-1 100 Ω Interface . DCR pri. DCR sec. ( Ω max.) ( Ω max.) 0.80 1.2 55 ...
Page 73
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 (for extended temperature range) PM4341A T1XC T1 FRAMER/TRANSCEIVER 56 ...
Page 74
... DATA SHEET PMC-900602 8.28 Microprocessor Interface (MPIF) The Microprocessor Interface allows the T1XC to be configured, controlled and monitored via internal registers. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER 57 ...
Page 75
... CDRC Reserved 14H XPLS Line Length Configuration 15H XPLS Control/Status 16H XPLS CODE Indirect Address 17H XPLS CODE Indirect Data 18H DJAT Interrupt Status PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER 58 ...
Page 76
... ALMI Alarm Detection Status 30H TPSC Configuration 31H TPSC µP Access Status 32H TPSC Channel Indirect Address/Control 33H TPSC Channel Indirect Data Buffer 34H XFDL Configuration PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER 59 ...
Page 77
... PMON LCV Count (MSB) 4CH PMON BEE Count (LSB) 4DH PMON BEE Count (MSB) 4EH PMON FER Count 4FH PMON OOF/COFA Count 50H RPSC Configuration PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER 60 ...
Page 78
... XBOC Code 58H XPDE Reserved 59H XPDE Interrupt Enable/Status 5AH-5BH Reserved 5CH RSLC Reserved 5EH-7FH Reserved 80H-FFH Reserved for Test PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 LC Interrupt Enable/Status PM4341A T1XC T1 FRAMER/TRANSCEIVER 61 ...
Page 79
... Inter nal Registers PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 ION ode R egister Bits : s has no effect. Reading back unused software when rea d. trolling th e T1XC to determine the programming PM4341A T1XC T1 FRAMER/TRANSCEIVER C 62 ...
Page 80
... The SRPCM bit selects the output signal seen on the multifunction output RPCM/ RDPCM. When set to logic 1, the multifunction output becomes PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X UNF 0 ELSTBYP 0 TRSLIP 0 SRPCM 0 SRSFP 0 ALTRFP 0 CCOFA 0 PM4341A T1XC T1 FRAMER/TRANSCEIVER alignment on the incoming data ...
Page 81
... SFP is set to logic 0, the multifunction , which pulses high during each framing bit (i.e. every sses every second o utp RFP is set t o logic 1, th bit setting. PM4341A T1XC T1 FRAMER/TRANSCEIVER ltifunction output becomes pending on the framing format ut pulse on the multifunction e output signal on RFP pulses 64 ...
Page 82
... BRPCM is output as 1 byte of "filler" followed by 3 bytes of channel data, repeated 8 times. When BRX2M is set to logic 0, the backplane data rate and PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X ALTFDL 0 RXDMAGAT 0 BRX2M 0 BRX2RAIL 0 BRXSFP 0 ALTBRFP 0 RXMTKC 0 PM4341A T1XC T1 FRAMER/TRANSCEIVER rface format t ing 65 ...
Page 83
... B RFPO output pulses high during the first 12 fra fram ESF (depending on the framing PM4341A T1XC T1 FRAMER/TRANSCEIVER a signal on the s, which cont ain the received .544MHz receive line rate, multifunction pins become the ...
Page 84
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default RXDMASIG 0 RXDCHAN 0 TXDMASIG 0 TXDCHAN 0 RDLINTE 0 RDLEOME 0 TDLINTE 0 TDLUDRE 0 PM4341A T1XC T1 FRAMER/TRANSCEIVER . set to ream ity datalink DLSIG ...
Page 85
... EOM and INT RFDL interrupt outputs. See the Operation section for further details on using the RFDL. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER e HAN terrupt to also generate ...
Page 86
... XFDL without needing to interface to the n TDL UDRE XFDL (which is visible on the TDLUDR output pin PM4341A T1XC T1 FRAMER/TRANSCEIVER rrupt to also upt, INTB. This allows a needing to interface to the logic 1, an request for service ) also causes and interrupt to interrupt on INTB. ...
Page 87
... SDP/RDP/RDD and SDN/RDN/RLCV, respectively. When RDPINV is set to logic 1, the interface PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X SDOEN 0 RDIEN 0 RDNINV 0 RDPINV 0 RUNI 0 R FALL 0 RRZ 0 PM4341A T1XC T1 FRAMER/TRANSCEIVER s 70 ...
Page 88
... P/RDD and SDN/RDN/RLCV multifunction pins d negative p ulse inpu ts the falling RCLKI edge. When RF PM4341A T1XC T1 FRAMER/TRANSCEIVER INV is set to logic signal unaltered. ni-polar digital data and line RDP and RDN, sampled on ALL is set to logic assed on to CDRC. The RRZ ...
Page 89
... When TDPINV is set to logic 1, the TDP/TDD output is inverted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default FIFOBYP 0 TAISEN 0 TDNINV 0 TDPINV 0 TUNI 0 FIFOFULL 0 TRISE 0 TRZ 0 PM4341A T1XC T1 FRAMER/TRANSCEIVER " the TCLKI. When lar r violations. 72 ...
Page 90
... TUNI bit is set to lo gic P and TA N, from the XPLS block cannot be used. mines the indication given on the TFLG output pin. positions of becoming empty. PM4341A T1XC T1 FRAMER/TRANSCEIVER inverted. When TDNINV selected TCLKO edge. TDN/TFLG multifunction pins 1 (unipolar mode), the analog 73 ...
Page 91
... BTPCM and BTSIG is expected to be formatted as 1 byte of "filler" followed by 3 bytes of channel data, repeated 8 times. When BTX2M is set to PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X ABXXEN 0 BTXCLK 0 BTX2M 0 BTX2RAIL 0 BTXSFP 0 PM4341A T1XC T1 FRAMER/TRANSCEIVER t ABAB). 74 ...
Page 92
... BTDN. When BTX2RAIL BTPCM and BTSIG digital inputs. The dual- ly only whe n the bac kpl PM4341A T1XC T1 FRAMER/TRANSCEIVER 1 framing bit). a signal il format. When BTX2RAIL is and BTDN dual-rail is set to logic 0, ane data rate is set to 1.544 indicates each framing bit ...
Page 93
... XBAS is enabled to generate and insert the framing into the transmit data. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X SIGAEN 0 TXSIGA 0 FDIS 0 FBITBYP 0 CRCBYP 0 FDLBYP 0 PM4341A T1XC T1 FRAMER/TRANSCEIVER al alling aligner (SIGA) to IGA is inserted into the 76 ...
Page 94
... BT PCM, to bypass the generation through P is set to lo gic 1, the input CRC-6 bit is re-inserted am. When CRCBYP output CRC -6 bits. PM4341A T1XC T1 FRAMER/TRANSCEIVER tion bit in the input data output stream. When is set to logic 0, the XBAS is ization bits. onding to the CRC-6 bit ...
Page 95
... Function Default HSBPSEL 0 XCLKSEL 0 OCLKSEL1 0 OCLKSEL0 0 PLLREF1 EF0 0 TCLKISEL 0 SMCLKO 0 onfigure the options of the transmit timing s the source of the high-speed clock used in the , and RPSC blocks. This allows the T1XC to interface to nes (>2.048MHz, externally gapped, or 2.048MHz, PM4341A T1XC T1 FRAMER/TRANSCEIVER ...
Page 96
... TCLKISEL and SM CLKO are set to logi MHz clock signal is driven by the XCLK input signal. The LKISEL set to logic 1 and SMCLKO set to strates the required bit settings for these ransmitted data: PM4341A T1XC T1 FRAMER/TRANSCEIVER k. Whe n OCLKSEL0 is ( either the d clock derived LK and B TX2M) ...
Page 97
... OCLKSEL1 =0 OCLKSEL0 =0 PLLREF1 =0 PLLREF0 =0 TCLKISEL =0 SMCLKO =0 PLLREF1 =0 PLLREF0 =1 PLLREF1 =1 PLLREF0 =0 PLLREF1 =1 PLLREF0 =1 PM4341A T1XC T1 FRAMER/TRANSCEIVER Affect on Output Transmit Data Jitter attenua ted. TCLKO is a smooth 1.544MH z. TCLKO referenced to BTCLK. TCLKO reference d to RCLKO. TCLKO referenc ed to TCLKI. Jitter attenuated. TCLKO is a smooth 1 ...
Page 98
... XCLKSEL =0 OCLKSEL1 =1 OCLKSEL0 =X PLLREF1 =X PLLREF0 =X TCLKISEL =0 SMCLKO =0 12.352MHz XCLKSEL =1 TCLKISEL =1 SMCLKO =1 PM4341A T1XC T1 FRAMER/TRANSCEIVER Affect on Output Transmit Data Jitter atte nuated. TCLKO is a smooth 1.544MHz. TCLKO referenced to externally "g apped" transmit clock. TCLKO referenced to RCLKO. TCLKO referenced to TCLKI. No jitter attenuation ...
Page 99
... HSBPSEL =0 jitter-free 12.352MHz XCLKSEL =1 OCLKSEL1 =0 OCLKSEL0 =0 PLLREF1 =X PLLREF0 =X TCLKISEL =1 SMCLKO =1 PM4341A T1XC T1 FRAMER/TRANSCEIVER Affect on Output Transmit Data No jitter attenuation. TCLKO is equal to TCLKI (useful for higher rate MUX applications). Same as above. TCLKI is a jitter- free 12.352MHz clock. TCLKO is equal to TCLKI÷8. Same as above. ...
Page 100
... TCLKO referenced to the backplane transmit clock, BTCLK. The following Figure 12 illustrates the various bit setting options, with the reset condition highlighted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 mit clock is used, the DJAT SYNC bit PM4341A T1XC T1 FRAMER/TRANSCEIVER 83 ...
Page 101
... FIF O input DJAT da ta clock 0 FIFO 1 BTX2M Smooth 1.544MHz 00 DJAT 01 PLL 10 11 ÷ TCLKISEL 0 1 XCLKSEL 0 1 HSBPSEL PM4341A T1XC T1 FRAMER/TRANSCEIVER FIFO output TCLKO data clock 0 1 OCLKSEL1 OCLKSEL0 "Jitter-free" 1 1.544MHz SMCLKO Smooth 0 12.352 MHz 1 "Jitter-free" 12.352MHz XPLS "High-speed" clock for CDRC & ...
Page 102
... Reading this register does not remove the interrupt indication; the corresponding block's interrupt status register must be read to remove the interrupt indication. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X IBCD 0 FRMR 0 PDVD 0 ELST 0 RFDL 0 RBOC 0 ALMI 0 PM4341A T1XC T1 FRAMER/TRANSCEIVER 85 ...
Page 103
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X DJAT 0 XPDE 0 RSLC 0 XPLS 0 XFDL 0 CDRC 0 PM4341A T1XC T1 FRAMER/TRANSCEIVER 86 ...
Page 104
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X PAYLB 0 LINELB 0 DMLB 0 DDLB 0 TXMFP 0 TXDIS 0 to ensure the options are such that data PM4341A T1XC T1 FRAMER/TRANSCEIVER c Payload MHz lect e default k). 87 ...
Page 105
... Configurat ion registe and the RUNI bit must be set r, S1 Inte rface Conf igu diagno stic metallic loopback mode, where the PM4341A T1XC T1 FRAMER/TRANSCEIVER AT are internally connected to is enabled. When DDLB is set is disabled. If diagnostic ration register. 10’ line is stic 88 ...
Page 106
... Mode 0 Details" in the "Test Features" section). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X PMCTST X DBCTRL 0 IOTST 0 HIZDATA 0 HIZIO 0 PM4341A T1XC T1 FRAMER/TRANSCEIVER 89 ...
Page 107
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 he tri-state modes of the T1XC . While logic 1 , all output pins o f the T1X e state mic roprocess ibits m icroproces sor PM4341A T1XC T1 FRAMER/TRANSCEIVER C except the data bus are or interface is still active. read cycles. 90 ...
Page 108
... The version identification bits, ID[6:0], are set to a fixed value representing the version number of the T1XC. The chip identification bit, TYPE, is set to logic 0 representing the T1XC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default TYPE 0 ID[6] 0 ID[5] 0 ID[4] 0 ID[3] 0 ID[2] 0 ID[1] 1 ID[0] 0 PM4341A T1XC T1 FRAMER/TRANSCEIVER 91 ...
Page 109
... A hardware reset clears the RESET bit, thus deasserting the software reset. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X RESET 0 PM4341A T1XC T1 FRAMER/TRANSCEIVER ...
Page 110
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default PSB[7] X PSB[6] X PSB[5] X PSB[4] X PSB[3] X PSB[2] X PSB[1] X PSB[0] X ailable on RCLKO) and a system timing 7). The count value corresponds to the location within the PM4341A T1XC T1 FRAMER/TRANSCEIVER X2M=0). By e-locked-loop ...
Page 111
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 s Word Op erati on Current PSB[7:5] 11X 1X1 000 000 tatus Wo rd registers (address 0EH and 0FH) are tatus Word MSB) is unfrozen and the contents may PM4341A T1XC T1 FRAMER/TRANSCEIVER ): Affect on PSB[8] toggle toggle toggle toggle SB register 94 ...
Page 112
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X PSB[8] X PM4341A T1XC T1 FRAMER/TRANSCEIVER efore ord LSB) 95 ...
Page 113
... Note that in Line Loopback mode (Register 0AH, LINELB bit =1) AGSEL should be set to logic 0 for optimal performance. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default AMI 0 Unused X Unused X Unused X Unused X ALGSEL 0 Unused X Unused X PM4341A T1XC T1 FRAMER/TRANSCEIVER ng DPLL logic 0, the jitter tolerance 96 ...
Page 114
... LCVE,LOSE,B8ZSE, Z8DE, and Z16DE are set to logic 0, disabling these events from generating an interrupt. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default LCVE 0 LOSE 0 B8ZSE 0 Z8DE 0 Z16DE 0 Unused X Unused X Unused X PM4341A T1XC T1 FRAMER/TRANSCEIVER s 97 ...
Page 115
... The current state of the LOS alarm can be determined by reading bit his register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default LCVI X LOSI X B8ZSI X Z8DI X Z16DI X Unused X Unused X LOS X PM4341A T1XC T1 FRAMER/TRANSCEIVER on the s 98 ...
Page 116
... ILS[2:0] bits are ignored and the default 330-440 ft. waveform template is selected. The eight available templates are selected via the following values of ILS[2:0]: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default RPT ILS[2] 0 ILS[1] 0 ILS[0] 0 PM4341A T1XC T1 FRAMER/TRANSCEIVER uired to 99 ...
Page 117
... The >660 setting is used when driving very long lines. The square pulse template allows the use of external line buildout networks with the T1XC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 t.) PM4341A T1XC T1 FRAMER/TRANSCEIVER 100 ...
Page 118
... TAP When DPME is set to log r alarm condition is disabled from generating PM4341A T1XC T1 FRAMER/TRANSCEIVER signal. leared when the register rtion of XPLS. When DPME driver performance consecutive bit N output pins occurs. The exact ic 0, detection of a driver an interrupt ...
Page 119
... Unused X Unused X CRA2 0 CRA1 0 CRA0 0 CRA0 Internal Code Register 0 CODE register #0 - first code applied 1 CODE register #1 0 CODE register #2 1 CODE register #3 0 CODE register #4 1 CODE register #5 0 CODE register #6 1 CODE register #7 - last code applied PM4341A T1XC T1 FRAMER/TRANSCEIVER 102 ...
Page 120
... DATA SHEET PMC-900602 See the Operation section for more details on setting up custom waveform templates. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER 103 ...
Page 121
... D[3:0] bits. CRD3 is the most significant bit. See the Operation section for more details on setting up custom waveform templates. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X CRD3 0 CRD2 0 CRD1 0 CRD0 0 PM4341A T1XC T1 FRAMER/TRANSCEIVER al register identified by 104 ...
Page 122
... UNDI is cleared by a read to this register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X OVRI X UNDI X PM4341A T1XC T1 FRAMER/TRANSCEIVER FIFO e FIFO gic 1, an underrun event 105 ...
Page 123
... FIFO. Upon reset of the T1XC, the default value set to decimal 47 (2FH). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default N1[7] 0 N1[6] 0 N1[5] 1 N1[4] 0 N1[3] 1 N1[2] 1 N1[1] 1 N1[0] 1 PM4341A T1XC T1 FRAMER/TRANSCEIVER put the 106 ...
Page 124
... PLL and, if the SYNC bit is high, will also res et the FIFO reset of the T1XC, the default value set to decimal 47 (2FH). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default N2[7] 0 N2[6] 0 N2[5] 1 N2[4] 0 N2[3] 1 N2[2] 1 N2[1] 1 N2[0] 1 PM4341A T1XC T1 FRAMER/TRANSCEIVER 107 ...
Page 125
... EMPTY or FULL alarm conditions. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X WIDEN 1 CENT 0 UNDE 0 OVRE 0 SYNC 1 LIMIT 1 the DJAT FIFO read and write pointers and PM4341A T1XC T1 FRAMER/TRANSCEIVER nt of energy sourced by T1XC 108 e ...
Page 126
... L. For example, if the PLL is operating so he reference clock by 24 UI, then the at the PL L sends to the FIFO will force its output C bit must be set and N2 (Registers19h and 1Ah) must be set PM4341A T1XC T1 FRAMER/TRANSCEIVER run event, respectively logic 0. If the SYNC bit is set h 109 . ...
Page 127
... TO LOGIC RESERVED SETTING AND SHOULD NOT BE USED. Upon reset of the T1XC, these bits are set to logic 0. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default ACCEL 0 Unused X Unused X Unused X Unused X Unused PM4341A T1XC T1 FRAMER/TRANSCEIVER 110 ...
Page 128
... Upon reset of the T1XC, SLIPE is set to logic 0, disabling generation of an interrupt. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X SLIPE 0 SLIPD X SLIPI X PM4341A T1XC T1 FRAMER/TRANSCEIVER 111 ...
Page 129
... T1XC. One channel of trouble code data will always be corrupted if the register is written while the receiver is out of frame. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default PM4341A T1XC T1 FRAMER/TRANSCEIVER n 112 ...
Page 130
... ESF frame search in the n the incoming data. A logic 0 oes not declare infram e while more than one framing bit PM4341A T1XC T1 FRAMER/TRANSCEIVER s criteria used by the framing bits in selects the ESF 113 ...
Page 131
... Select ESF framing format & 4 kHz FDL Data Select ESF framing format & 2 kHz FDL Data Rate using frames 3,7,11,15,19,23. Select ESF framing format & 2 kHz FDL Data Rate using frames 1,5,9,13,17,21 RESERVED PM4341A T1XC T1 FRAMER/TRANSCEIVER FMS1 and FMS0 bits select ata at the full 4 kHz rate from Rate 114 ...
Page 132
... T1DM formatted data. When BEEE is set to logic 1, the detection of a bit PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X ACCEL 0 COFAE 0 FERE 0 BEEE 0 SFEE 0 MFPE 0 INFRE 0 previous alignment. When COFAE is set to logic PM4341A T1XC T1 FRAMER/TRANSCEIVER new 115 ...
Page 133
... T1DM formatted data. When SFEE is set to severe ly errored framing event is allowed to gener ation of an interrupt when the frame find PM4341A T1XC T1 FRAMER/TRANSCEIVER nt superframe for SF, ESF, or hen ate is disabled from 116 f ...
Page 134
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default COFAI X FERI X BEEI X SFEI X MFPI X INFRI X MFP X INFR X FERI, BEEI, and SFEI indicate that the sition indicates that no change in the state of the n indicates that no state change occurred. PM4341A T1XC T1 FRAMER/TRANSCEIVER , hat gic 117 ...
Page 135
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X IDLE 0 AVC 0 BOCE 0 ation of an interrupt; a logic 0 in this bit position PM4341A T1XC T1 FRAMER/TRANSCEIVER hen 118 ...
Page 136
... T1XC is reset, the BOC[5:0] bits are set to l IDLEI bits are set to logic 0. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default IDLEI X BOCI X BOC[5] X BOC[4] X BOC[3] X BOC[2] X BOC[1] X BOC[0] X PM4341A T1XC T1 FRAMER/TRANSCEIVER tes ic 0 ogic 1, and the BOCI and 119 ...
Page 137
... The valid combinations of the ESF, FMS1, and FMS0 bits are summarized in the table below: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X ESF 0 FMS1 0 FMS0 0 Un used X Un used X PM4341A T1XC T1 FRAMER/TRANSCEIVER 120 ...
Page 138
... T 0 Select ESF fram ing 1 Select ESF fram ing 0 Selec t ESF fram ing Rate. 1 RESE RVED PM4341A T1XC T1 FRAMER/TRANSCEIVER ing format 1DM mode format & 4 kbit FDL Data Rate format & 2 kbit FDL Data Rate format & 2 kbit FDL Data 121 ...
Page 139
... CFA's can be enabled to generate an interrupt. Upon reset of the T1XC, these bits are cleared to logic 0. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X FASTD 0 ACCEL 0 YELE 0 REDE 0 AISE 0 PM4341A T1XC T1 FRAMER/TRANSCEIVER s of 122 ...
Page 140
... CFA state are cleared to logic 0 when thi reg ister is read. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X YELI X REDI X AISI X YEL X RED X AIS X state change in the corresponding CFA has generated PM4341A T1XC T1 FRAMER/TRANSCEIVER of s 123 ...
Page 141
... ESF framing format with a 2 kHz data link. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X REDD X YELD X AISD X PM4341A T1XC T1 FRAMER/TRANSCEIVER 124 ...
Page 142
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 ignal was present during the last 60ms logic 0, the AIS signal was absent during the last valid AIS signal is deemed to be present during conditio n has persisted for the entire interval and PM4341A T1XC T1 FRAMER/TRANSCEIVER 125 ...
Page 143
... SIGNALLING Control byte are passed on to the XBAS. When the PCCE bit is set to logic 0, the per-channel functions are disabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X IND 0 PCCE 0 PM4341A T1XC T1 FRAMER/TRANSCEIVER utput 126 ...
Page 144
... Register should be polled until the BUSY bit goes low before another µP acce request is initiated. A µP access request is typically completed within 640 ns. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default BUSY 0 Unused X Unused X Unused X Unused X Unused X Unused X Unused X PM4341A T1XC T1 FRAMER/TRANSCEIVER ss 127 ...
Page 145
... R/WB is set to a logic 1, a read from the internal TPSC register is requested; when R/WB is set to a logic 0, an write to the internal TPSC register requested. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default R/ PM4341A T1XC T1 FRAMER/TRANSCEIVER 128 ...
Page 146
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default arget register's address and R/WB=0 is written into PM4341A T1XC T1 FRAMER/TRANSCEIVER rnal TPSC the internal TPSC e read from the 1 is written into 129 ...
Page 147
... The bits within each control byte are allocated as follows: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 ata Control byte for Channel 1 ata Control byte for Channel 2 a Contr ol byte for Channel 23 ata Control byte for Channel 24 for Channel 24 PM4341A T1XC T1 FRAMER/TRANSCEIVER 130 ...
Page 148
... Effect on PCM Channel Data PCM Channel data is unchanged All 8 bits of the PCM channel data are inverted Only the MSB of the PCM channel data is inverted (SIGN bit inversion) All bits EXCEPT the MSB of the PCM channel data is inverted (Magnitude inversion) PM4341A T1XC T1 FRAMER/TRANSCEIVER 131 ...
Page 149
... GTE Zero Code Suppression ("jammed bit 8", excep in signalling frames when "jammed bit 7" is used if the signalling bit is 0) DDS Zero Code Suppression (data b with "10011000") Bell Zero Code Suppression ("jammed bit 7") PM4341A T1XC T1 FRAMER/TRANSCEIVER illiwatt pattern replaces the t yte replaced 132 ...
Page 150
... SIGC1 is set to logic 0, the insertion of signalling bits is disabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function IDLE7 IDLE6 IDLE5 IDLE4 IDLE3 IDLE2 IDLE1 IDLE0 Function SIGC0 SIGC1 Unused Unused PM4341A T1XC T1 FRAMER/TRANSCEIVER 133 ...
Page 151
... For SF and SLC®96 formats, the C' and and D bits from Signalling Control byte or BTSIG, respectively, a positions of every second superframe that is transmitted assumed that C=A and D=B. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 re inserted into the A and B signalling bit PM4341A T1XC T1 FRAMER/TRANSCEIVER 134 ...
Page 152
... Datalink Options register, the interrupt generated on the TDLINT output is also generated on the microprocessor INTB pin. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X EOM 0 INTE 0 ABT 0 CRC PM4341A T1XC T1 FRAMER/TRANSCEIVER 135 ...
Page 153
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 yte of data written in the Transmit Data present cket nded to the last data byte s is gene rated. The EOM bit is automatically cleared e next da ta packet begins. PM4341A T1XC T1 FRAMER/TRANSCEIVER e CRC bit is set then the transmitted and a 136 ...
Page 154
... The UDR bit can only be cleared by writing a logic 0 to the UDR bit position in this register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X INT 1 UDR 0 PM4341A T1XC T1 FRAMER/TRANSCEIVER bit is 137 ...
Page 155
... kbit/sec F to 1.0 0 ms. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default TD7 X TD6 X TD5 X TD4 X TD3 X TD2 X TD1 X TD0 X DL data rate this period corresponds PM4341A T1XC T1 FRAMER/TRANSCEIVER 138 ...
Page 156
... LAPD frame, empty the FIFO, c hing for a new flag sequence. The RFDL handle anner as if the EN bit had been cleared and then figuration register will reset itself after a rising and g is detected. PM4341A T1XC T1 FRAMER/TRANSCEIVER hen the block is enabled, it immediately lear the ...
Page 157
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X INTC1 0 INTC0 0 INT 0 Description Disable interrupts (All sources) Enable interrupt when FIFO receives data Enable interrupt when FIFO has 2 bytes of data Enable interrupt when FIFO has 3 bytes of data PM4341A T1XC T1 FRAMER/TRANSCEIVER 140 ...
Page 158
... DATA SHEET PMC-900602 The contents of the Enable/Status register should only be changed when the RFDL is disabled to prevent an PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 y erroneous interrupt generation. PM4341A T1XC T1 FRAMER/TRANSCEIVER 141 ...
Page 159
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default FE X OVR X FLG X EOM X CRC X NVB2 X NVB1 X NVB0 X a byte is read since the data frame can be alid NVB[2:0] and CRC bits, even though the EOM bit is PM4341A T1XC T1 FRAMER/TRANSCEIVER y indicates that only the 142 ...
Page 160
... RF DL has detected the presence of the LAPD n the d ata. FLG tected in the data first Status register read PM4341A T1XC T1 FRAMER/TRANSCEIVER a so that the Status will eset only when the LAPD abort hen the RFDL is disabled. riented ata 143 ...
Page 161
... RD1 X RD0 X le/Status register) is set to 01, the 11 the Rec eiver Data register must be read within giste r is read the causes an PM4341A T1XC T1 FRAMER/TRANSCEIVER PD abo rt sequence generated and the dat at the end of the FIFO underr un, then the 144 a ...
Page 162
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default ACCEL 0 Unused X Unused X Unused X DSEL1 0 DSEL0 0 ASEL1 0 ASEL0 0 ACTIVATE Code ASEL1 ASEL0 PM4341A T1XC T1 FRAMER/TRANSCEIVER CODE LENGTH 5 bits 6 (or 3*) bits 7 bits 8 (or 4*) bits 145 ...
Page 163
... The LBA and LBD bits indicate the current state of the corresponding loopback code detect indication. A logic 1 in these bit positions indicate the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default LBACP X LBDCP X LBAE 0 LBDE 0 LBAI X LBDI X LBA X LBD X PM4341A T1XC T1 FRAMER/TRANSCEIVER 146 ...
Page 164
... DATA SHEET PMC-900602 presence of that code has been detected; a logic 0 in these bit positions indicate the absence of that code. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 PM4341A T1XC T1 FRAMER/TRANSCEIVER 147 ...
Page 165
... Upon reset of the T1XC, the register contents are set to logic 0. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default ACT7 0 ACT6 0 ACT5 0 ACT4 0 ACT3 0 ACT2 0 ACT1 0 ACT0 0 PM4341A T1XC T1 FRAMER/TRANSCEIVER 148 ...
Page 166
... Up on reset of the T1XC, the register contents are set to logic 0. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default DACT7 0 DACT6 0 DACT5 0 DACT4 0 DACT3 0 DACT2 0 DACT1 0 DACT0 0 PM4341A T1XC T1 FRAMER/TRANSCEIVER f repetitions 149 ...
Page 167
... The valid combinations of the ESF, FMS1, and FMS0 bits are summarized in the table below: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X ESF 0 FMS1 0 FMS0 0 IND 0 PCCE 0 superframe or SLC®96 framing formats. A PM4341A T1XC T1 FRAMER/TRANSCEIVER F 150 ...
Page 168
... Select Superframe framing format 0 Selec t SLC®96 f ram 1 Disabl e signallin Select ESF fram ing ccess type: either indirect or direct. to logic 1 for proper w, disabl ing the ind ire PM4341A T1XC T1 FRAMER/TRANSCEIVER ing format xtraction format op eration. When the T1XC is ct access mode. ormed 151 el ...
Page 169
... Register should be polled until the BUSY bit goes low before another µP acce request is initiated. A µP access request is typically completed within 640 ns. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default BUSY 0 Unused X Unused X Unused X Unused X Unused X Unused X Unused X PM4341A T1XC T1 FRAMER/TRANSCEIVER ss 152 ...
Page 170
... R/WB is set to a logic 1, a read from the internal SIGX register is requested, when R/WB is set to a logic 0, an write to the internal SIGX regis requested. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default R/WB 0 Unused PM4341A T1XC T1 FRAMER/TRANSCEIVER est ter is 153 ...
Page 171
... The channel registers are allocated within the SIGX as follows: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused PM4341A T1XC T1 FRAMER/TRANSCEIVER nal SIGX registers nal SIGX registers itten into the 154 ...
Page 172
... Channel 24 Per-channel Configuration Data 39-3FH Ignored The bits within each channel register byte are allocated as follows: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Signalling Data Signalling Data rati on r-ch annel Configuration Data PM4341A T1XC T1 FRAMER/TRANSCEIVER 155 ...
Page 173
... If the state was not th e same, the current state (accessible via these registers) is not changed. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Unused Unused Unused Unused PM4341A T1XC T1 FRAMER/TRANSCEIVER ing 156 ...
Page 174
... Unused Unused INV FIX POL DEB the sense of POL is also inverted (i.e. if inversion is then the bit will be fixed to logic 0). whether a channel's signalling bits are to be debounced es before the signalling bits are changed to th PM4341A T1XC T1 FRAMER/TRANSCEIVER tion disables bit fixing state. 157 ...
Page 175
... GTE Zero Code Supp ression ("jammed bit 8", except in signalling frames when "jammed bit 7" is used if the signalling bit is 0) DDS Zero Code Suppression (data byte replaced with "10011000") Bell Zero Code Suppression ("jammed bit 7") PM4341A T1XC T1 FRAMER/TRANSCEIVER per-channel 158 ...
Page 176
... SLC®96 1 T1DM framing format (FDL data replaces R bit) 0 ESF framing format - 4 kbit/s data link 1 ESF framing format - 2 kbit/s data link (frames 3,7,11,15,19,23) 0 ESF framing format - 2 kbit/s data link (frames 1,5,9,13,17,21) 1 ESF framing format - 4 kbit/s data link PM4341A T1XC T1 FRAMER/TRANSCEIVER ted) 159 ...
Page 177
... When XAIS is set to logic 0, the XBAS bi-polar outputs operate normally. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X XYEL 0 XAIS 0 is set to logic 1, XBAS is enabled to PM4341A T1XC T1 FRAMER/TRANSCEIVER s, the Y-bit to 160 ...
Page 178
... The bit positions CL[1:0] (bits 1 & this register indicate the length of the inband loopback code sequence, as follows: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X CL1 0 CL0 0 PM4341A T1XC T1 FRAMER/TRANSCEIVER 161 ...
Page 179
... Codes bit in length may be accommodated by treating them as half double-sized code (i.e. a 3-bit code would use the 6-bit code length setting). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Code Le ngth PM4341A T1XC T1 FRAMER/TRANSCEIVER 162 ...
Page 180
... Wh en the T1XC is reset, the contents of this register are not affected. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default IBC7 X IBC6 X IBC5 X IBC4 X IBC3 X IBC2 X IBC1 X IBC0 X PM4341A T1XC T1 FRAMER/TRANSCEIVER ritten as the 6-bit 163 ...
Page 181
... PMON count registers (addresses 4AH-4FH). A write to any of these locations loads performance data located in the PMON into the internal holding PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Reserved 0 XFER 0 OVR 0 PM4341A T1XC T1 FRAMER/TRANSCEIVER 164 ...
Page 182
... When the T1XC is reset, the contents of the PMON count registers are unknown until the first latching of performance data is performed. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 register address space. The latching so tha t no events are missed. NOTE necessary to write PM4341A T1XC T1 FRAMER/TRANSCEIVER 165 ...
Page 183
... This register contains the lower eight bits of the 12 bit Line Code Violation event counter. A Line Code Violation event is defined as the occurrence of a Bipolar Violation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default LCV7 X LCV6 X LCV5 X LCV4 X LCV3 X LCV2 X LCV1 X LCV0 X PM4341A T1XC T1 FRAMER/TRANSCEIVER 166 ...
Page 184
... This register contains the upper four bits of the 12 bit Line Code Violation event counter. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X LCV11 X LCV10 X LCV9 X LCV8 X PM4341A T1XC T1 FRAMER/TRANSCEIVER 167 ...
Page 185
... SLC®96, and an F-bit or sync bit error (there can bits in error per frame) in T1DM. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default BEE7 X BEE6 X BEE5 X BEE4 X BEE3 X BEE2 X BEE1 X BEE0 X PM4341A T1XC T1 FRAMER/TRANSCEIVER -bit T 168 ...
Page 186
... Bit 0 R This register contains the upper bit of the 9-bit Bit Error event counter. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X Unused X BEE8 X PM4341A T1XC T1 FRAMER/TRANSCEIVER 169 ...
Page 187
... Bit 0 R This register contains the value of the 5 bit Framing Bit Error event counter. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X FER4 X FER3 X FER2 X FER1 X FER0 X PM4341A T1XC T1 FRAMER/TRANSCEIVER 170 ...
Page 188
... Change Of Frame Alignment events. The COFA bit in register 00H controls whet her Change of Frame Alignment or Out Of Frame events are counted. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X OO F2/COFA 2 X OOF1/COFA1 X OOF0/COFA0 X PM4341A T1XC T1 FRAMER/TRANSCEIVER 171 ...
Page 189
... PCM Control byte. When the PCCE bit is set to logic 0, the per-channel functions are disabled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X Unused X Unused X Unused X IND 0 PCCE 0 PM4341A T1XC T1 FRAMER/TRANSCEIVER utput 172 ...
Page 190
... Register should be polled until the BUSY bit goes low before another µP acce request is initiated. A µP access request is typically completed within 640 ns. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default BUSY 0 Unused X Unused X Unused X Unused X Unused X Unused X Unused X PM4341A T1XC T1 FRAMER/TRANSCEIVER ss 173 ...
Page 191
... R/WB is set to a logic 1, a read from the internal RPSC register is requested; when R/WB is set to a logic 0, an write to the internal RPSC register is requested. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default R/ PM4341A T1XC T1 FRAMER/TRANSCEIVER 174 ...
Page 192
... PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default written into the internal RPSC PM4341A T1XC T1 FRAMER/TRANSCEIVER st be written into B=0 is written into be read from the written into is register will 175 ...
Page 193
... Signalling Trunk Conditioning byte for Channel 23 48H S ignalling Trunk Conditioning byte for Channel 24 The bits within each control byte are allocated as follows: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Trunk Conditioning byte for Channel 2 PM4341A T1XC T1 FRAMER/TRANSCEIVER 176 ...
Page 194
... PCM Channel data is unchanged All 8 bits of the received PCM channel data are inverted Only the MSB of the received PCM channel data is inverted (SIGN bit inversion) All bits EXCEPT the MSB of the received PCM channel data is inverted (Magnitude inversion) PM4341A T1XC T1 FRAMER/TRANSCEIVER 177 ...
Page 195
... Digital milliwatt insertion t akes p recede nce o ver data trunk conditioning which, in turn, takes precedence over the various data inversi PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 al milliwatt insertion are ons. PM4341A T1XC T1 FRAMER/TRANSCEIVER s the 178 ...
Page 196
... BRPCM when the DTRKC bit in the PCM Control Byte is set to a logic 1. The Data Trunk Conditioning Code is transmitted from MSB (bit 7) to LSB (bit 0). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function DTRK7 DTRK6 DTRK5 DTRK4 DTRK3 DTRK2 DTRK1 DTRK0 PM4341A T1XC T1 FRAMER/TRANSCEIVER 179 ...
Page 197
... BRSIG when the STRKC bit logic 1. The Signalling Trunk Conditioning Code is placed in least significant nib ble of the channel byte. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function STRKC Unused Unused Unused PM4341A T1XC T1 FRAMER/TRANSCEIVER t 180 ...
Page 198
... PDV indication persists for the duration of the pulse density violation. At its minimum, PDV may be asserted for only 1 bit time, therefore, reading this bit PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X Unused X PDV X Z16DI X PDVI X Z16DE 0 PDVE 0 PM4341A T1XC T1 FRAMER/TRANSCEIVER 181 ...
Page 199
... DATA SHEET PMC-900602 may not return a logic 1 even though a pulse density violation has occurred. When the XPDE is enable PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 d for pulse stuffing, PDV remains logic 0. PM4341A T1XC T1 FRAMER/TRANSCEIVER 182 ...
Page 200
... HDLC packets currently being transmitted. When the register is written with 111111, the XBOC is dis abled. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE ISSUE 8 Function Default Unused X Unused X BC[5] 1 BC[4] 1 BC[3] 1 BC[2] 1 BC[1] 1 BC[0] 1 PM4341A T1XC T1 FRAMER/TRANSCEIVER 183 ...