M30843FJFP

Manufacturer Part NumberM30843FJFP
ManufacturerRenesas Electronics Corporation.
M30843FJFP datasheets

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Page 194/529:

Timer B

Download datasheet (4Mb)Embed
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M
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8 /
4
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M
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15.2 Timer B
Figure 15.16 shows a block diagram of the timer B. Figures 15.17 to 15.19 show registers associated with
the timer B. The timer B supports the following three modes. The TMOD1 and TMOD0 bits in the TBiMR
register (i=0 to 5) determine which mode is used.
• Timer mode : The timer counts an internal count source.
• Event counter mode : The timer counts pulses from an external source or overflow and underflow of
another timer.
• Pulse period/pulse width measurement mode : The timer measures pulse period or pulse width of an
external signal.
Table 15.8 lists TBi
pin settings.
IN
Select Clock Source
TCK1 and
TCK0
00
f
1
01
f
8
10
f
(1)
2n
11
f
c32
TBj Overflow
(2,3)
Signal
Polarity Switching
TBi
IN
and Edge Pulse
i=0 to 5
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select no
division (n=0) or divide-by-2n (n=1 to 15).
2. Overflow signal or underflow signal.
3. j=i-1, except j=2 when i=0 j=5 when i=3
TCK1 and TCK0, TMOD1 and TMOD0 : Bits in the TBiMR Register
TBiS : Bits in the TABSR and the TBSR Register
Figure 15.16 Timer B Block Diagram
Timer Bi Register
b15
b8 b7
NOTES:
1. Use 16-bit data for reading and writing.
2. The TBi register counts how many pulse inputs are provided externally or how many times another
timer counter overflows and underflows.
Figure 15.17 TB0 to TB5 Registers
Page 173
R
e
. v
1
0 .
1
J
u
. l
0
, 7
2
0
0
5
R
E
J
0
9
B
0
0
3
6
0 -
1
0
1
C
8 /
4
) T
00: Timer Mode
TMOD1 and
01: Pulse Period/Pulse Width
TMOD0
Measurement Mode
01: Event
TCK1
Counter Mode
1
0
Counter Reset Circuit
(1)
(i=0 to 5)
Symbol
Address
b0
TB0 to TB2
0351
- 0350
, 0353
16
16
TB3 to TB5
0311
- 0310
, 0313
16
16
Mode
Function
If setting value is n, a count source
Timer Mode
is divided by n+1
Event Counter
If setting value is n, a count source
Mode
is divided by n+1
A count source is incremented
Pulse Period/Pulse
between one valid edge and
Width Measurement
Mode
another valid edge of TBi
f o
4
9
5
15. Timer (Timer B)
High-order Bits of Data Bus
Low-order Bits of Data Bus
8 low-order
bits
Reload Register
Counter
TBiS
TBi
Address
TBj
Timer B0
0351
0350
Timer B2
16
16
Timer B1
0353
0352
Timer B0
16
16
Timer B2
0355
0354
Timer B1
16
16
Timer B3
0311
0310
Timer B5
16
16
Timer B4
0313
0312
Timer B3
16
16
Timer B5
0315
0314
Timer B4
16
16
After Reset
- 0352
, 0355
- 0354
Indeterminate
16
16
16
16
- 0312
, 0315
- 0314
Indeterminate
16
16
16
16
Setting Range
0000
to FFFF
16
16
0000
to FFFF
16
16
(2)
pulse
IN
8 high-
order
bits
RW
RW
RW
RO

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