M30843FJFP

Manufacturer Part NumberM30843FJFP
ManufacturerRenesas Electronics Corporation.
M30843FJFP datasheets

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Page 251/529:

Clock Phase Setting Function

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17.4.2 Clock Phase Setting Function
The CKPH bit in the UiSMR3 register (i=0 to 4) and the CKPOL bit in the UiC0 register select one of four
combinations of transfer clock polarity and phases.
The transfer clock phase and polarity must be the same between the master and the slave involved in the
transfer.
17.4.2.1 When setting the DINC Bit to "0" (Master (Internal Clock))
Figure 17.24 shows transmit and receive timing.
17.4.2.2 When Setting the DINC Bit to "1" (Slave (External Clock))
When the CKPH bit is set to "0" (no clock delay) and the SSi input pin is held high ("H"), the STxDi pin
is placed in a high-impedance state. When the SSi input pin becomes low ("L"), conditions to start a
serial transfer are met, but output is indeterminate. The serial transmission is synchronized with the
transfer clock. Figure 17.25 shows the transmit and receive timing.
When the CKPH bit is set to "1" (clock delay) and the SSi input pin is held high, the STxDi pin is placed
in a high-impedance state. When the SSi pin becomes low, the first data is output. The serial transmis-
sion is synchronized with the transfer clock. Figure 17.26 shows the transmit and receive timing.
Signal Applied to
the SS Pin
Clock Output
(CKPOL=0, CKPH=0)
Clock Output
(CKPOL=1, CKPH=0)
Clock Output
(CKPOL=0, CKPH=1)
Clock Output
(CKPOL=1, CKPH=1)
Data Output Timing
Data Input Timing
Figure 17.24 Transmit and Receive Timing in Master Mode (Internal Clock)
Page 230
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_____
_____
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"H"
"L"
"H"
"L"
"H"
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"L"
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17. Serial I/O (Special Function)
_____
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