M30843FJFP

Manufacturer Part NumberM30843FJFP
ManufacturerRenesas Electronics Corporation.
M30843FJFP datasheets

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Page 328/529:

Transmit Buffer (Receive Data) Register

Download datasheet (4Mb)Embed
PrevNext
M
3
2
C
8 /
4
G
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M
3
2
C
8 /
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M
3
2
SI/O Special Communication Interrupt Detect Register 1
b7
b6
b5
b4
b3
b2
b1
0
NOTES:
1. The G1IRF register is used in special communication mode or HDLC data processing mode. It must
be in a reset state or set to "00
2. The SRT1R bit in the IIO4IR register is also set to "1" if the BSERR, ABT or IRF0 to IRF3 bit is set to "1".

Transmit Buffer (Receive Data) Register

b7
Figure 22.27 G1IRF Register, G0TB and G1TB / G0DR and G1DR Registers
Page 307
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1
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0
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2
0
0
5
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0
9
B
0
0
3
6
0 -
1
0
1
C
8 /
4
) T
b0
Symbol
Address
0
G1IRF
013E
16
Bit
Bit Name
Symbol
Reserved Bit
Set to "0"
(b1 - b0)
Bit Stuffing Error
0 : Not detected
BSERR
Detect Flag
1 : Detected
Arbitration Lost
0 : Not detected
ABT
Detect Flag
1 : Detected
0 : The G1DR register (receive data register)
Interrupt Cause
does not match the G1CMP0 register
IRF0
Determination
1 : The G1DR register (receive data register)
Flag 0
matches the G1CMP0 register
0 : The G1DR register (receive data register)
Interrupt Cause
does not match the G1CMP1 register
IRF1
Determination
1 : The G1DR register (receive data register)
Flag 1
matches the G1CMP1 register
0 : The G1DR register (receive data register)
Interrupt Cause
does not match the G1CMP2 register
IRF2
Determination
1 : The G1DR register (receive data register)
Flag 2
matches the G1CMP2 register
0 : The G1DR register (receive data register)
Interrupt Cause
does not match the G1CMP3 register
IRF3
Determination
1 : The G1DR register (receive data register)
Flag 3
matches the G1CMP3 register
" in clock synchronous serial I/O mode or UART mode.
16
(i=0,1)
b0
Symbol
Address
G0TB, G0DR
00EA
16
G1TB, G1DR
012A
16
Function
Set data to be transmitted.
In HDLC data processing mode, the receive data register is read by
reading the GiTB register. Value is written to the transmit buffer register
by writing it to the GiTB register. In HDLC data processing mode, the
value set in the GiRI register is transferred to the GiDR register.
f o
4
9
5
22. Intelligent I/O (Communication Function)
(1,2)
After Reset
00
16
Function
RW
RW
RW
RW
RW
RW
RW
RW
After Reset
Indeterminate
Indeterminate
RW
RW

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