82562EX Intel Corporation, 82562EX Datasheet
82562EX
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82562EX Summary of contents
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Dual Footprint Design Guide Networking Silicon 317520-002 Revision 2.2 ...
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... North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777, Germany 44-0-1793-421-333, other Countries 708- 296-9333. Intel® trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries. Copyright © Intel Corporation, 2008 *Third-party brands and names are the property of their respective owners. ...
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... Crystal validation methods • Crystal testing methods Changed signal name FL_SO to the correct signal name FLSH_SO. Added 82562EX applicability. Added new values for TX and RX terminations (next to LAN silicon). New values are now 110 Ω for both TX and RX terminations. Added new starting values for RBIAS100 and RBIAS10. New starting values are now 649 Ω ...
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Contents 1.0 Introduction......................................................................................................................... 1 1.1 Scope............................................................................................................................................ 1 1.2 Reference Documents .................................................................................................................. 2 1.3 Product Codes .............................................................................................................................. 2 2.0 System Data Port Interfaces .............................................................................................. 3 2.1 LCI Connection to 82562EZ(EX) Platform LAN Connect Device ................................................. 3 2.2 CSA Port Connection to ...
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Dual Footprint Design Guide 4.1.11 Traces for Decoupling Capacitors ................................................................................. 26 4.1.12 Ground Planes Under the Magnetics Module................................................................ 26 4.1.13 Special Considerations for Non-Integrated Magnetics Modules and RJ-45 Connectors................................................................... 28 4.2 Layout for the 82562EZ(EX) Platform LAN Connect Device ...
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Tables 1 LAN Component Connections/Features ....................................................................................... 1 2 Product Ordering Codes ............................................................................................................... 2 3 CSA Port Reference Circuit Specifications................................................................................... 4 4 CSA Port CI_RCOMP Resistor Values......................................................................................... 5 5 Crystal Parameters ....................................................................................................................... 7 6 82547GI(EI) Recommended Crystals...........................................................................................8 7 82562EZ(EX) Memory Layout ...
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... Table 1. LAN Component Connections/Features LAN Component ® Intel 82547GI(EI) ® Intel 82562EX (196 BGA) ® Intel 82562EZ (196 BGA) 1.1 Scope This application note contains Ethernet design guidelines applicable to LOM designs based on the ® ...
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... Programming information can be obtained through your local Intel representative. 1.3 Product Codes Table 2 lists the product ordering codes for the 82562EZ(EX)and 82547GI(EI). Table 2. Product Ordering Codes Device 82562EZ GD82562EZ 82562EX GD82562EX 82547GI GD82547GI 82547EI GD82547EI 2 Product Code Product Code (Lead Free) LU82562EZ LU82562EX LU82547GI LU82547EI ...
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System Data Port Interfaces The 82562EZ(EX) Platform LAN Connect Device and the 82547GI(EI) Gigabit Ethernet controller employ different system interfaces, as illustrated in GMCH CSA LCI Intel® ICH5 Figure 1. ICH5 Platform LAN Connect Sections 2.1 LCI Connection to ...
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Dual Footprint Design Guide 2.2 CSA Port Connection to 82547GI(EI) Gigabit Ethernet Controller The 82547GI(EI) Gigabit Ethernet Controller uses the Communications Streaming Architecture (CSA) port to connect to the Memory Control Hub (MCH). CSA is a point-to-point interface supporting ...
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The values of R1, R2 and R3 must be rated at ±1% tolerance. The selected resistor values must also ensure that the reference voltage and reference swing voltage tolerance are maintained over the input leakage specification. A 0.1 µF capacitor ...
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Ethernet Component Design Guidelines These sections provide recommendations for selecting components and connecting special pins. The main design elements are the 82562EZ(EX) Platform LAN Connect device or the 82547GI(EI) Gigabit Ethernet Controller, an integrated magnetics module with RJ-45 connector, ...
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Dual Footprint Design Guide .Table 6 lists the approved crystals for use with the 83547GI(EI) B1 steppings. Table 6. 82547GI(EI) Recommended Crystals Raltron (<20 Ω ESR and +/-30 ppm) TXC 3.1.1.1 Vibration Mode Crystals in the frequency range listed ...
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A crystal specified and tested as series resonant oscillates without problem in a parallel-resonant circuit, but the frequency is higher than nominal by several hundred parts per million. The purpose of adding load capacitors to a crystal circuit is to ...
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Dual Footprint Design Guide Standard capacitor loads used by crystal manufacturers include 16 pF and 20 pF. Any of these values will generally operate with the controller. However, a difference of several picofarads between the calibrated load ...
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Reference Crystal Selection There are several methods available for choosing the appropriate reference crystal: • Saunders and Associates (S&A) crystal network analyzer is available, then discrete crystal components can be tested until one is found with zero ...
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Dual Footprint Design Guide 3.1.6 Integrated Magnetics Module The magnetics module has a critical effect on overall IEEE and regulatory conformance. The device should meet the performance required for a design with reasonable margin to allow for manufacturing variation. ...
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Super IO GP Port or ICHx GPIO 24, 25, 27 µController (mobile) Sensor/ Supervisor Figure 5. LAN Disable Circuitry Note: The 100 Ω resistors for the Test Mode signals are required for the Exclusive OR (XOR) Tree and ...
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Dual Footprint Design Guide Table 8. 82562EZ(EX) Memory Layout (512 Byte EEPROM) 00h 3Fh 40h FFh NOTE: Legacy manageability only. 3.2.3 Magnetics Modules for 82562EZ(EX) PLC Device A 5-core magnetics module should be carefully selected for your design. integrated ...
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For best results, do not attempt to use the LAN_POWER_GOOD signal for a LAN disable input. This pin is intended to operate as a power-on reset connected to a power monitor circuit. The input of FLSH_SO (ball P9) is the ...
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Dual Footprint Design Guide For non-ASF applications, use a 64 register by 16-bit Microwire serial EEPROM. For ASF 1.0 applications, use larger 93C66 Microwire or AT25040 SPI* Serial EEPROM. ASF 2.0 requires an 8K SPI* Serial EEPROM. Intel has ...
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EEPROM Map Information Table 12 summarizes the EEPROM map for the 82547GI(EI) Gigabit Ethernet Controller. Table 12. 82547GI(EI) EEPROM Memory Layout 00h HW/SW Reserved Area 3Fh 40h ASF and Legacy FFh 100h Packet Filter Data 19F 1A0 ... Manageability ...
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Dual Footprint Design Guide Instead of using external regulators to supply 1.2 V and 1.8 V, the designer can use power transistors in conjunction with on-chip regulation circuitry. See the reference schematic for an implementation example. The 82547GI(EI) controller ...
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Device Test Capability The 82547GI(EI) Gigabit Ethernet Controller contains a test access port conforming to the IEEE 1149.1a-1994 (JTAG) Boundary Scan specification. To use the test access port, connect these balls to pads accessible by your test equipment. ...
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Ethernet Component Layout Guidelines These sections provide recommendations for performing printed circuit board layouts. Good layout practices are essential to meet IEEE PHY conformance specifications and EMI regulatory requirements. 4.1 General Layout Considerations for Ethernet Controllers Critical signal traces ...
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Dual Footprint Design Guide Keep silicon traces at least 1 inch from edge of PCB (2 inches preferred) LAN Silicon Figure 5. General Placement Distances Figure 5 shows some basic placement distance guidelines. The figure shows two differential pairs, ...
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Layer 3 is used for power planes. • Layer signal layer. For Gigabit designs common to route two of the differential pairs on this layer. This board stack up configuration can be adjusted to ...
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Dual Footprint Design Guide • The reference plane for the differential pairs should be continuous and low impedance recommended that the reference plane be either ground or 1.8 V (the voltage used by the PHY). This provides ...
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Impedance Discontinuities Impedance discontinuities cause unwanted signal reflections. Avoid vias (signal through holes) and other transmission line irregularities. If vias must be used, a reasonable budget is two per differential trace. Unused pads and stub traces should also be ...
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Dual Footprint Design Guide The following guidelines help reduce circuit inductance in both backplanes and motherboards: • Route traces over a continuous plane with no interruptions. Do not route over a split power or ground plane. If there are ...
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Figure 8 below shows the preferred method for implementing a ground split under an integrated magnetics module/RJ-45 connector. The capacitor stuffing options (C1 – C6) are used to reduce/ filter high frequency emissions. The value(s) of the capacitor stuffing options ...
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Dual Footprint Design Guide 4.1.13 Special Considerations for Non-Integrated Magnetics Modules and RJ-45 Connectors It is possible to employ discrete (non-integrated) magnetics modules and RJ-45 connectors. Similar rules will apply to design and layout. The differential pairs should be ...
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Layout for the 82562EZ(EX) Platform LAN Connect Device This section provides layout guidelines specific to the 82562EZ(EX) PLC device. 4.2.1 Termination Resistors for Designs Based on 82562EZ(EX) PLC Device Two differential pairs are terminated using 54.9 Ω (1% tolerance) ...
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Dual Footprint Design Guide 4.3 Layout for the 82547GI(EI) Gigabit Ethernet Controller 4.3.1 Termination Resistors for Designs Based on 82547GI(EI) Gigabit Ethernet Controller The four differential pairs are terminated with 49.9 Ω (1% tolerance) resistors, placed near the 82547GI(EI) ...
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Troubleshooting Common Physical Layout Issues The following is a list of common physical layer design and layout mistakes in LAN On Motherboard Designs. 1. Unequal length of the two traces within a differential pair. Inequalities create common-mode noise and ...
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Design and Layout Checklists The Design and Layout checklists are in Portable Data Format (PDF) and available to aid designers via: http://developer.intel.com. 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide 33 ...
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Ball Number to Signal Mapping with Population Options Table 14 lists the ball names for both devices corresponding to the shared ball number. Please note that signal names may vary slightly from the names on the reference schematic in ...
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Dual Footprint Design Guide Table 14. Ball Number to Signal Mapping (Sheet (Continued) Ball 82562EZ(EX) 82547GI(EI) Pin Ref Pin Name Name B11 SPDLED# LED2/LINK100# B12 TOUT LED3/LINK1000# B13 RBIAS100 CTRL18 B14 RBIAS10 IEEE_TEST ...
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Table 14. Ball Number to Signal Mapping (Sheet (Continued) Ball 82562EZ(EX) 82547GI(EI) Pin Ref Pin Name Name D10 ISOL_EXEC NC D11 NC 1.8 V D12 ISOL_TI 1.8 V D13 VSSA ANALOG_VSS D14 ISOL_TCK IEEE_TEST- E1 VCC 3.3 ...
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Dual Footprint Design Guide Table 14. Ball Number to Signal Mapping (Sheet (Continued) Ball 82562EZ(EX) 82547GI(EI) Pin Ref Pin Name Name F11 VSS VSS F12 NC NC F13 NC MDI[2]+ F14 NC MDI[2 CI_CLK ...
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Table 14. Ball Number to Signal Mapping (Sheet (Continued) Ball 82562EZ(EX) 82547GI(EI) Pin Ref Pin Name Name J2 NC CI[ CI[ CSA_1.2V J5 VCCR 1 VCC 1 VCC 1.2 ...
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Dual Footprint Design Guide Table 14. Ball Number to Signal Mapping (Sheet (Continued) Ball 82562EZ(EX) 82547GI(EI) Pin Ref Pin Name Name L7 ADV10 VCC 1.2 V L10 VCC 1.2 V L11 ...
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Table 14. Ball Number to Signal Mapping (Sheet (Continued) Ball 82562EZ(EX) 82547GI(EI) Pin Ref Pin Name Name N2 NC CI[ CI_RCOMP N4 NC CI_VREF VCC 3 ...
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Dual Footprint Reference Schematic The following pages illustrate a dual purpose 10/100 and 10/100/1000 design using the 82562EZ(EX) Platform LAN Connect device and the 82547GI(EI) Gigabit Ethernet Controller. 82562EZ(EX)/82547GI(EI) Dual Footprint Design Guide 43 ...
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Dual Footprint Design Guide 46 Pins VDD Pins VSS ...
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Appendix A Measuring LAN Reference Frequency Using a Frequency Counter A.1 Background To comply with IEEE specifications for 10/100 Mbps and 10/100/1000Base-T Ethernet LAN, the transmitter reference frequency must be correct and accurate within ±50 parts per million (ppm). Note: ...
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Dual Footprint Design Guide A.3 Indirect Probing Method The indirect probing test method is applicable foremost devices that support 100BASE-T. Since probe capacitance can load the reference crystal and affect the measured frequency, the preferred method is to use ...
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A.4 Indirect Frequency Measurement and Frequency Accuracy Calculation Steps 1. Make sure the system BIOS has the LAN controller enabled. 2. Connect the test equipment as shown in 3. Using the appropriate controls for your model of high resolution digital ...
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Dual Footprint Design Guide Example 2. Given: The measured averaged center frequency is 125.00087 MHz (or 125,000,870 Hertz). FrequencyAccuracy ppm Note: The following items should be noted for an ideal reference crystal on a typical printed circuit board. • ...
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Figure 12. Direct Probing Method A.6 Direct Frequency Measurement and Frequency Accuracy Calculation Steps 1. Make sure the system BIOS has the LAN controller enabled. 2. Connect the test equipment as shown in 3. Using the appropriate controls for your ...
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Dual Footprint Design Guide where x = Average measured frequency in Hertz and y = Ideal reference frequency in Hertz Example 3. Given: The measured averaged center frequency is 24.99963 MHz (or 24,999,630 Hertz). FrequencyAccuracy ppm Example 4. Given: ...
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Appendix B GigConf.exe Register Settings for 82547GI(EI) Devices The following steps describe the indirect probing test method using GigConf.exe for 82547GI(EI) devices. 1. Boot to DOS using a DOS Boot Diskette. 2. Launch Gigconf from the diskette (gigconf.exe). 3. Select ...
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