MPC972 Freescale Semiconductor, Inc, MPC972 Datasheet

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MPC972

Manufacturer Part Number
MPC972
Description
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Low Voltage PLL Clock Driver
devices targeted for high performance CISC or RISC processor based
systems. With output frequencies of up to 125MHz and skews of 550ps
the MPC972/973 are ideally suited for most synchronous systems. The
devices offer twelve low skew outputs plus a feedback and sync output for
added flexibility and ease of system implementation.
programmability between the 12 outputs as well as the input vs output
relationships. Using the select lines output frequency ratios of 1:1, 2:1,
3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 6:1 and 6:5 between outputs can be
realized by pulsing low one clock edge prior to the coincident edges of the
Qa and Qc outputs. The Sync output will indicate when the coincident
rising edges of the above relationships will occur. The selectability of the
feedback frequency is independent of the output frequencies, this allows
for very flexible programming of the input reference vs output frequency
relationship. The output frequencies can be either odd or even multiples
of the input reference. In addition the output frequency can be less than
the input frequency for applications where a frequency needs to be
reduced by a non–binary factor. The Power–On Reset ensures proper
programming if the frequency select pins are set at power up. If the
fselFB2 pin is held high, it may be necessary to apply a reset after
power–up to ensure synchronization between the QFB output and the
other outputs. The internal power–on reset is designed to provide this
function, but with power–up conditions being system dependent, it is
difficult to guarantee. All other conditions of the fsel pins will automatically
synchronize during PLL lock acquisition.
debug as well as provide unique opportunities for system power down schemes to meet the requirements of “green” class
machines. The MPC972 allows for the enabling of each output independently via a serial input port. When disabled or “frozen”
the outputs will be locked in the “LOW” state, however the internal state machines will continue to run. Therefore when “unfrozen”
the outputs will activate synchronous and in phase with those outputs which were not frozen. The freezing and unfreezing of
outputs occurs only when they are already in the “LOW” state, thus the possibility of runt pulse generation is eliminated. A
power-on reset will ensure that upon power up all of the outputs will be active. Note that all of the control inputs on the
MPC972/973 have internal pull–up resistors.
compatible levels while the outputs provide LVCMOS levels with the capability to drive 50Ω transmission lines. For series
terminated lines each MPC972/973 output can drive two 50Ω lines in parallel thus effectively doubling the fanout of the device.
AN1545/D in the Timing Solutions book (BR1333/D) for a discussion on the thermal issues with the MPC family of clock drivers.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
8/97
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1997
Fully Integrated PLL
Output Frequency up to 125MHz
Compatible with PowerPC
TQFP Packaging
3.3V V CC
The MPC972/973 are 3.3V compatible, PLL based clock driver
The MPC972/973 features an extensive level of frequency
The MPC972/973 offers a very flexible output enable/disable scheme. This enable/disable scheme helps facilitate system
The MPC972/973 is fully 3.3V compatible and requires no external loop filter components. All inputs accept LVCMOS/LVTTL
The MPC972/973 can consume significant power in some configurations. Users are encouraged to review Application Note
100ps Typical Cycle–to–Cycle Jitter
and Pentium
1
Microprocessors
REV 1
PLL CLOCK DRIVER
52–LEAD TQFP PACKAGE
LOW VOLTAGE
MPC972
MPC973
CASE 848D-03
FA SUFFIX

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MPC972 Summary of contents

Page 1

... LVCMOS levels with the capability to drive 50Ω transmission lines. For series terminated lines each MPC972/973 output can drive two 50Ω lines in parallel thus effectively doubling the fanout of the device. The MPC972/973 can consume significant power in some configurations. Users are encouraged to review Application Note AN1545/D in the Timing Solutions book (BR1333/D) for a discussion on the thermal issues with the MPC family of clock drivers ...

Page 2

... MPC972 MPC973 39 38 fselb1 40 fselb0 41 fsela1 42 fsela0 43 Qa3 44 VCCO 45 Qa2 46 GNDO 47 Qa1 48 VCCO 49 Qa0 50 GNDO 51 VCO_Sel FUNCTION TABLE 1 fsela1 fsela0 FUNCTION TABLE 2 fselFB2 fselFB1 fselFB0 ...

Page 3

... BR1333 — Rev VCO LPF Sync Pulse Data Generator Output Disable 12 Circuitry Figure 2. Logic Diagram 3 MPC972 MPC973 Sync Qa0 D Q Frz Qa1 Qa2 Qa3 Sync Qb0 D Q Frz Qb1 Qb2 Qb3 Sync Qc0 ...

Page 4

... MPC972 MPC973 fVCO Qa Qc Sync Qa Qc Sync Qc( 2) Qa( 6) Sync Qa( 4) Qc( 6) Sync Qc( 2) Qa( 8) Sync Qa( 6) Qc( 8) Sync Qa( 12) Qc( 2) Sync MOTOROLA 1:1 Mode 2:1 Mode 3:1 Mode 3:2 Mode 4:1 Mode 4:3 Mode 6:1 Mode Figure 3. Timing Diagrams 4 TIMING SOLUTIONS BR1333 — Rev 6 ...

Page 5

... V CMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the V CMR range and the input lies within the V PP specification. 2. The MPC972/973 outputs can drive series or parallel terminated 50Ω (or 50Ω /2) transmission lines on the incident edge (see Applications Info section). ...

Page 6

... This inversion allows for the development of 180 phase shifted clocks. This output could also be used as a feedback output to the MPC972/973 or a second PLL device to generate early or late clocks for a specific design. Figure 11 illustrates the use of two ...

Page 7

... MPC972/973’s to generate two banks of clocks with one bank divided by 2 and delayed by 180 relative to the first. Using the MPC973 as a Zero Delay Buffer The external feedback of the MPC973 clock driver allows for its use as a zero delay buffer. By using one of the outputs as a feedback to the PLL the propagation delay through the device is eliminated ...

Page 8

... MPC972 MPC973 400 300 200 100 0 –100 –200 –300 –400 Qc3 Qc2 Qc1 500 400 Max 300 200 100 Nom 0 –100 Min –200 Reference Clock Frequency (MHz) Figure 5. Static Phase Offset versus Reference Frequency T pd versus TCLK 60 58 ...

Page 9

... Qc 66MHz ‘0’ fselFB2 ‘1’ Inv_Clk QFB 66MHz Input Ref Ext_FB Figure 11. Phase Delay Using Multiple MPC972/973’s TIMING SOLUTIONS BR1333 — Rev 6 ‘0’ fsela0 ‘0’ fsela1 100MHz ‘0’ fselb0 fselb1 ‘0’ 40MHz ‘ ...

Page 10

... The on–board oscillator is completely self contained so that the only external component required is the crystal. As the oscillator is somewhat sensitive to loading on its inputs the user is advised to mount the crystal as close to the MPC972 as possible to avoid any board level parasitics. To facilitate co–location surface mount crystals are recommended, but not required ...

Page 11

... VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC972/973 clock driver. For the series terminated case however there current draw, thus the outputs can drive multiple series terminated lines ...

Page 12

... NRZ freeze enable bits. The period of each Frz_Data bit equals the period of the free–running Frz_Clk signal. The Frz_Data serial transmission should be timed so the MPC972 can sample each Frz_Data bit with the rising edge of the free–running Frz_Clk signal. Start ...

Page 13

... 0.10 (0.004) T VIEW θ1 0.25 (0.010) θ GAGE PLANE MPC972 MPC973 –X– X= VIEW Y BASE METAL F PLATING É É É É Ç Ç Ç Ç É É É É Ç Ç Ç Ç D 0.13 (0.005) T L– ...

Page 14

... MPC972 MPC973 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...

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