MPC950 Freescale Semiconductor, Inc, MPC950 Datasheet

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MPC950

Manufacturer Part Number
MPC950
Description
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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Low Voltage PLL Clock Driver
devices targeted for high performance clock tree designs. With output
frequencies of up to 180MHz and output skews of 375ps the MPC950 is
ideal for the most demanding clock tree designs. The devices employ a
fully differential PLL design to minimize cycle–to–cycle and long term
jitter. This parameter is of significant importance when the clock driver is
providing the reference clock for PLL’s on board today’s microprocessors
and ASiC’s. The devices offer 9 low skew outputs, the outputs are
configurable to support the clocking needs of the various high
performance microprocessors.
to provide input reference clock flexibility. The FBSEL pin will choose
between a divide by 8 or a divide by 16 of the VCO frequency to be
compared with the input reference to the MPC950. The internal VCO is
running at either 2x or 4x the high speed output, depending on
configuration, so that the input reference will be either one half, one fourth
or one eighth the high speed output.
an external feedback input. These features allow for the MPC951 to be used as a zero delay, low skew fanout buffer. In addition,
the external feedback allows for a wider variety of input–to–output frequency relationships. The MPC951 REF_SEL pin allows for
the selection of an alternate LVCMOS input clock to be used as a test clock or to provide the reference for the PLL from an
LVCMOS source.
pin allows the user to select between a crystal input to an on–board oscillator for the reference or to chose a TTL level oscillator
input directly. The on–board crystal oscillator requires no external components beyond a series resonant crystal.
LVCMOS or LVTTL compatible levels while the outputs provide LVCMOS levels with the capability to drive terminated 50Ω
transmission lines. Select inputs do not have internal pull–up/pull–down resistors and thus must be set externally. If the
PECL_CLK inputs are not used, they can be left open. For series terminated 50Ω lines, each of the MPC950/951 outputs can
drive two traces giving the device an effective fanout of 1:18. The device is packaged in a 7x7mm 32–lead TQFP package to
provide the optimum combination of board density and performance.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
2/97
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1997
Fully Integrated PLL
Oscillator or Crystal Reference Input
Output Frequency up to 180MHz
Outputs Disable in High Impedance
Compatible with PowerPC , Intel and High Performance RISC
Microprocessors
TQFP Packaging
Output Frequency Configurable
The MPC950/951 are 3.3V compatible, PLL based clock driver
Two selectable feedback division ratios are available on the MPC950
The MPC951 replaces the crystal oscillator and internal feedback of the MPC950 with a differential PECL reference input and
The MPC950 provides an external test clock input for scan clock distribution or system diagnostics. In addition the REF_SEL
Both the MPC950 and MPC951 are fully 3.3V compatible and require no external loop filter components. All inputs accept
100ps Typical Cycle–to–Cycle Jitter
1
REV 4
PLL CLOCK DRIVER
32–LEAD TQFP PACKAGE
LOW VOLTAGE
MPC950
MPC951
CASE 873A–02
FA SUFFIX

Related parts for MPC950

MPC950 Summary of contents

Page 1

... Select inputs do not have internal pull–up/pull–down resistors and thus must be set externally. If the PECL_CLK inputs are not used, they can be left open. For series terminated 50Ω lines, each of the MPC950/951 outputs can drive two traces giving the device an effective fanout of 1:18. The device is packaged in a 7x7mm 32–lead TQFP package to provide the optimum combination of board density and performance ...

Page 2

... MR/OE fseld GNDO VCCO MPC950 GNDO 29 TCLK 30 PLL_En 31 Ref_Sel MOTOROLA MPC950 LOGIC DIAGRAM PHASE VCO DETECTOR 200–480MHz LPF 8/ 16 POWER–ON RESET Qd2 15 VCCO 14 Qd3 13 GNDO 12 Qd4 11 VCCO 10 MR/OE 9 xtal2 ...

Page 3

... LPF POWER–ON RESET Qd2 15 VCCO 14 Qd3 13 GNDO 12 Qd4 11 VCCO 10 MR/OE 9 PECL_CLK MPC950 MPC951 Qc0 4/ 8 Qc1 Qd0 4/ 8 Qd1 Qd2 Qd3 Qd4 FUNCTION TABLES Ref_Sel Function 1 TCLK 0 PECL_CLK PLL_En Function 1 PLL Enabled 0 ...

Page 4

... V CMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “HIGH” input is within the V CMR range and the input swing lies within the V PP specification. 2. The MPC950/951 outputs can drive series or parallel terminated 50Ω (or 50Ω /2) transmission lines on the incident edge (see Applications Info section). ...

Page 5

... The relationship between the input reference and the output frequency is also very flexible. Table 2 shows the multiplication factors between the inputs and outputs for the MPC950. For external feedback (MPC951) Table 1 can be used to determine the multiplication factor, there are too many potential combinations to tabularize the external feedback condition ...

Page 6

... Table 2. Input Reference versus Output Frequency Relationships (MPC950 Only) Config fsela fselb fselc ...

Page 7

... Unfortunately with today’s high performance measurement equipment there is no way to measure this parameter for jitter performance in the class demonstrated by the MPC950/951 result different methods are used which approximate cycle–to–cycle jitter. TIMING SOLUTIONS BR1333 — Rev 6 66.66MHz ‘ ...

Page 8

... MPC950 MPC951 switching at the same frequency the total jitter is exactly equal to the PLL jitter device, like the MPC950/951, where a number of the outputs can be switching synchronously but at different frequencies a “multi–modal” jitter distribution can be seen on the highest frequency outputs. Because the output being monitored is affected by the activity on the other outputs it is important to consider what is happening on those other outputs ...

Page 9

... DC voltage drop that will be seen between the V CC supply and the VCCA pin of the MPC950/951. From the data sheet the I VCCA current (the current sourced through the VCCA pin) is typically 15mA (20mA maximum), assuming that a minimum of 3 ...

Page 10

... To determine the crystal required to produce the desired output frequency for an application which utilizes internal feedback the block diagram of Figure 11 should be used. The P and the M values for the MPC950/951 are also included in Figure 11. The M values can be found in the configuration tables included in this applications section. MOTOROLA ...

Page 11

... MPC950/951 clock driver. For the series terminated case however there current draw, thus the outputs can drive multiple series terminated lines. Figure 12 illustrates an output driving a single series terminated line vs two series terminated lines in parallel. When taken to its extreme the fanout of the MPC950/951 clock driver is effectively doubled due to its capability to drive multiple lines ...

Page 12

... MPC950 MPC951 –T– DETAIL –Z– –AB– SEATING –AC– PLANE 0.10 (0.004 DETAIL AD MOTOROLA OUTLINE DIMENSIONS FA SUFFIX TQFP PACKAGE CASE 873A–02 ISSUE A 4X 0.20 (0.008) AB T–U Z –U– ...

Page 13

... Mfax : RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609 INTERNET: http://www.mot.com/sps/ TIMING SOLUTIONS BR1333 — Rev 6 MPC950 MPC951 are registered trademarks of Motorola, Inc. Motorola, Inc Equal JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. ...

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