AT91M40800 ATMEL Corporation, AT91M40800 Datasheet
AT91M40800
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AT91M40800 Summary of contents
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... Thumb Processor Core Secondary SRAM Bank – 128K Bytes – – AT91 ® ARM Thumb Microcontrollers AT91M40800 AT91R40807 AT91M40807 AT91R40008 ROM – – 128K Bytes – Rev. 1354D–ATARM–08/02 ® 1 ...
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Pin Configuration Figure 1. AT91X40 Series Pinout (Top View) P22/RXD1 76 NWR1/NUB 77 GND 78 NRST 79 NWDOVF 80 VDDIO 81 MCKI 82 P23 83 P24/BMS 84 P25/MCKO 85 GND 86 GND 87 TMS 88 TDI 89 TDO 90 TCK ...
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Table 1. AT91X40 Series Pin Description Module Name Function EBI A0 - A23 Address Bus D0 - D15 Data Bus NCS0 - NCS3 Chip Select CS4 - CS7 Chip Select NWR0 Lower Byte 0 Write Signal NWR1 Upper Byte 1 ...
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Block Diagram TMS TDO TDI TCK MCKI P25/MCKO P12/FIQ P9/IRQ0 P10/IRQ1 P11/IRQ2 P P13/SCK0 I P14/TXD0 O P15/RXD0 P20/SCK1 P21/TXD1/NTRI P22/RXD1 P16 P17 P18 P19 P23 P24/BMS AT91X40 Series 4 Figure 2. AT91X40 Series Embedded ICE ARM7TDMI Core ASB ROM ...
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Architectural Overview Memories Peripherals System Peripherals 1354D–ATARM–08/02 The AT91X40 Series Microcontrollers integrate an ARM7TDMI with its embedded ICE interface, memories and peripherals. The series’ architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus ...
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User Peripherals AT91X40 Series 6 The Watchdog (WD) can be used to prevent system lock-up if the software becomes trapped in a deadlock. The Special Function (SF) module integrates the Chip ID, the Reset Status and the Pro- tect registers. ...
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... Mechanical characteristics Ordering information Timings DC characteristics AT91X40 Series Document Title ARM7TDMI (Thumb) Datasheet AT91M40800 Summary Datasheet AT91M40800 Electrical Characteristics ARM7TDMI (Thumb) Datasheet AT91R40807 Summary Datasheet AT91R40807 Electrical Characteristics ARM7TDMI (Thumb) Datasheet AT91M40807 Summary Datasheet AT91M40807 Electrical Characteristics ARM7TDMI (Thumb) Datasheet AT91R40008 Summary Datasheet ...
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... The AT91M40800 Microcontroller I/O pads are 5V-tolerant, enabling it to interface with external 5V devices without any additional components. 5V-tolerant means that the AT91M40800 accepts 5V (3V) on the inputs even powered at 3V (2V). Refer to the AT91M40800 Electrical Characteristics datasheet for further details. After the reset, the peripheral I/Os are initialized as inputs to provide the user with maxi- mum flexibility ...
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JTAG/ICE Debug Memory Controller Internal Memories Using Internal Memories 1354D–ATARM–08/02 To enter tri-state mode, the pin NTRI must be held low during the last 10 clock cycles before the rising edge of NRST. For normal operation, the pin NTRI must ...
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... SRAM. Then, the NRST must be reasserted by external circuitry after the level on the pin BMS is changed. The pin BMS is multiplexed with the I/O line P24 that can be programmed after reset like any standard PIO line. Table 3. Boot Mode Select BMS Product AT91M40800 AT91R40807 1 AT91M40807 AT91R40008 0 All The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt, Fast Interrupt) are mapped from address 0x0 to address 0x20 ...
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External Bus Interface Peripherals Peripheral Registers 1354D–ATARM–08/02 No abort is generated when reading the internal memory or by accessing the internal peripheral, whether the address is defined or not. When a write-protected area is accessed, the memory controller detects it ...
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Peripheral Interrupt Control Peripheral Data Controller System Peripherals PS: Power-saving AIC: Advanced Interrupt Controller PIO: Parallel IO Controller WD: Watchdog AT91X40 Series 12 The Interrupt Control of each peripheral is controlled from the status register using the interrupt mask. The ...
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SF: Special Function 1354D–ATARM–08/02 The AT91X40 Series provides registers that implement the following special functions. • Chip identification • RESET status • Protect Mode • Write protection for the AT91R40807 internal 128-Kbyte memory AT91X40 Series 13 ...
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User Peripherals USART: Universal Synchronous/ Asynchronous Receiver Transmitter TC: Timer Counter AT91X40 Series 14 The AT91X40 Series provides two identical, full-duplex, universal synchronous/asyn- chronous receiver/transmitters. Each USART has its own baud rate generator, and two dedicated Peripheral Data Con- troller ...
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... Memory Map Figure 3. AT91M40800/R40008 Memory Map Before and After the Remap Command Before Address Function Size 0xFFFFFFFF On-chip 4M Bytes Peripherals 0xFFC00000 0xFFBFFFFF Reserved 0x00400000 0x003FFFFF On-chip 1M Byte Primary RAM Bank 0x00300000 0x002FFFFF Reserved 1M Byte On-chip Device 0x00200000 0x001FFFFF Reserved 1M Byte On-chip ...
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Figure 4. AT91R40807/M40807 Before and After the Remap Command Before Address Function Size 0xFFFFFFFF On-chip 4M Bytes Peripherals 0xFFC00000 0xFFBFFFFF Reserved 0x00400000 0x003FFFFF On-chip 1M Byte Primary RAM Bank 0x00300000 0x002FFFFF Reserved 1M Byte On-chip Device 0x00200000 0x001FFFFF On-chip ROM ...
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Peripheral Memory Map 1354D–ATARM–08/02 Figure 5. Peripheral Memory Map Address Peripheral 0xFFFFFFFF AIC 0xFFFFF000 0xFFFFBFFF WD 0xFFFF8000 0xFFFF7FFF PS 0xFFFF4000 0xFFFF3FFF PIO 0xFFFF0000 0xFFFE3FFF TC 0xFFFE0000 0xFFFD3FFF USART0 0xFFFD0000 0xFFFCFFFF USART1 0xFFFCC000 0xFFF03FFF SF 0xFFF00000 0xFFE03FFF EBI 0xFFE00000 0xFFC00000 AT91X40 ...
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EBI: External Bus Interface External Memory Mapping AT91X40 Series 18 The EBI generates the signals that control the access to the external memory or periph- eral devices. The EBI is fully-programmable and can address up to 64M bytes. It has ...
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Figure 6. External Memory Smaller than Page Size 1M Byte Device 1M Byte Device Memory Map 1M Byte Device 1M Byte Device AT91X40 Series Base + 4M Bytes Hi Repeat 3 Low Base + 3M Bytes Hi Repeat 2 ...
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External Bus Interface Pin Description Name A0 - A23 D0 - D15 NCS0 - NCS3 CS4 - CS7 NRD NWR0 - NWR1 NOE NWE NUB, NLB NWAIT The following table shows how certain EBI signals are multiplexed: Table 4. EBI ...
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Chip Select Lines 1354D–ATARM–08/02 The EBI provides up to eight chip select lines: • Chip select lines NCS0 - NCS3 are dedicated to the EBI (not multiplexed). • Chip select lines CS4 - CS7 are multiplexed with the top four ...
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Figure 8. Memory Connections for Eight External Devices CS4 - CS7 NCS0 - NCS3 NRD EBI NWRx A0 - A19 D0 - D15 Note: For eight external devices, the maximum address space per device is 1M byte. AT91X40 Series 22 ...
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Data Bus Width 1354D–ATARM–08/02 A data bus width bits can be selected for each chip select. This option is con- trolled by the DBW field in the EBI_CSR (Chip Select Register) for the corresponding chip select. ...
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Byte Write or Byte Select Access AT91X40 Series 24 Each chip select with a 16-bit data bus can operate with one of two different types of write access: • Byte Write Access supports two byte write and a single read ...
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Byte Select Access is used to connect 16-bit devices in a memory page. • The signal A0/NLB is used as NLB and enables the lower byte for both read and write operations. • The signal NWR1/NUB is used as ...
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Boot on NCS0 AT91X40 Series 26 Depending on the device and the BMS pin level during the reset, the user can select either an 8-bit or 16-bit external memory device connected on NCS0 as the Boot Mem- ory. In this ...
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Read Protocols Standard Read Protocol Early Read Protocol Early Read Wait State 1354D–ATARM–08/02 The EBI provides two alternative protocols for external memory read access: standard and early read. The difference between the two protocols lies in the timing of the ...
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Write Data Hold Time AT91X40 Series 28 Figure 15. Early Read Protocol MCKI ADDR NCS NRD or NWE Figure 16. Early Read Wait State Write Cycle MCKI ADDR NCS NRD NWE During write cycles in both protocols, output data becomes ...
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Wait States Standard Wait States 1354D–ATARM–08/02 Figure 17. Data Hold Time MCK ADDR NWE Data Output In early read protocol the data can remain valid longer than in standard read protocol due to the additional wait cycle which follows a ...
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Data Float Wait State AT91X40 Series 30 Figure 18. One Wait State Access MCK ADDR NCS NWE NRD (1) Notes: 1. Early Read Protocol 2. Standard Read Protocol Some memory devices are slow to release the external bus. For such ...
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External Wait 1354D–ATARM–08/02 Figure 19. Data Float Output Time MCK ADDR NCS NRD ( D15 Notes: 1. Early Read Protocol 2. Standard Read Protocol The NWAIT input can be used to add wait states at any time. NWAIT ...
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Chip Select Change Wait States AT91X40 Series 32 Additional constraints are applicable to the AT91R40807, the AT91M40807 and the AT91 40800. The behavior of the EBI is correct when NWAIT is asserted during an external memory access: • When NWAIT ...
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Memory Access Waveforms 1354D–ATARM–08/02 Figures 22 through 25 show examples of the two alternative protocols for external mem- ory read access. Figure 22. Standard Read Protocol without t AT91X40 Series DF 33 ...
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AT91X40 Series 34 Figure 23. Early Read Protocol Without t DF 1354D–ATARM–08/02 ...
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Figure 24. Standard Read Protocol with t AT91X40 Series DF 35 ...
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AT91X40 Series 36 Figure 25. Early Read Protocol With t DF 1354D–ATARM–08/02 ...
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Figures 26 through 32 show the timing cycles and wait states for read and write access to the various AT91X40 Series external memory devices. The configurations described are shown in the following table: Table 5. Memory Access Waveforms Figure ...
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Figure 26. 0 Wait States, 16-bit Bus Width, Word Transfer MCK A1 - A23 NCS NLB NUB READ ACCESS · Standard Protocol NRD D0 - D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS · Byte Write/ ...
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Figure 27. 1 Wait, 16-bit Bus Width, Word Transfer MCK A1 - A23 NCS NLB NUB READ ACCESS · Standard Protocol NRD D0 - D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS · Byte Write/ Byte ...
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Figure 28. 1 Wait State, 16-bit Bus Width, Half-word Transfer MCK A1 - A23 NCS NLB NUB READ ACCESS · Standard Protocol NRD D0 - D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS · Byte Write/ ...
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Figure 29. 0 Wait States, 8-bit Bus Width, Word Transfer MCK A0 - A23 NCS READ ACCESS · Standard Protocol NRD D0-D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS NWR0 NWR1 D0 - D15 1354D–ATARM–08/02 ADDR ...
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Figure 30. 1 Wait State, 8-bit Bus Width, Half-word Transfer 1 Wait State MCK A0 - A23 NCS READ ACCESS · Standard Protocol NRD D0 - D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS NWR0 NWR1 ...
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Figure 31. 1 Wait State, 8-bit Bus Width, Byte Transfer MCK A0 - A23 NCS READ ACCESS · Standard Protocol NRD D0 - D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS NWR0 NWR1 D0 - D15 ...
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Figure 32. 0 Wait States, 16-bit Bus Width, Byte Transfer MCK A1 - A23 Internal Address NCS NLB NUB READ ACCESS · Standard Protocol NRD D0 - D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS · ...
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EBI User Interface 1354D–ATARM–08/02 The EBI is programmed using the registers listed in the table below. The Remap Control Register (EBI_RCR) controls exit from Boot Mode (See “Boot on NCS0” on page 26.) The Memory Control Register (EBI_MCR) is used ...
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EBI Chip Select Register Register Name: EBI_CSR0 - EBI_CSR7 Access Type: Read/Write Reset Value: See Table 6 Absolute Address:0xFFE00000 - 0xFFE0001C Offset: 0x00 - 0x1C – – PAGES – • DBW: ...
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PAGES: Page Size PAGES Page Size Byte Bytes 1 0 16M Bytes 1 1 64M Bytes • TDF: Data Float Output Time TDF Number of Cycles Added after the Transfer ...
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EBI Remap Control Register Register Name: EBI_RCR Access Type: Write Only Absolute Address:0xFFE00020 Offset: 0x20 31 30 – – – – – – – – • RCB: Remap Command Bit (Code Label EBI_RCB) 0 ...
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EBI Memory Control Register Register Name: EBI_MCR Access Type: Read/Write Reset Value: 0 Absolute Address:0xFFE00024 Offset: 0x24 31 30 – – – – – – – – • ALE: Address Line Enable This field ...
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PS: Power-saving Peripheral Clocks AT91X40 Series 50 The AT91X40 Series’ Power-saving feature enables optimization of power consumption. The PS controls the CPU and Peripheral Clocks. One control register (PS_CR) enables the user to stop the ARM7TDMI Clock and enter Idle ...
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PS User Interface Base Address: 0xFFFF4000 (Code Label PS_BASE) Table 7. PS Memory Map Offset Register 0x00 Control Register 0x04 Peripheral Clock Enable Register 0x08 Peripheral Clock Disable Register 0x0C Peripheral Clock Status Register 1354D–ATARM–08/02 AT91X40 Series Name Access PS_CR ...
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PS Control Register Name: PS_CR Access: Write Only Offset: 0x00 31 30 – – – – – – – – • CPU: CPU Clock Disable effect Disables the CPU ...
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PS Peripheral Clock Enable Register Name: PS_PCER Access: Write Only Offset: 0x04 31 30 – – – – – – – TC2 • US0: USART 0 Clock Enable effect ...
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PS Peripheral Clock Disable Register Name: PS_PCDR Access: Write Only Offset: 0x08 31 30 – – – – – – – TC2 • US0: USART 0 Clock Disable effect ...
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PS Peripheral Clock Status Register Name: PS_PCSR Access: Read Only Reset Value: 0x17C Offset: 0x0C 31 30 – – – – – – – TC2 • US0: USART 0 Clock Status 0 = USART ...
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AIC: Advanced Interrupt Controller Figure 33. Interrupt Controller Block Diagram FIQ Source Advanced Peripheral Bus (APB) Internal Interrupt Sources External Interrupt Sources Note: After a hardware reset, the AIC pins are controlled by the PIO Controller. They must be configured ...
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Table 8. AIC Interrupt Sources (1) Interrupt Source Interrupt Name ...
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Hardware Interrupt Vectoring Priority Controller Interrupt Handling Interrupt Masking AT91X40 Series 58 The hardware interrupt vectoring reduces the number of instructions to reach the inter- rupt handler to only one. By storing the following instruction at address 0x00000018, the processor ...
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Interrupt Clearing and Setting Fast Interrupt Request Software Interrupt Spurious Interrupt 1354D–ATARM–08/02 All interrupt sources which are programmed to be edge triggered (including FIQ) can be individually set or cleared by respectively writing to the registers AIC_ISCR and AIC_ICCR. This ...
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Protect Mode Action Calculate active interrupt (higher than current or spurious) Determine and return the vector of the active interrupt Memorize interrupt Push on internal stack the current priority level (1) Acknowledge the interrupt (2) No effect AT91X40 Series 60 ...
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AIC User Interface • Base Address: 0xFFFFF000 (Code Label AIC_BASE) Table 9. AIC Memory Map Offset Register 0x000 Source Mode Register 0 0x004 Source Mode Register 1 – – 0x07C Source Mode Register 31 0x080 Source Vector Register 0 0x084 ...
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AIC Source Mode Register Register Name: AIC_SMR0 - AIC_SMR31 Access Type: Read/Write Reset Value: 0 Offset: 0x000 - 0x07C 31 30 – – – – – – – SRCTYPE • PRIOR: Priority Level (Code ...
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AIC Source Vector Register Register Name: AIC_SVR0 - AIC_SVR31 Access Type: Read/Write Reset Value: 0 Offset: 0x080 - 0x0FC • VECTOR: Interrupt Handler Address The user may store in these registers the ...
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AIC Interrupt Vector Register Register Name: AIC_IVR Access Type: Read Only Reset Value: 0 Offset: 0x100 • IRQV: Interrupt Vector Register The IRQ Vector Register contains the vector programmed by the user ...
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AIC Interrupt Status Register Register Name: AIC_ISR Access Type: Read Only Reset Value: 0 Offset: 0x108 31 30 – – – – – – – – • IRQID: Current IRQ Identifier (Code Label AIC_IRQID) ...
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AIC Interrupt Mask Register Register Name: AIC_IMR Access Type: Read Only Reset Value: 0 Offset: 0x110 31 30 – – – – – – WDIRQ TC2IRQ • Interrupt Mask 0 = Corresponding interrupt is ...
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AIC Core Interrupt Status Register Register Name: AIC_CISR Access Type: Read Only Reset Value: 0 Offset: 0x114 31 30 – – – – – – – – • NFIQ: NFIQ Status (Code Label AIC_NFIQ) ...
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AIC Interrupt Enable Command Register Register Name: AIC_IECR Access Type: Write Only Offset: 0x120 31 30 – – – – – – WDIRQ TC2IRQ • Interrupt Enable effect Enables ...
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AIC Interrupt Clear Command Register Register Name: AIC_ICCR Access Type: Write Only Offset: 0x128 31 30 – – – – – – WDIRQ TC2IRQ • Interrupt Clear effect Clears ...
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AIC End of Interrupt Command Register Register Name: AIC_EOICR Access Type: Write Only Offset: 0x130 31 30 – – – – – – – – The End of Interrupt Command Register is used by ...
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Standard Interrupt Sequence 1354D–ATARM–08/ assumed that: • The Advanced Interrupt Controller has been programmed, AIC_SVR are loaded with corresponding interrupt service routine addresses and interrupts are enabled. • The Instruction at address 0x18(IRQ exception vector address) is ldr ...
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AT91X40 Series 72 SPSR, masking or unmasking the interrupts depending on the state saved in the SPSR (the previous state of the ARM core). Note: The I bit in the SPSR is significant set, it indicates that ...
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Fast Interrupt Sequence It is assumed that: • The Advanced Interrupt Controller has been programmed, AIC_SVR[0] is loaded with fast interrupt service routine address and the fast interrupt is enabled. • The Instruction at address 0x1C(FIQ exception vector address) ...
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... In all cases, the level on the pin can be read in the register PIO_PDSR (Pin Data Status). Optional input glitch filtering is available on each pin of the AT91M40800, the AT91M40807 and the AT91R40807. Filtering is controlled by the registers PIO_IFER (Input Filter Enable) and PIO_IFDR (Input Filter Disable). The input glitch filtering can be selected whether the pin is used for its peripheral function parallel I/O line ...
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Interrupts User Interface 1354D–ATARM–08/02 Each parallel I/O can be programmed to generate an interrupt when a level change occurs. This is controlled by the PIO_IER (Interrupt Enable) and PIO_IDR (Interrupt Dis- able) registers which enable/disable the I/O interrupt by setting/clearing ...
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Figure 34. Parallel I/O Multiplexed with a Bi-directional Signal Pad Output Enable Pad Output Pad Pad Input AT91X40 Series 76 Filter PIO_IFSR Event Detection Note: The filter is not implemented in the AT91R40008. PIO_OSR 1 0 PIO_PSR PIO_ODSR ...
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Table 10. Multiplexed Parallel I/Os PIO Controller Bit (1) Number Port Name Port Name 0 P0 TCLK0 1 P1 TIOA0 2 P2 TIOB0 3 P3 TCLK1 4 P4 TIOA1 5 P5 TIOB1 6 P6 TCLK2 7 P7 TIOA2 8 P8 ...
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PIO User Interface PIO Base Address: 0xFFFF0000 (Code Label PIO_BASE) Table 11. PIO Controller Memory Map Offset Register 0x00 PIO Enable Register 0x04 PIO Disable Register 0x08 PIO Status Register 0x0C Reserved 0x10 Output Enable Register 0x14 Output Disable Register ...
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PIO Enable Register Register Name: PIO_PER Access Type: Write Only Offset: 0x00 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 This register is used to enable individual pins to be controlled by ...
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PIO Status Register Register Name: PIO_PSR Access Type: Read Only Reset Value: 0x01FFFFFF Offset: 0x08 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 This register indicates which pins are enabled for PIO ...
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PIO Output Enable Register Register Name: PIO_OER Access Type: Write Only Offset: 0x10 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 This register is used to enable PIO output drivers. If the ...
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PIO Output Status Register Register Name: PIO_OSR Access Type: Read Only Reset Value: 0 Offset: 0x18 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 This register shows the PIO pin control (output ...
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PIO Input Filter Enable Register Register Name: PIO_IFER Access Type: Write Only Offset: 0x20 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 This register is used to enable input glitch filters. It ...
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PIO Input Filter Status Register Register Name: PIO_IFSR Access Type: Read Only Reset Value: 0 Offset: 0x28 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 This register indicates which pins have glitch ...
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PIO Set Output Data Register Register Name: PIO_SODR Access Type: Write Only Offset: 0x30 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 This register is used to set PIO output data. It ...
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PIO Output Data Status Register Register Name: PIO_ODSR Access Type: Read Only Reset Value: 0 Offset: 0x38 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 This register shows the output data status ...
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PIO Interrupt Enable Register Register Name: PIO_IER Access Type: Write Only Offset: 0x40 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 This register is used to enable PIO interrupts on the corresponding ...
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PIO Interrupt Mask Register Register Name: PIO_IMR Access Type: Read Only Reset Value: 0 Offset: 0x48 31 30 P31 P30 23 22 P23 P22 15 14 P15 P14 This register shows which pins have interrupts enabled. ...
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WD: Watchdog Timer Advanced Peripheral Bus (APB) WD_RESET WDIRQ MCKI/8 MCKI/32 MCKI/128 MCKI/1024 1354D–ATARM–08/02 The AT91X40 Series has an internal watchdog timer which can be used to prevent sys- tem lock-up if the software becomes trapped in a deadlock. In ...
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WD User Interface WD Base Address: 0xFFFF8000 (Code Label WD_BASE) Table 12. WD Memory Map Offset Register 0x00 Overflow Mode Register 0x04 Clock Mode Register 0x08 Control Register 0x0C Status Register WD Overflow Mode Register Name: WD_OMR Access: Read/Write Reset ...
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WD Clock Mode Register Name: WD_CMR Access: Read/Write Reset Value: 0 Offset: 0x04 31 30 – – – – – CKEY • WDCLKS: Clock Selection WDCLKS Clock Selected 0 0 MCK MCK/32 ...
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WD Control Register Name: WD_CR Access: Write Only Offset: 0x08 31 30 – – – – • RSTKEY: Restart Key (Code Label WD_RSTKEY) 0xC071 = Watch Dog counter is restarted. Other value = No ...
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WD Enabling Sequence 1354D–ATARM–08/02 To enable the Watchdog Timer the sequence is as follows: 1. Disable the Watchdog by clearing the bit WDEN: Write 0x2340 to WD_OMR This step is unnecessary if the WD is already disabled (reset state). 2. ...
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... SF: Special Function Registers Chip Identification Table 13 provides the Chip ID values for the products described in this datasheet. Table 13. Chip ID Values Product AT91M40800 AT91R40807 AT91M40807 AT91R40008 SF User Interface Chip ID Base Address = 0xFFF00000 (Code Label SF_BASE) Table 14. SF Memory Map Offset Register 0x00 Chip ID Register ...
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Chip ID Register Register Name: SF_CIDR Access Type: Read Only Reset Value: Hardwired Offset: 0x00 31 30 EXT 23 22 ARCH 15 14 NVDSIZ • VERSION: Version of the chip (Code Label SF_VERSION) This value is ...
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VDSIZ: Volatile Data Memory Size VDSIZ Others • ARCH: Chip Architecture (Code Label SF_ARCH) Code of Architecture: Two BCD digits. 0100 0000 • NVPTYP: ...
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Reset Status Register Register Name: SF_RSR Access Type: Read Only Reset Value: See Below Offset: 0x08 31 30 – – – – – – • RESET: Reset Status Information This field indicates whether the ...
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SF Memory Mode Register This register only applies to the AT91R40807. Register Name: SF_MMR Access Type: Read/Write Reset Value: 0 Offset: 0x0C 31 30 – – – – – – – – • RAMWU: ...
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USART: Universal Synchronous/ Asynchronous Receiver/ Transmitter Figure 36. USART Block Diagram ASB AMBA APB USxIRQ MCK MCK/8 Pin Description Each USART channel has the following external signals: Name Description USART Serial clock can be configured as input or output: SCK ...
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Baud Rate Generator Figure 37. Baud Rate Generator USCLKS [0] USCLKS [1] MCK MCK/8 1 SCK AT91X40 Series 100 The Baud Rate Generator provides the bit period clock (the Baud Rate clock) to both the Receiver and ...
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Receiver Asynchronous Receiver Figure 38. Asynchronous Mode: Start Bit Detection 16 x Baud Rate Clock RXD Sampling Figure 39. Asynchronous Mode: Character Reception Example: 8-bit, parity enabled 1 stop 0.5 bit periods RXD Sampling True Start Detection 1354D–ATARM–08/02 The USART ...
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Synchronous Receiver Receiver Ready Parity Error Framing Error Time-out AT91X40 Series 102 When configured for synchronous operation (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate clock low level is ...
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Transmitter Time-guard Multi-drop Mode 1354D–ATARM–08/02 The transmitter has the same behavior in both synchronous and asynchronous operat- ing modes. Start bit, data bits, parity bit and stop bits are serially shifted, lowest significant bit first, on the falling edge of ...
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Break Transmit Break AT91X40 Series 104 A break condition is a low signal level which has a duration of at least one character (including start/stop bits and parity). The transmitter generates a break condition on the TXD line when STTBRK ...
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Receive Break Peripheral Data Controller Interrupt Generation Channel Modes 1354D–ATARM–08/02 Each of these steps can be scheduled by using the interrupt if the bit TXRDY in US_IMR is set. For character transmission, the USART channel must be enabled before sending ...
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AT91X40 Series 106 Figure 42. Channel Modes Automatic Echo Receiver Transmitter Local Loopback Receiver Transmitter Remote Loopback Receiver Transmitter RXD Disabled TXD Disabled RXD V DD Disabled TXD V DD Disabled RXD Disabled TXD 1354D–ATARM–08/02 ...
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USART User Interface Base Address USART0: 0xFFFD0000 (Code Label USART0_BASE) Base Address USART1: 0xFFFCC000 (Code Label USART1_BASE) Table 15. USART Memory Map Offset Register 0x00 Control Register 0x04 Mode Register 0x08 Interrupt Enable Register 0x0C Interrupt Disable Register 0x10 Interrupt ...
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USART Control Register Name: US_CR Access Type:Write Only Offset: 0x00 31 30 – – – – – – TXDIS TXEN • RSTRX: Reset Receiver (Code Label US_RSTRX effect The ...
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STTTO: Start Time-out (Code Label US_STTTO effect Start waiting for a character before clocking the time-out counter. • SENDA: Send Address (Code Label US_SENDA effect Multi-drop Mode only, ...
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USART Mode Register Name: US_MR Access Type:Read/Write Reset Value: 0 Offset: 0x04 31 30 – – – – CHMODE 7 6 CHRL • USCLKS: Clock Selection (Baud Rate Generator Input Clock) USCLKS ...
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PAR: Parity Type PAR Parity Type Even Parity Odd Parity Parity forced to 0 (Space Parity forced to 1 (Mark parity 1 1 ...
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USART Interrupt Enable Register Name: US_IER Access Type:Write Only Offset: 0x08 31 30 – – – – – – PARE FRAME • RXRDY: Enable RXRDY Interrupt (Code Label US_RXRDY effect. 1 ...
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USART Interrupt Disable Register Name: US_IDR Access Type:Write Only Offset: 0x0C 31 30 – – – – – – PARE FRAME • RXRDY: Disable RXRDY Interrupt (Code Label US_RXRDY effect. 1 ...
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USART Interrupt Mask Register Name: US_IMR Access Type:Read Only Reset Value: 0 Offset: 0x10 31 30 – – – – – – PARE FRAME • RXRDY: Mask RXRDY Interrupt (Code Label US_RXRDY ...
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USART Channel Status Register Name: US_CSR Access Type:Read Only Reset Value: 0x18 Offset: 0x14 31 30 – – – – – – PARE FRAME • RXRDY: Receiver Ready (Code Label US_RXRDY ...
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PARE: Parity Error (Code Label US_PARE least one parity bit has been detected false (or a parity bit high in Multi-drop Mode) since the last “Reset Status Bits” command parity bit has been ...
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USART Receiver Holding Register Name: US_RHR Access Type:Read Only Reset Value: 0 Offset: 0x18 31 30 – – – – – – • RXCHR: Received Character Last character received if RXRDY is set. When ...
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USART Baud Rate Generator Register Name: US_BRGR Access Type:Read/Write Reset Value: 0 Offset: 0x20 31 30 – – – – • CD: Clock Divisor This register has no effect if Synchronous Mode is selected ...
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USART Receiver Time-out Register Name: US_RTOR Access Type:Read/Write Reset Value: 0 Offset: 0x24 31 30 – – – – – – • TO: Time-out Value When a value is written to this register, a ...
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USART Receive Pointer Register Name: US_RPR Access Type:Read/Write Reset Value: 0 Offset: 0x30 • RXPTR: Receive Pointer RXPTR must be loaded with the address of the receive buffer. USART Receive Counter Register ...
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USART Transmit Pointer Register Name: US_TPR Access Type:Read/Write Reset Value: 0 Offset: 0x38 • TXPTR: Transmit Pointer TXPTR must be loaded with the address of the transmit buffer. USART Transmit Counter Register ...
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TC: Timer Counter Figure 43. TC Block Diagram MCK/2 TCLK0 MCK/8 TIOA1 TIOA2 MCK/32 TCLK1 TCLK2 MCK/128 MCK/1024 TCLK0 TCLK1 TIOA0 TIOA2 TCLK2 TCLK0 TCLK1 TCLK2 TIOA0 TIOA1 Timer Counter Block AT91X40 Series 122 The AT91X40 Series features a Timer ...
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Signal Name Description Channel Signal XC0, XC1, XC2 TIOA TIOB INT SYNC Block Signals TCLK0, TCLK1, TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 Note: After a hardware reset, the Timer Counter block pins are controlled by the PIO Controller. They ...
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Clock Control AT91X40 Series 124 The selected clock can be inverted with the CLKI bit in TC_CMR (Channel Mode). This allows counting on the opposite edges of the clock. The burst function allows the clock to be validated when an ...
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Timer Counter Operating Modes Trigger 1354D–ATARM–08/02 Figure 45. Clock Control Selected Clock Counter Clock Each Timer Counter channel can independently operate in two different modes: • Capture Mode allows measurement on signals • Waveform Mode allows wave ...
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Capture Operating Mode Capture Registers A and B (RA and RB) Trigger Conditions Status Register AT91X40 Series 126 This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register). Capture Mode allows the TC Channel to perform ...
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Figure 46. Capture Mode 1354D–ATARM–08/02 AT91X40 Series CPCS LOVRS COVFS LDRBS LDRAS ETRGS TC_IMR TC_SR 127 ...
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Waveform Operating Mode Compare Register A, B and C (RA, RB, and RC) AT91X40 Series 128 This mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). Waveform Operating Mode allows the TC Channel to generate 1 ...
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Output Controller Status 1354D–ATARM–08/02 The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA ...
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Figure 47. Waveform Mode Controller AT91X40 Series 130 Output Controller Output CPCS CPBS CPAS COVFS ETRGS TC_IMR TC_SR 1354D–ATARM–08/02 ...
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TC User Interface TC Base Address: 0xFFFE0000 (Code Label TC_BASE) Table 16. TC Global Memory Map Offset Channel/Register 0x00 TC Channel 0 0x40 TC Channel 1 0x80 TC Channel 2 0xC0 TC Block Control Register 0xC4 TC Block Mode Register ...
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TC Block Control Register Register Name: TC_BCR Access Type: Write only Offset: 0xC0 31 30 – – – – – – – – • SYNC: Synchro Command effect Asserts ...
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TC Block Mode Register Register Name: TC_BMR Access Type: Read/Write Reset Value: 0 Offset: 0xC4 31 30 – – – – – – – – • TC0XC0S: External Clock Signal 0 Selection TC0XC0S 0 ...
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TC Channel Control Register Register Name: TC_CCR Access Type: Write only Offset: 0x00 31 30 – – – – – – – – • CLKEN: Counter Clock Enable Command (Code Label TC_CLKEN ...
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TC Channel Mode Register: Capture Mode Register Name: TC_CMR Access Type: Read/Write Reset Value: 0 Offset: 0x04 31 30 – – – – WAVE = 0 CPCTRG 7 6 LDBDIS LDBSTOP • TCCLKS: Clock Selection TCCLKS ...
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LDBDIS: Counter Clock Disable with RB Loading (Code Label TC_LDBDIS Counter clock is not disabled when RB loading occurs Counter clock is disabled when RB loading occurs. • ETRGEDG: External Trigger Edge Selection ETRGEDG Edge ...
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TC Channel Mode Register: Waveform Mode Register Name: TC_CMR Access Type: Read/Write Reset Value: 0 Offset: 0x04 31 30 BSWTRG 23 22 ASWTRG 15 14 WAVE = 1 CPCTRG 7 6 CPCDIS CPCSTOP • TCCLKS: Clock Selection TCCLKS Clock Selected ...
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CPCDIS: Counter Clock Disable with RC Compare (Code Label TC_CPCDIS Counter clock is not disabled when counter reaches RC Counter clock is disabled when counter reaches RC. • EEVTEDG: External Event Edge Selection EEVTEDG Edge ...
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ACPC: RC Compare Effect on TIOA ACPC Effect 0 0 None 0 1 Set 1 0 Clear 1 1 Toggle • AEEVT: External Event Effect on TIOA AEEVT Effect 0 0 None 0 1 Set 1 0 Clear 1 ...
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BEEVT: External Event Effect on TIOB BEEVT Effect 0 0 None 0 1 Set 1 0 Clear 1 1 Toggle • BSWTRG: Software Trigger Effect on TIOB BSWTRG Effect 0 0 None 0 1 Set 1 0 Clear 1 ...
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TC Counter Value Register Register Name: TC_CVR Access Type: Read Only Reset Value: 0 Offset: 0x10 31 30 – – – – • CV: Counter Value (Code Label TC_CV) CV contains the counter value ...
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TC Register B Register Name: TC_RB Access Type: Read Only if WAVE = 0, Read/Write if WAVE = 1 Reset Value: 0 Offset: 0x18 31 30 – – – – • RB: Register B ...
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TC Status Register Register Name: TC_SR Access Type: Read Only Reset Value: 0 Offset: 0x20 31 30 – – – – – – ETRGS LDRBS • COVFS: Counter Overflow Status (Code Label TC_COVFS) 0 ...
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MTIOA: TIOA Mirror (Code Label TC_MTIOA TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low TIOA is high. If ...
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TC Interrupt Enable Register Register Name: TC_IER Access Type: Write only Offset: 0x24 31 30 – – – – – – ETRGS LDRBS • COVFS: Counter Overflow (Code Label TC_COVFS effect. ...
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TC Interrupt Disable Register Register Name: TC_IDR Access Type: Write only Offset: 0x28 31 30 – – – – – – ETRGS LDRBS • COVFS: Counter Overflow (Code Label TC_COVFS effect. ...
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TC Interrupt Mask Register Register Name: TC_IMR Access Type: Read Only Reset Value: 0 Offset: 0x2C 31 30 – – – – – – ETRGS LDRBS • COVFS: Counter Overflow (Code Label TC_COVFS) 0 ...
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AT91X40 Series 148 1354D–ATARM–08/02 ...
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Table of Contents 1354D–ATARM–08/02 Features................................................................................................. 1 Description ............................................................................................ 1 Pin Configuration.................................................................................. 2 Block Diagram....................................................................................... 4 Architectural Overview......................................................................... 5 Memories .............................................................................................................. 5 Peripherals............................................................................................................ 5 Associated Documentation ................................................................. 7 Product Overview ................................................................................. 8 Power Supply........................................................................................................ 8 Input/Output Considerations ................................................................................. 8 Master Clock......................................................................................................... ...
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AT91X40 Series ii PS: Power-saving ............................................................................... 50 Peripheral Clocks................................................................................................ 50 PS User Interface ............................................................................................... 51 PS Control Register ............................................................................................ 52 PS Peripheral Clock Enable Register ................................................................. 53 PS Peripheral Clock Disable Register ................................................................ 54 PS Peripheral Clock Status Register .................................................................. ...
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PIO Output Enable Register ............................................................................... 81 PIO Output Disable Register .............................................................................. 81 PIO Output Status Register ................................................................................ 82 PIO Input Filter Enable Register ......................................................................... 83 PIO Input Filter Disable Register ........................................................................ 83 PIO Input Filter Status Register .......................................................................... 84 ...
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AT91X40 Series iv USART Interrupt Disable Register.................................................................... 113 USART Interrupt Mask Register ....................................................................... 114 USART Channel Status Register...................................................................... 115 USART Receiver Holding Register................................................................... 117 USART Transmitter Holding Register............................................................... 117 USART Baud Rate Generator Register ............................................................ 118 USART Receiver Time-out Register................................................................. ...
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... Fax: (81) 3-3523-7581 Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...