AD9483KS-140 Analog Devices, AD9483KS-140 Datasheet
AD9483KS-140
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AD9483KS-140 Summary of contents
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... The user may select dual channel or single channel digital outputs. The Dual Channel (demultiplexed) REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use ...
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... ILD Common-Mode Input (V ) ICM HIGH Level Current ( LOW Level Current ( VREF IN Input Resistance ( +3.3 V, external reference, ENCODE = maximum conversion rate CC DD differential PECL) Test AD9483KS-140 Temperature Level Min Typ 8 + 0.8 Full VI + 0.9 Full VI Full VI Guaranteed + ...
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... Measured under the following conditions: analog input is –1 dBFS at 19.7 MHz. 5 SNR/harmonics based on an analog input voltage of –1.0 dBFS referenced to a 1.024 V full-scale input range. Typical thermal impedance for the S-100 (MQFP) 100-lead package: Specifications subject to change without notice. REV. A Test AD9483KS-140 Temperature Level Min Typ Full IV 2 ...
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... V – Parameter is a typical value only. VI – 100% production tested at +25 C; guaranteed by design and characterization testing. Model AD9483KS-100 AD9483KS-140 AD9483/PCB CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. ...
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Pin Number Name 10, 20, 30, 40, 50, 60, 70, 73, 77, 78, 80, 81, 95, 96, 100 GND 2 ENCODE ENCODE DCO DCO 9 11, 21, 31, 41, 51, 61, ...
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AD9483 GND ENCODE ENCODE DS DS GND GND DCO DCO GND ...
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TIMING SAMPLE N SAMPLE N–1 AIN ENCODE ENCODE D7–D0 DATA N–5 CLOCK OUT CLOCK OUT SAMPLE N–1 AIN SAMPLE N– ENCODE ENCODE t HDS t SDS DS DS PORT A DATA N–7 D7–D0 OR N–8 PORT ...
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AD9483 EQUIVALENT CIRCUITS AIN AD9483 Figure 3. Equivalent Analog Input Circuit V CC VREF IN 500 2k AD9483 Figure 4. Equivalent Reference Input Circuit AD9483 300 ENCODE DS Figure 5. Equivalent Encode and Data Select Input Circuit AD9483 DEMUX Figure ...
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NYQUIST FREQUENCY (70MHz) –2 –2.5 –3 –3.5 –4 –4.5 – 100 150 200 250 f – MHz IN Figure 10. Frequency Response: f –70 –60 –50 –40 –30 –20 – 2.5 5 ...
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AD9483 –Typical Performance Characteristics 9 8 6.5 6 5 LOAD CAPACITANCE – pF Figure 16. Clock Output Delay vs. Capacitance ...
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MSPS S Figure 22. SNR vs –75 –70 3RD HARMONIC –65 –60 2ND HARMONIC –55 – ...
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AD9483 46 SNR f = 140 MSPS 19.3MHz 25% 28% 31% 38% 45% 52% 1.8 2 2.2 2.7 3.2 3.7 ENCODE DUTY CYCLE – % ENCODE PULSEWIDTH – ...
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... APPLICATION NOTES Theory of Operation The AD9483 combines Analog Devices’ patented MagAmp bit- per-stage architecture with flash converter technology to create a high performance, low power ADC. For ease of use the part includes an on board reference and input logic that accepts TTL, CMOS or PECL levels. ...
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AD9483 ADC Gain Control Each of the three ADC channels has independent limited gain control. The full-scale signal amplitude for a given ADC is set by the dc voltage on its VREF In pin. The equation relating the full scale ...
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Data Sync The Data Sync input, DS, is required to be driven for most applications to guarantee at which output port a given sample will appear. When DS is held high, the ADC data outputs and clock outputs do not ...
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AD9483 EVALUATION BOARD The AD9483 evaluation board offers an easy way to test the AD9483. It provides biasing for the analog input, it generates the output latch clocks for Single Mode, Dual Parallel Mode and Dual Interleaved ...
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OUTA B7 52 OUTA B7 OUTA B6 53 OUTA B6 OUTA B5 54 OUTA B5 OUTA B4 55 OUTA B4 OUTA B3 56 OUTA B3 OUTA B2 57 OUTA B2 OUTA B1 58 OUTA B1 OUTA B0 59 OUTA B0 ...
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AD9483 Figure 36. Output Latches Section –18– REV. A ...
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REV. A FSADJ IO LO SLEEP FSADJ IO LO SLEEP FSADJ IO LO SLEEP Figure 37. DACs and Clock Buffer Section –19– AD9483 ...
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AD9483 Figure 38. Digital Outputs Connectors and Terminations Section –20– REV. A ...
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Figure 39. Power Connector, Decoupling Capacitors, DC Adjust Trimpot Section REV. A –21– AD9483 ...
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AD9483 PCB LAYOUT The PCB is designed on a four layer (1 oz. Cu) board. Compo- nents and routing are on the top layer with a ground flood for additional isolation. Test and ground points were judiciously placed to facilitate ...
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REV. A Figure 40. Layer 1. Routing and Top Layer Ground Figure 41. Layer 2 Ground Plane –23– AD9483 ...
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AD9483 Figure 42. Layer 3 Split Power Planes Figure 43. Layer 4 Routing and Negative 5 V –24– REV. A ...
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... CRCW12062000F STRIP10 NOT INSTALLED STRIP5 NOT INSTALLED TB8A 95F6002 50F3583 TSTPT NOT INSTALLED SO14NB MC74LCX86D SO28WB AD9760AR MQFP-100 AD9483KS-140/100 SO20WB MC74LCX574DW SO8NB AD8055AN DIP20 NOT INSTALLED JMP-2P SEE NOTE JMP-3P SEE NOTE JMP_6 SEE NOTE –25– AD9483 VALUE SUPPLIER ...
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... PLANE 0.031 (0.78) NOTE: THE AD9483KS PACKAGE USES A COPPER INSERT TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OVER THE FULL +85 C TEMPERATURE RANGE. THIS COPPER INSERT IS EXPOSED ON THE UNDERSIDE OF THE DEVICE RECOMMENDED THAT DURING THE DESIGN OF THE PC BOARD NO THROUGHHOLES OR SIGNAL TRACES BE PLACED UNDER THE AD9483 THAT COULD COME IN CONTACT WITH THE COPPER INSERT ...