CXA3106Q Sony, CXA3106Q Datasheet
CXA3106Q
Specifications of CXA3106Q
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CXA3106Q Summary of contents
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... PLL IC for LCD Monitor/Projector Description The CXA3106Q is a PLL IC for LCD monitors/ projectors with built-in phase detector, charge pump, VCO and counter. The various internal settings are performed by serial data via a 3-line bus. Applicable LCD monitor/projector resolution are VGA, SVGA and XGA, etc. ...
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... TTLV , PECLV , IRV CC CC –0. level IOV 1 L level 2 H level 2 L level – 2 – CXA3106Q –0.5 to +7.0 –0.5 to +0.5 IOGND – 0.5 to IOV + 0.5 CC IRGND – 0.5 to IRV + 0.5 CC –30 to +30 – –65 to +150 –25 to +75 750 Min. Typ. Max. 4.75 5.00 5.25 0 0.05 – 1.1 CC IOV – ...
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... CXA3106Q ...
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... PECL PECL TTL TTL PECL PECL TTL TTL TTL TTL TTL TTL TTL TTL TTL 5V 0V TTL TTL TTL TTL TTL PECL PECL PECL PECL PECL PECL PECLV – 1. 1.3V 2.0V to 4.4V 2. – 4 – CXA3106Q ...
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... VCO circuit analog GND. VCO SUB analog GND. IREF analog GND. IREF analog power supply. Ground this pin to the ground pattern with a 0.1µF ceramic chip capacitor as close to the pin as possible. – 5 – CXA3106Q Description ...
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... IOGND – 6 – CXA3106Q Description External VCO input. Programmable counter test input (switchable by a control register). When using the VCO PECL input, open the Pin 5 VCO TTL input. External inverted VCO input. When open, this pin goes to the PECL threshold voltage (IOVcc – ...
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... Control Register Table and Control Timing Chart.) Programmable counter test input. This pin is normally open status and high. Register contents can be loaded immediately to Programmable counter by setting TLOAD low during the programmable counter test mode. – 7 – CXA3106Q Description ...
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... I/O Timing Chart.) TTL output can be turned ON/OFF (high impedance control register. Delay sync signal output. (See the I/O Timing Chart.) TTL output can be turned ON/OFF (high impedance) and switched between positive/negative polarity by a control register. – 8 – CXA3106Q Description ...
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... IOGND – 9 – CXA3106Q Description Unlock signal output. This pin is an open collector output, and pulls in the current when a phase difference occurs. The UNLOCK sensitivity can be adjusted by connecting a capacitor and resistors to this output as appropriate. (See the UNLOCK Timing Chart.) TTL output can be turned ON/OFF (high impedance control register ...
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... CC VCOV VCOGND IRGND 100 IOGND – 10 – CXA3106Q Description PECL reference voltage. When used, ground this pin to the ground pattern with a 0.1µF ceramic chip capacitor as close to the pin as possible. Charge pump current preparation. Connect to GND via an external resistor (1.6k ). Ground this pin to the ground pattern with a 0.1µ ...
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... CXA3106Q ...
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... IOV – 1.6V –200 2.7V –200 0.5V –500 PECLV 330 –1 330 RL = 330 CL = 10pF 2 10pF – 12 – CXA3106Q (Ta = 25° 5V, GND = 0V) CC Typ. Max. Unit 67 100 IOV CC V –1.5 IOV CC V –1.3 100 µA 0 µ ...
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... DIV = 1/1 40 DIV = 1/2 20 DIV = 1/4 10 2.0 DIV = 1/1 200 DIV = 1/2 100 DIV = 1/4 50 C.Pump Bit = 00, 80 IREF = 1.6k C.Pump Bit = 10, 350 IREF = 1.6k C.Pump Bit = 11, 1350 IREF = 1.6k – 13 – CXA3106Q Typ. Max. Unit mA 100 kHz 2 bit 4 CLK 5 bit 20/16 CLK 120 MHz 60 MHz 30 MHz 4.4 V 320 550 Mrad/sv 160 ...
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... DIV = 1/4 10 10% to 90%, 1 330 10% to 90%, 1 330 DIV = 1/1 40 DIV = 1/2 20 DIV = 1/4 10 10% to 90%, 2 10pF 10% to 90%, 2 10pF CL = 10pF 10pF CL = 10pF 1 10pF 0 10pF CL = 10pF CL = 10pF 1.5 – 14 – CXA3106Q Typ. Max. Unit 120 MHz 60 MHz 30 MHz 1.5 2.0 ns 1.5 2 MHz 60 MHz 30 MHz 3.0 4.0 ns 3.0 4 ...
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... N = 1040 triggered at SYNC Fsync = 56.48kHz (Crystal) Fclk = 75.00MHz N = 1328 triggered at DSYNC in write/read mode in write mode 3 in write mode 0 in write mode 3 in read mode 0 in read mode 3 in read mode 0 – 15 – CXA3106Q Typ. Max. Unit 4.0 7.0 ns 3.0 5.0 ns 2.0 3.0 ns 1.6 2 MHz ns ns ...
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... PD POL = 1. Phase comparison is performed at the edges. The input circuit of the phase detector does not contain a hysteresis circuit, so the waveform must be shaped at the front end of the CXA3106Q when inputting a noisy signal. The phase detector HOLD signal is supplied by TTL. (See the HOLD Timing Chart.) The PLL UNLOCK signal is output by an open collector ...
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... ON OFF 1 0 OFF ON 00001 · · · · · · · · · · · · 2/16CLK · · · · · · · · · · · · 2CLK 3CLK 1 0 Negative – 17 – CXA3106Q 10011 20/16CLK 11 4CLK ...
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... Power save with register contents held Register read function power ON/OFF Programmable counter TTL output OFF function Power Save The CXA3106Q realizes 2-step power saving (all OFF, control registers only ON). This is controlled by a control register and the chip selector. Step 1: Chip selector control CS ...
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... This is the programmable counter test signal input pin. This pin can be switched internally by the MUX circuit. TTL and PECL input are possible. This pin is normally not used. Register: VCO By-pass Input status Internal VCO Function External input – 19 – CXA3106Q ...
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... Control Register Timing 1) Write mode Many CXA3106Q functions can be controlled via a program. Characteristics are changed by setting the internal control register values via a serial interface comprised of three pins: SENABLE (Pin 10), SCLK (Pin 11) and SDATA (Pin 12). The write timing diagram is shown below. Input the 8-bit data and 3-bit register address MSB first to the SDATA pin. Some registers are not 8 bits, but the data is input aligned with the LSB side in these cases ...
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... DIVREG2 (upper 4 bits of VCODIV) CENFREREG (2 bits of DIV1 DIVREG1 (lower 8 bits of VCODIV) All three of the above registers must be changed even when changing only (2 bits of DIV1, 2, 4). This is the same when changing only (12 bits of VCODIV). SENABLE SDATA SCLK DIVREG2 CENFREREG DIVREG1 – 21 – CXA3106Q ...
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... BIT DATA 3 BIT ADDRESS 7 DATA REGISTERS (41 LATCHES). REGISTERS ARE DIFFERENT LENGTHS BIT SCAN PATH, 1 ELEMENT PER REGISTER BIT Block Diagram during Read Mode READ NO. 1 READ NO Timing Chart during Read Mode – 22 – CXA3106Q SEROUT TNENH READ NO ...
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... Thh Ths T hold The phase comparison output is held and fixed VCO output frequency is output 1nA 1ms 0.33µF, and KVCO = 2 · 50MHz/V, then: leak hold –6 – [V] – · 151 [Hz] – 24 – CXA3106Q Thh Ths ...
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... S2 signal falls below the threshold level of the next inverter, the UNLOCK signal goes from low to high, and the PLL is said to be unlocked UNLOCK Inside the IC Outside the unlock I1 detect – 25 – CXA3106Q R2 UNLOCK C threshold level threshold level threshold level ...
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... Charge Pump and Loop Filter Settings The CXA3106Q's charge pump is a constant-current output type as shown below LPF 1/S + – 1/S The PLL closed loop transmittance is obtained by the following formula. o/N KPD · F (S) · KVCO · 1/N · 1 KPD · F (S) · KVCO · 1/N · 1/S ...
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... VCO. In addition to this, however, the loop filter also plays an important element in determining the PLL response characteristics. Typical examples of loop filters include lag filters, lag-lead filters, active filters, etc. However, the CXA3106Q's LPF is a current input type active filter as shown below, so the following calculations show an actual example of deriving the PLL closed loop transmittance when using this type of filter and then using this transmittance to create a formula for setting the filter constants ...
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... S ( · · · C2 · Here, assuming C2 = C1/100, then: C1 · C1/100 · C1/100 · R 101 101 Vo The Bode diagram for formula ( follows. .................. (7) –90 – 28 – CXA3106Q log w log w 0 –45deg ...
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... Next, the various parameters inside an actual CXA3106Q are obtained. The CXA3106Q's charge pump output block and the LPF circuit are as follows 100µA or 400µA or 1600µA 100µA or 400µA or 1600µA First, KPD is as follows. KPD = 100µ/2 or 400µ/2 or 1600µ/2 Typical KVCO characteristics curves for the CXA3106Q's internal VCO are as follows ...
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... CXA3106Q setting µF kHzrad kHz 780 0.33 3300 4.41 0.70 2.40 1170 0.33 3300 3.60 0.57 1.96 1560 0.33 3300 4.41 0.70 2.40 940 0.33 3300 4.01 0.64 2.19 1410 0.33 3300 3.28 0.52 1.78 1880 0.33 3300 4 ...
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... CLK Jitter Evaluation Method The regenerated CLK is obtained by applying Hsync to the CXA3106Q. Apply this CLK to a digital oscilloscope and observe the CLK waveform using Hsync as the trigger. Hsync Pulse Generator H Sync Computer signal Hsync CLK Enlarged Trigger The CLK jitter is measured at peak to peak in the long-term write mode of the digital oscilloscope as shown in the figure ...
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... SVGA 1056, DIV = 1/ XGA 1344, DIV = 1/ 3.0 VGA 2.5 SVGA 2.0 XGA 1.5 1 Output Frequency [MHz] – 32 – CXA3106Q K characteristics VCO Ta = –25° +25° +75°C 2.5 3.0 3.5 4.0 4.5 Vrc2 Control Voltage [V] Fine Delay Td2 vs. Fine Delay Bit Ta = –25° +25° +75°C 5 ...
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... Ground the power supply pins of the IC with a 0.1µF or larger ceramic chip capacitor as close to each pin as possible. • Be sure to accurately match the I/O characteristic impedance in order to ensure sufficient performance during high-speed operation. • Design the set so that the loop filter (external) is located at the minimum distance. (See the CXA3106Q PWB.) – 33 – CXA3106Q ...
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... PECL level output pins 330 Control Register HOLD SYNCH, SYNCL: PECL level complementary input – 34 – CXA3106Q 25 DSYNC 24 CLK 23 CLKN 22 CLK/2 21 CLK/ DGND 100k UNLOCK output 100 UNLOCK 17 10nF DIVOUT ...
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... The loop filter's capacitors and resistor should also be temperature compensated Control Register HOLD SYNC: TTL level input – 35 – CXA3106Q 25 TTL level output pins DSYNC 24 CLK 23 CLKN 22 CLK/2 21 CLK/2N 20 DGND 100k 100 UNLOCK output UNLOCK 17 ...
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... When connecting the PLL output to A/D converters with built-in demultiplex function such as the CXA3026AQ/CXA3026Q/CXA3086Q (Sony), a simple system can be configured by connecting the CLK (PECL) and CLKN (PECL) outputs of the CXA3106Q to the CLK (PECL) and CLKN (PECL) inputs of each A/D converter, respectively, and the 1/2 CLK (PECL) and 1/2 CLKN (PECL) outputs of the CXA3106Q to the RESETN (PECL) and RESET (PECL) inputs of each A/D converter, respectively ...
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... A/D converters from different lots, and are defined for all operating temperatures and all operating supply voltages. See the CXA3026Q/CXA3026AQ/CXA3086Q specifications for a detailed description.) • Within the CMOS LOGIC at the rear end of the A/D converters DSYNC signal from CXA3106Q vs. A/D converter 1/2 clock output The setup time is T–3ns and the hold time is T–5ns. CXA3106Q ...
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... Connecting the CXA3106Q with Sony ADC (Straight Mode) When connecting the PLL output to A/D converters such as the CXA3026AQ/CXA3026Q/CXA3086Q (Sony), a simple system can be configured as shown below. Wiring Diagram PLL CXA3106Q VIN CLK (PECL) TTL CLKN (PECL) ADC CXA3026AQ CXA3026Q CXA3086Q ...
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... See the CXA3026Q/CXA3026AQ/CXA3086Q specifications for a detailed description.) • Within the CMOS LOGIC at the rear end of the A/D converters DSYNC signal from CXA3106Q vs. clock output from CXA3106Q The setup time is T–4.5ns and the hold time is 1.5ns. CXA3106Q ...
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... CXA3106Q-PWB (CXA3106Q Evaluation Board) The CXA3106Q-PWB is an evaluation board for the CXA3106Q PLL-IC. This board makes it possible to easily evaluate the CXA3106Q's performance using the supplied control program (Note: IBM PC/AT, MS-DOS 5.0 and newer US mode specifications). Features • Two input level (TTL and PECL) SYNC input • ...
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... PECL outputs (VBB, DSYNCH, DSYNCL, CLKH, CLKL, CLK/2H, CLK/2L) are output constantly, but TTL outputs (DSYNC, CLK, CLKN, CLK/2, CLK/2N, SEROUT, DIVOUT, UNLOCK) are controlled by the respective control registers. Therefore, the enable/disable settings should be made in accordance with the application. See the following pages for the setting method. – 41 – CXA3106Q ...
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... Power Save, connect the jumper wire to S5 (CS = low). (For the initial setting, the jumper wire is connected to S6.) Supplied Program This PWB is equipped with a control program that facilitates evaluation of the CXA3106Q. Operation methods and precautions are as follows. 1) Compatible personal computers Use an IBM PC/AT or compatible machine equipped with a 25-pin D-SUB parallel port (printer port). Also, operating systems which support the program are MS-DOS 5 ...
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... Use Pg Up and increment/decrement divisor and fine delay registers. Press a to abort scan registers CXA3106 PLL REGISTERS Divisor 1344 Divider 2 Fine Delay Charge Pump 10 Power SCAN SYNTH OFF ON DSYNC CLK2 NCLK2 OFF OFF OFF MIXED SIGNAL SYSTEMS JAN 1997 – 43 – CXA3106Q 10 VCO Bypass ON CLK1 NCLK1 OFF OFF ...
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... Return or Enter key. (Note: The operating range of the CXA3106Q is from 256 to 4096.) The value can also be incremented or decremented by one step by pressing the Page Up or Page Down key, respectively. ...
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... VCO Bypass: This is set to OFF when testing the program counter. This should normally be set to ON. O/P Enable These are the enable/disable settings for each TTL output (DIVOUT, UNLOCK, DSYNC, CLK2, NCLK2, CLK1 and NCLK1). Set to ON when performing evaluation using TTL output. – 45 – CXA3106Q ...
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... C) Description of readout mode This program has a function (readout mode) that reads the contents written to the control registers from the CXA3106Q SEROUT (Pin 15) and displays these contents on the screen. This function is described below. 1) Set SCAN the function setting screen. 2) Press the S key. ...
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... Substrate Pattern (parts surface) Substrate Pattern (solder surface) – 47 – CXA3106Q ...
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... VCO VCOL VCOH BNC3 BNC2 BNC1 CXA3106Q PCB v1.1 BNC4 SYNCH S1 S2 BNC5 SYNCL IC1 BNC6 SYNC PR2 PR3 PR4 PR11 SEROUT DIVOUT UNLOCK CLK/2N Silk Screen (parts surface Silk Screen (solder surface) – 48 – ...
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... CXA3106Q ...
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... NOTE : PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame). 48PIN QFP (PLASTIC 0.15 0.3 – 0.1 ± 0. 0.35 2.2 – 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT – 50 – CXA3106Q + 0.1 0.15 – 0.05 0.15 + 0.2 0.1 – 0.1 EPOXY RESIN SOLDER / PALLADIUM PLATING COPPER / 42 ALLOY 0.7g ...